TWI573230B - Package structure and its package substrate - Google Patents

Description

Package and its package substrate

The invention relates to a package substrate, in particular to a package substrate and a package used in a semiconductor package process.

In the development of semiconductor packaging, the long-term use of a lead frame as a carrier for carrying an active component is mainly due to its low manufacturing cost and high reliability. However, with the rapid development of the electronics industry, electronic products tend to be light and thin in terms of type, and in terms of functions, they are oriented toward high-performance, high-function, and high-speed research and development. Therefore, in order to meet the high integration and miniaturization requirements of semiconductor devices, the packaging process is gradually replacing the lead frame with a package substrate having a high density and fine pitch line.

As shown in FIG. 1A, the conventional package substrate 1 includes a dielectric structure 10, a first wiring layer 11 and a second wiring layer 12 disposed on the dielectric structure 10, and the dielectric structure 10 has a core layer 100. And a plurality of first dielectric layers 101 and a plurality of second dielectric layers 102 respectively disposed on opposite sides of the core layer 100, and the plurality of conductive vias 120 are electrically connected to the first and second layers Circuit layers 11, 12. In the packaging process, the semiconductor active device 13 is disposed on the first dielectric layer 101 and is wire-bonded (or flip-chip) The first circuit layer 11 is electrically connected, and the semiconductor active device 13 is covered with an encapsulant 14 to form a package.

However, the thickness of the conventional package substrate 1 is extremely thin and presents a full-faceted surface pattern in the process, and the materials and thicknesses of the first and second dielectric layers 101, 102 are the same, so in the packaging process, the package substrate 1 in the temperature cycle, it is easy to warp the package substrate 1 due to the difference in thermal expansion coefficient (CTE Mismatch) between the semiconductor active device 13 (or the encapsulant 14). Case (dashed outline shown in Fig. 1A) or recessed condition (dashed outline of package substrate 1' shown in Fig. 1B), resulting in poor planarity of the package, so that it occurs when the board is subsequently connected Non-sticking (Non wetting) problems, but the electrical connection is not good.

Moreover, the warpage also causes the semiconductor active device 13 to be chipped, resulting in a decrease in product yield.

Further, if the thickness of the dielectric layer is increased, the warpage can be slowed down, but the thickness of the package substrate 1 is increased, so that it does not meet the requirements of lightness, thinness, and shortness.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a difficult problem to be overcome in the industry.

The present invention provides a package substrate, comprising: a first circuit structure comprising at least a first dielectric layer and a first circuit layer formed on the first dielectric layer; And the second circuit structure includes at least one second dielectric layer and a second circuit layer formed on the second dielectric layer, and the weight of the first circuit structure is equal to the second circuit The weight of the structure.

In the foregoing package substrate, the first circuit structure is adjacent to the second circuit structure.

The present invention further provides a package substrate, comprising: a core layer having opposite first and second surfaces; a first circuit structure disposed on the first surface of the core layer and including at least one first dielectric a layer and a first circuit layer formed on the first dielectric layer; and a second circuit structure disposed on the second surface of the core layer and including at least one second dielectric layer and formed on the second dielectric layer a second circuit layer on the electrical layer, and the weight of the second circuit structure is equal to the sum of the weights of the core layer and the first circuit structure.

In the above two package substrates, the first circuit structure further comprises an insulating protective layer formed on the first dielectric layer and the first circuit layer.

In the two kinds of package substrates, the second circuit structure further comprises an insulating protective layer formed on the second dielectric layer and the second circuit layer.

The present invention also provides a package comprising: a first circuit structure comprising at least a first dielectric layer and a first circuit layer formed on the first dielectric layer; and a second circuit structure comprising at least one a second dielectric layer and a second circuit layer formed on the second dielectric layer; and a package structure is disposed on the second circuit structure, and the weight of the first circuit structure is equal to the package structure and the first The sum of the weights of the two circuit structures.

In the aforementioned package, the first circuit structure is adjacent to the second circuit structure.

The present invention further provides a package comprising: a core layer having opposite first and second surfaces; and a first circuit structure disposed on the core The first surface of the core layer includes at least a first dielectric layer and a first circuit layer formed on the first dielectric layer; the second circuit structure is disposed on the second surface of the core layer and includes At least a second dielectric layer and a second circuit layer formed on the second dielectric layer; and a package structure is disposed on the second circuit structure, wherein the first circuit structure has a weight equal to the core layer And the sum of the weight of the package structure and the second circuit structure, or the sum of the weights of the first circuit structure and the core layer is equal to the sum of the weights of the package structure and the second circuit structure.

In the foregoing two packages, the first circuit structure further comprises an insulating protective layer formed on the first dielectric layer and the first circuit layer.

In the foregoing two packages, the second circuit structure further comprises an insulating protective layer formed on the second dielectric layer and the second circuit layer.

In the above two packages, the package structure includes at least one electronic component, which is disposed on the second circuit structure and electrically connected to the second circuit layer.

In the foregoing two packages, the package structure further comprises an encapsulation layer covering the electronic component.

The present invention further provides a package comprising: a first circuit structure comprising at least a first dielectric layer and a first circuit layer formed on the first dielectric layer; the first package structure is disposed on the a second circuit structure comprising: at least one second dielectric layer and a second circuit layer formed on the second dielectric layer; and a second package structure disposed on the second circuit structure And the sum of the weights of the first circuit structure and the first package structure is equal to the sum of the weights of the second package structure and the second circuit structure, or the weight of the first package structure is equal to the first circuit structure, the first Two The sum of the weight of the mounting structure and the second circuit structure.

In the aforementioned package, the first circuit structure is adjacent to the second circuit structure.

The present invention further provides a package comprising: a core layer having opposite first and second surfaces; a first circuit structure disposed on the first surface of the core layer and including at least one first dielectric And a first circuit layer formed on the first dielectric layer; a first package structure is disposed on the first circuit structure; and a second circuit structure is disposed on the second surface of the core layer and includes At least a second dielectric layer and a second circuit layer formed on the second dielectric layer; and a second package structure disposed on the second circuit structure, wherein the first circuit structure and the first The sum of the weights of the package structures is equal to the sum of the weights of the core layer, the second package structure and the second circuit structure.

In the foregoing two packages, the first circuit structure further comprises an insulating protective layer formed on the first dielectric layer and the first circuit layer.

In the foregoing two packages, the second circuit structure further comprises an insulating protective layer formed on the second dielectric layer and the second circuit layer.

In the above two packages, the first package structure includes at least one electronic component disposed on the first circuit structure and electrically connected to the first circuit layer. For example, the first package structure further comprises an encapsulation layer covering the electronic component.

In the above two packages, the second package structure includes at least one electronic component, which is disposed on the second circuit structure and electrically connected to the first circuit layer. For example, the second package structure further comprises an encapsulation layer covering the electronic component.

It can be seen from the above that in the package substrate and the package of the present invention, the overall structure is divided into two parts, and the weight of one part is equal to the weight of the other part, so that the neutral axis is in the shape of the package substrate (or package). At the center of the heart or at the center of gravity, to reduce the deformation of the package substrate (or package).

1,1',2,2',2",3,3',4,4'‧‧‧ package substrate

10‧‧‧Dielectric structure

100, 20, 30, 40‧‧‧ core layer

101,210,210',310,410‧‧‧First dielectric layer

102,220,220',320,420‧‧‧second dielectric layer

11,211,211',311,411‧‧‧First circuit layer

12,221,221',321,421‧‧‧second circuit layer

120‧‧‧ conductive through holes

13‧‧‧Active components

14‧‧‧Package colloid

20a‧‧‧ first surface

20b‧‧‧second surface

200,300,400‧‧‧conductive blind holes

21, 21’, 31, 41‧‧‧ first circuit structure

212,312,412‧‧‧first insulation protection layer

22,22’,32,42‧‧‧second circuit structure

222,322,422‧‧‧Second insulation protection layer

3a, 3a’, 3a”, 3b, 4a, 4a’‧‧‧Package

33,33’,33”‧‧‧Package structure

330,430,440‧‧‧Electronic components

331,431,441‧‧‧Encapsulation layer

34‧‧‧Electrical bumps

34’‧‧‧welding line

35‧‧‧Conducting components

43‧‧‧First package structure

44‧‧‧Second package structure

t,d,h,h’,r,r’‧‧‧ thickness

1A is a schematic cross-sectional view of a conventional semiconductor package; FIG. 1B is a schematic cross-sectional view of a conventional package substrate; and 2 and 2' are different states of the first embodiment of the package substrate of the present invention; 2A to 2C are schematic cross-sectional views showing a method of fabricating a second embodiment of the package substrate of the present invention; and FIG. 3A is a cross-sectional view showing a first embodiment of the package of the present invention; 3A' and 3A' are diagrams of other embodiments of FIG. 3A; FIG. 3B is a schematic cross-sectional view of a second embodiment of the package of the present invention; and FIG. 4 is a package of the present invention A cross-sectional view of a third embodiment; wherein the 4'th image is another embodiment of FIG.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. Limited The conditions are not technically meaningful, and any modification of the structure, change of the proportional relationship or adjustment of the size should remain in the present invention without affecting the effects and the achievable objectives of the present invention. The technical content revealed can be covered. In the meantime, the terms "upper", "one", "first" and "second" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

The second and second views are schematic cross-sectional views of the first embodiment of the package substrate 2, 2' of the present invention.

As shown in FIG. 2, the package substrate 2 is a coreless state, and includes: a first circuit structure 21 and a second circuit structure 22, and the weight of the first circuit structure 21 is equal to the second The weight of the circuit structure 22.

The first circuit structure 21 includes at least a first dielectric layer 210 and a first circuit layer 211 formed on the first dielectric layer 210.

The second circuit structure 22 includes at least one second dielectric layer 220 and a second circuit layer 221 formed on the second dielectric layer 220, and selectively forms at least one conductive via hole 200. The first and second circuit layers 211, 221 are electrically connected to the first and second dielectric layers 210, 220.

In this embodiment, the first circuit structure 21 has a single first dielectric layer 210, and the second circuit structure 22 has a single second dielectric layer 220, that is, the package substrate 2 has two dielectric layers. And pressing the first dielectric layer 210 and the second dielectric layer 220 to make the first circuit structure 21 and the first The two circuit structures 22 are adjacent.

Moreover, the thickness t of the first circuit structure 21 is equal to or different from the thickness d of the second circuit structure 22.

Therefore, the package substrate 2 of the present embodiment has a weight equal to the weight of the second circuit structure 22 by the first circuit structure 21 (for example, by adjusting the thickness t of the first circuit structure 21 and the second circuit structure 22) The thickness d) is such that a neutral axis is located in the middle of the package substrate 2, thereby reducing the probability that the package substrate 2 will warp as shown in FIG. 1B. Wherein, the intermediate position is at the centroid or center of gravity of the package substrate 2.

Moreover, as shown in FIG. 2', the package substrate 2' may be a core pattern including a core layer 20 having a first surface 20a and a second surface 20b opposite to each other. The circuit structure 21 is disposed on the first surface 20a of the core layer 20, and the second circuit structure 22 is disposed on the second surface 20b of the core layer 20, wherein the weight of the second circuit structure 22 is equal to the core layer 20 is summed with the weight of the first circuit structure 21.

Therefore, the weight of the second circuit structure 22 is equal to the sum of the weights of the core layer 20 and the first circuit structure 21, so that the neutral axis is located at the middle of the package substrate 2', thereby lowering the package substrate 2 'The probability of warping. Wherein, the intermediate position is at the centroid or center of gravity of the package substrate 2'.

2A to 2C are the manufacturing method of the second embodiment of the package substrate 2" of the present invention. The second embodiment is substantially the same as the first embodiment. The main difference lies in the number of layers of the circuit structure, so the following details Different, not jealous Said the same place.

As shown in FIG. 2A, a dielectric structure such as a first dielectric layer 210 and a second dielectric layer 220 are stacked.

As shown in FIG. 2B, a first wiring layer 211 is formed on the first dielectric layer 210, and a second wiring layer 221 is formed on the second dielectric layer 220.

As shown in FIG. 2C, the first dielectric layer 210' and the first circuit layer 211' are repeatedly formed on the first dielectric layer 210 and the first circuit layer 211, so that the first circuit structure 21' has a complex interface. And the second dielectric layer 220 ′ and the second circuit layer 221 ′ are formed on the second dielectric layer 220 and the second circuit layer 221 , so that the second circuit structure 22 ′ has a plurality of dielectric layers Electrical layer and circuit layer.

In this embodiment, the first circuit structure 21 ′ further includes a first insulating protective layer 212 such as a solder resist layer formed on the first dielectric layer 210 ′ and the first wiring layer 211 ′, and the second The circuit structure 22' further includes a second insulating protective layer 222 such as a solder resist layer formed on the second dielectric layer 220' and the second wiring layer 221'.

Furthermore, the thicknesses r, r' of the first dielectric layers 210, 210' are equal or unequal to the thicknesses h, h' of the second dielectric layers 220, 220', as shown in the following table.

Therefore, the weight of the first circuit structure 21' is equal to the weight of the second circuit structure 22' such that the neutral axis is located in the middle of the package substrate 2" Position, thereby reducing the probability of warpage of the package substrate 2", wherein the intermediate position is at the centroid or center of gravity of the package substrate 2".

Please refer to Figures 3A, 3A' and 3A" for a cross-sectional view of a first embodiment of the package of the present invention.

As shown in FIGS. 3A and 3A', the package 3a of the present invention comprises: a package substrate 3, and a package structure 33, 33' disposed on the package substrate 3, and the package substrate 3 has a first circuit structure. 31 and the second circuit structure 32.

In this embodiment, the package substrate 3 is in a coreless manner, so the first circuit structure 31 is adjacent to the second circuit structure 32.

The first circuit structure 31 includes at least a first dielectric layer 310, a first circuit layer 311 formed on the first dielectric layer 310, and a first dielectric layer 310 and the first A first insulating protective layer 312 on the wiring layer 311.

In the embodiment, the first insulating protection layer 312 exposes the first circuit layer 311, so that the exposed first circuit layer 311 is bonded to the conductive component 35 such as a solder ball, so the outer side of the first circuit structure 31 It is used as a ball-planting side.

The second circuit structure 32 includes at least one second dielectric layer 320, a second circuit layer 321 formed on the second dielectric layer 320, and a second dielectric layer 320 and the second layer. A second insulating protective layer 322 is disposed on the circuit layer 321 , and a plurality of conductive vias 300 are selectively formed in the first and second dielectric layers 310 , 320 to electrically connect the first and second circuit layers 311 , 321 .

In the embodiment, the second insulating layer 322 exposes the second circuit layer 321 so that the exposed second circuit layer 321 is electrically coupled to the package structure 33, 33', so the second circuit structure 32 Used as a crystallizing side. However, the crystallizing side and the ball-planting side are determined according to the process, and are not limited to the above.

Furthermore, the first circuit structure 31 has a plurality of first dielectric layers 310, and the second circuit structure 32 has a single second dielectric layer 320, such that the thickness of the first circuit structure 31 and the second circuit The thickness of the structure 32 is not equal; of course, the thickness of the first circuit structure 31 and the thickness of the second circuit structure 32 may be equal.

The package structure 33 is disposed on the second circuit structure 32, and the weight of the first circuit structure 31 is equal to the sum of the weights of the package structures 33, 33' and the second circuit structure 32.

In this embodiment, as shown in FIG. 3A, the package structure 33 includes at least one electronic component 330 disposed on the second circuit structure 32 and electrically connected to the second circuit layer 320. Specifically, the electronic component 330 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor.

In another embodiment, as shown in FIG. 3A, the package structure 33' includes at least one electronic component 330 and an encapsulation layer 331 covering the electronic component 330. Specifically, the encapsulation layer 331 is formed on the second circuit structure 32 to encapsulate the electronic component 330.

In addition, the electronic component 330 is provided on the second circuit structure 32 in a flip chip manner, that is, the second conductive line 34 is electrically connected to the second circuit. Layer 321. However, in other embodiments, the electronic component 330 can also be packaged by a wire bonding method, such as the package 3a" shown in FIG. 3A", that is, the electronic component 330 is electrically connected to the second line by using a bonding wire 34'. The layer 321; or the electronic component 330 may be embedded in the second dielectric layer 320 (not shown).

Therefore, the weight of the first circuit structure 31 is equal to the weight of the package structures 33, 33' and the second circuit structure 32 such that the neutral axis is located between the packages 3a, 3a', 3a". Thereby, the probability of warping of the package 3a, 3a', 3a" is reduced. Wherein, the intermediate position is at the centroid or center of gravity of the package 3a, 3a', 3a".

Please refer to FIG. 3B , which is a schematic cross-sectional view of a second embodiment of the package of the present invention. This embodiment is substantially the same as the first embodiment of the package. The main difference lies in the aspect of the package substrate, so the following detailed description Different places, and no longer repeat the same place.

As shown in FIG. 3B, the package substrate 3' of the package 3b further includes a core layer 30, and the first and second circuit structures 31, 32 are respectively disposed on the first and second surfaces of the core layer 30. At least one conductive via 300 is selectively formed in the core layer 30 to electrically connect the first and second circuit layers 311, 321 .

In this embodiment, the first circuit structure 31 has a single first dielectric layer 310, and the second circuit structure 32 has a plurality of second dielectric layers 320, such that the thickness of the first circuit structure 31 is The thickness of the second circuit structure 32 is not equal; of course, the thickness of the first circuit structure 31 and the thickness of the second circuit structure 32 may be equal.

Moreover, the weight of the first circuit structure 31 is equal to the sum of the weight of the core layer 30, the package structure 33" and the second circuit structure 32. Alternatively, the sum of the weights of the first circuit structure 31 and the core layer 30 is equal to The package structure 33" is summed with the weight of the second circuit structure 32.

Therefore, the weight of the first circuit structure 31 is equal to the sum of the weight of the core layer 30, the package structure 33" and the second circuit structure 32 (or by the weight of the first circuit structure 31 and the core layer 30) The sum is equal to the sum of the weights of the package structure 33" and the second circuit structure 32 such that the neutral axis is located in the middle of the package 3b, thereby reducing the probability of warping of the package 3b. Wherein, the intermediate position is at the centroid or center of gravity of the package 3b.

Please refer to FIG. 4, which is a cross-sectional view showing a third embodiment of the package of the present invention. This embodiment is substantially the same as the above embodiment of the package. The main difference is that the first circuit structure is provided with a package structure. Therefore, the differences will be described in detail below, and the same portions will not be described again.

As shown in FIG. 4, the package 4a of the present invention comprises: a package substrate 4, and a first package structure 43 and a second package structure 44 respectively disposed on the lower side of the package substrate 4, and the package The substrate 4 has a first circuit structure 41 and a second circuit structure 42.

In this embodiment, the package substrate 4 is in a coreless state, so the first circuit structure 41 is adjacent to the second circuit structure 42.

The first circuit structure 41 includes at least a first dielectric layer 410, a first circuit layer 411 formed on the first dielectric layer 410, and a shape A first insulating protective layer 412 is formed on the first dielectric layer 410 and the first wiring layer 411.

In the embodiment, the first insulating layer 412 exposes the first circuit layer 411 for electrically connecting the exposed first wiring layer 411 to the first package structure 43.

The second circuit structure 42 includes at least a second dielectric layer 420, a second circuit layer 421 formed on the second dielectric layer 420, and a second dielectric layer 420 and the second layer. A second insulating protective layer 422 on the wiring layer 421.

In the embodiment, the second insulating layer 422 exposes the second circuit layer 421 to electrically expose the exposed second wiring layer 421 to the second package structure 44.

The first package structure 43 is disposed on the first circuit structure 41. In this embodiment, the first package structure 43 includes at least one electronic component 430 and an encapsulation layer 431 covering the electronic component 430. The electronic component 430 is electrically connected to the first circuit structure 41. The first circuit layer 410. For the type of electronic component 430, reference may be made to the above.

The second package structure 44 is disposed on the second circuit structure 42. In this embodiment, the second package structure 44 includes at least one electronic component 440 and an encapsulation layer 441 covering the electronic component 440. The electronic component 440 is disposed on the second circuit structure 42 and electrically connected. The second circuit layer 420. The types of electronic components 440 can be referred to above.

Moreover, the sum of the weights of the first circuit structure 41 and the first package structure 43 is equal to the weight of the second package structure 44 and the second circuit structure 42. The sum of the quantities. Alternatively, the weight of the first package structure 43 is equal to the sum of the weights of the first circuit structure 41, the second package structure 44, and the second circuit structure 42.

Therefore, the sum of the weights of the first circuit structure 41 and the first package structure 43 is equal to the sum of the weights of the second package structure 44 and the second circuit structure 42 (or the weight of the first package structure 43 is equal to The first circuit structure 41, the sum of the weights of the second package structure 44 and the second circuit structure 42 are such that the neutral axis is located at the middle of the package 4a, thereby reducing the warpage of the package 4a. Probability. Wherein, the intermediate position is at the centroid or center of gravity of the package 4a.

In addition, as shown in FIG. 4', the package substrate 4' may also have a core. Therefore, the package substrate 4' further includes a core layer 40 sandwiched between the first circuit structure. The first circuit structure 41 is electrically connected to the first and second circuit layers 411, 421, and the first circuit structure 41 is electrically connected to the second circuit structure 42 and the at least one conductive via 400 is selectively formed in the core layer 40. The sum of the weights of the first package structure 43 is equal to the sum of the weights of the core layer 40, the second package structure 44 and the second circuit structure 42.

Therefore, the sum of the weights of the first circuit structure 41 and the first package structure 43 is equal to the sum of the weights of the core layer 40, the second package structure 44 and the second circuit structure 42 so that the neutral axis is located at the The middle position of the package 4a', thereby reducing the probability of warpage of the package 4a'. Wherein, the intermediate position is at the centroid or center of gravity of the package 4a'.

In summary, the package of the present invention and its package substrate are divided into two parts by the whole structure, and the weight of one part is equal to the other part. The weight is such that the neutral axis is located at the centroid or center of gravity of the package substrate (or package) to reduce the deformation of the package substrate (or package).

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Package substrate

200‧‧‧conductive blind hole

21‧‧‧First circuit structure

210‧‧‧First dielectric layer

211‧‧‧First line layer

22‧‧‧Second circuit structure

220‧‧‧Second dielectric layer

221‧‧‧second circuit layer

t,d‧‧‧thickness

Claims (21)

A package substrate includes: a first circuit structure including at least a first dielectric layer and a first circuit layer formed on the first dielectric layer; and a second circuit structure including at least one second And an electrical layer and a second circuit layer formed on the second dielectric layer, and the weight of the first circuit structure is equal to the weight of the second circuit structure. The package substrate of claim 1, wherein the first circuit structure is adjacent to the second circuit structure. A package substrate comprising: a core layer having opposite first and second surfaces; a first circuit structure disposed on the first surface of the core layer and comprising at least one first dielectric layer and formed on a first circuit layer on the first dielectric layer; and a second circuit structure disposed on the second surface of the core layer and including at least one second dielectric layer and formed on the second dielectric layer a second circuit layer, and the weight of the second circuit structure is equal to the sum of the weights of the core layer and the first circuit structure. The package substrate of claim 1 or 3, wherein the first circuit structure further comprises an insulating protective layer formed on the first dielectric layer and the first circuit layer. The package substrate of claim 1 or 3, wherein the second circuit structure further comprises an insulating protective layer formed on the second dielectric layer and the second circuit layer. A package comprising: a first circuit structure comprising at least a first dielectric layer and a first circuit layer formed on the first dielectric layer; and a second circuit structure comprising at least a second dielectric And a second circuit layer formed on the second dielectric layer; and a package structure is disposed on the second circuit structure, and the weight of the first circuit structure is equal to the package structure and the second circuit structure The sum of the weights. The package of claim 6, wherein the first circuit structure is adjacent to the second circuit structure. A package comprising: a core layer having opposite first and second surfaces; a first circuit structure disposed on the first surface of the core layer and comprising at least one first dielectric layer and formed on a first circuit layer on the first dielectric layer; a second circuit structure disposed on the second surface of the core layer and including at least a second dielectric layer and a second dielectric layer a second circuit layer; and a package structure is disposed on the second circuit structure, wherein the weight of the first circuit structure is equal to the core layer, the sum of the weights of the package structure and the second circuit structure, or the first circuit The sum of the weight of the structure and the core layer is equal to the sum of the weights of the package structure and the second circuit structure. The package of claim 6 or 8, wherein the The first circuit structure further comprises an insulating protective layer formed on the first dielectric layer and the first circuit layer. The package of claim 6 or 8, wherein the second circuit structure further comprises an insulating protective layer formed on the second dielectric layer and the second circuit layer. The package of claim 6 or 8, wherein the package structure comprises at least one electronic component disposed on the second circuit structure and electrically connected to the second circuit layer. The package of claim 11, wherein the package structure further comprises an encapsulation layer covering the electronic component. A package includes: a first circuit structure including at least a first dielectric layer and a first circuit layer formed on the first dielectric layer; and a first package structure disposed on the first circuit structure The second circuit structure includes at least a second dielectric layer and a second circuit layer formed on the second dielectric layer; and a second package structure is disposed on the second circuit structure, and the The sum of the weights of the first circuit structure and the first package structure is equal to the sum of the weights of the second package structure and the second circuit structure, or the weight of the first package structure is equal to the first circuit structure, the second package structure and The sum of the weights of the second circuit structure. The package of claim 13, wherein the first circuit structure is adjacent to the second circuit structure. A package comprising: The core layer has a first surface and a second surface; the first circuit structure is disposed on the first surface of the core layer and includes at least one first dielectric layer and is formed on the first dielectric layer a first circuit layer; the first package structure is disposed on the first circuit structure; the second circuit structure is disposed on the second surface of the core layer and includes at least a second dielectric layer and is formed thereon a second circuit layer on the second dielectric layer; and a second package structure is disposed on the second circuit structure, wherein a sum of weights of the first circuit structure and the first package structure is equal to the core layer, The sum of the weights of the second package structure and the second circuit structure. The package of claim 13 or 15, wherein the first circuit structure further comprises an insulating protective layer formed on the first dielectric layer and the first circuit layer. The package of claim 13 or 15, wherein the second circuit structure further comprises an insulating protective layer formed on the second dielectric layer and the second wiring layer. The package of claim 13 or claim 15, wherein the first package structure comprises at least one electronic component disposed on the first circuit structure and electrically connected to the first circuit layer. The package of claim 18, wherein the first package structure further comprises an encapsulation layer covering the electronic component. The package of claim 13 or 15, wherein The second package structure includes at least one electronic component disposed on the second circuit structure and electrically connected to the second circuit layer. The package of claim 20, wherein the second package structure further comprises an encapsulation layer covering the electronic component.