TWI788099B - Electronic package and package substrate thereof - Google Patents

Abstract

An electronic package is provided in which a first insulating layer is disposed on a chip side of a package substrate and a second insulating layer is disposed on an external side of the package substrate, wherein a coefficient of thermal expansion of the first insulating layer is larger than a coefficient of thermal expansion of the second insulating layer, so that stretch of the first insulating layer on the chip side can be used to adjust degree of warpage of the packaging substrate to reduce deformation of the packaging substrate.

Description

Electronic package and its packaging substrate

The present invention relates to a semiconductor package, in particular to a package substrate with embedded traces and an electronic package made thereafter.

With the vigorous development of the electronic industry, electronic products tend to be thinner and smaller in form, and are developing toward high-performance, high-function, and high-speed research and development in terms of function. Therefore, in order to meet the high integration and miniaturization requirements of semiconductor devices, packaging substrates with high-density and fine-pitch circuits are often used in the packaging process.

As shown in FIG. 1A, a conventional packaging substrate 1a includes a core layer 10 having a plurality of conductive pillars 100, a plurality of dielectric layers 11 respectively disposed on opposite sides of the core layer 10, and a plurality of dielectric layers 11 disposed on each of the dielectric layers 11. The wiring layers 12 on the core layer 10 are electrically connected to the wiring layers 12 on opposite sides of the core layer 10 through the plurality of conductive pillars 100 .

However, the conventional packaging substrate 1a includes a core layer 10, so it is difficult to meet the requirements of lightness, thinness and shortness. Therefore, a packaging substrate 1b without a core layer (coreless) has been developed, as shown in FIG. 1B, which includes multiple stacked The dielectric layer 11, and the circuit layer 12 arranged on each of the dielectric layers 11.

However, in the conventional packaging substrate 1b, the material and thickness of each of the dielectric layers 11 are the same, so during the packaging process, when the packaging substrate 1 is subjected to a temperature cycle (temperature cycle), it is easy to warp due to the thickness being too thin. Warpage will cause non-wetting problems in the subsequent placement of semiconductor chips or circuit boards, resulting in poor electrical connections.

On the other hand, if the thickness of the dielectric layer 11 is increased, although the warpage can be alleviated, the thickness of the packaging substrate 1b will be increased, so that it cannot meet the requirement of lightness, thinness and compactness.

Therefore, how to overcome the various problems of the above-mentioned conventional technologies has become an urgent problem to be solved at present.

In view of the various deficiencies of the above-mentioned prior art, the present invention provides a packaging substrate, comprising: a first insulating portion comprising at least one first insulating layer; a second insulating portion comprising at least one second insulating layer, stacked combined on the first insulating part to form an insulating structure, and the insulating structure has opposite crystal placement side and external connection side, so that the first insulating layer is correspondingly disposed on the crystal placement side, and the second insulating layer is corresponding to It is disposed on the external side, wherein the thermal expansion coefficient of the first insulating portion is greater than that of the second insulating portion; and the circuit layer is embedded in the first insulating portion and the second insulating portion.

In the aforementioned packaging substrate, the second insulating portion has a plurality of the second insulating layers. For example, the thermal expansion coefficients of at least two of the plurality of second insulating layers are the same or different. Alternatively, the thermal expansion coefficients of the plurality of second insulating layers decrease or increase towards the outer side.

In the aforementioned packaging substrate, the material forming the first insulating layer is an Ajinomoto build-up film.

In the aforementioned packaging substrate, the material forming the second insulating layer is a prepreg material.

In the aforementioned packaging substrate, the thicknesses of the first insulating layer and the second insulating layer are the same or different.

The aforementioned packaging substrate further includes an insulating protective layer disposed on the first and/or second insulating portion and exposing part of the circuit layer.

The present invention further provides an electronic package, which includes: the above-mentioned package substrate; and electronic components, which are arranged on the die-mounting side and electrically connected to the circuit layer.

In the aforementioned electronic package, a plurality of conductive elements electrically connected to the circuit layer are disposed on the external side.

It can be seen from the above that the packaging substrate of the present invention mainly uses the thermal expansion coefficient of the first insulating layer to be greater than the thermal expansion coefficient of the second insulating layer, so that the expansion and contraction of the first insulating layer on the side where the chip is placed can be used to adjust the package. Therefore, compared with the prior art, the packaging substrate of the present invention does not need to increase the thickness of the insulating layers, and can reduce the warping deformation of the packaging substrate, thereby not only improving product yield, but also enabling Meet the needs of thin and light.

1a, 1b, 2, 3: package substrate

10: Core layer

100: Conductive column

11: Dielectric layer

12,20: line layer

2a, 3a: first insulating part

2b: Second insulating part

20a: crystal side

20b: External side

201: Conductive trace

202: Conductive blind hole

203: Electrical connection pad

204: welding pad

21: The first insulating layer

22,23,24,25: second insulating layer

26a: the first insulation protection layer

26b: the second insulation protection layer

30: Semiconductor wafer

30a: Action surface

30b: Non-active surface

300: electrode pad

31: Conductive bump

32: Conductive element

t: thickness

FIG. 1A is a schematic cross-sectional view of a conventional packaging substrate.

FIG. 1B is a schematic cross-sectional view of another conventional packaging substrate.

FIG. 2A is a schematic cross-sectional view of the packaging substrate of the present invention.

FIG. 2B is a schematic cross-sectional view of the electronic package of the present invention.

FIG. 3 is a schematic cross-sectional view of another embodiment of the packaging substrate of the present invention.

The implementation of the present invention is described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification, for the understanding and reading of those familiar with this technology, and are not used to limit the implementation of the present invention Therefore, it has no technical substantive meaning. Any modification of structure, change of proportional relationship or adjustment of size shall still fall within the scope of this invention without affecting the effect and purpose of the present invention. The technical content disclosed by the invention must be within the scope covered. At the same time, terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the present invention. The change or adjustment of the relative relationship shall also be regarded as the applicable scope of the present invention if there is no substantial change in the technical content.

FIG. 2A is a schematic cross-sectional view of the packaging substrate 2 of the present invention. As shown in FIG. 2A , the packaging substrate 2 is a coreless form, which includes: a first insulating portion 2a, a second insulating portion 2b stacked on the first insulating portion 2a, and At least one circuit layer 20, and the first insulating portion 2a includes at least one first insulating layer, and the second insulating portion 2b includes at least one second insulating layer, in this embodiment, it has a layer of first insulating layer Layer 21 and four second insulating layers 22, 23, 24, 25 are stacked and arranged to form an insulating structure.

The first insulating part 2a is used as the crystal side 20a of the insulating structure, and the second insulating part 2b is used as the outer side 20b of the insulating structure, that is, the first insulating layer 21 is correspondingly arranged on the chip. side 20a, and the second insulating layers 22, 23, 24, 25 are correspondingly arranged on the outer side 20b, wherein the thermal expansion coefficient of the first insulating part 2a (or the first insulating layer 21) (such as at least 4ppm/°C ) is greater than the coefficient of thermal expansion (eg, at most 2 ppm/° C.) of the second insulating portion 2 b (or the second insulating layers 22 , 23 , 24 , 25 ).

In this embodiment, the second insulating part 2b has a plurality of the second insulating layers 22, 23, 24, 25, and their thermal expansion coefficients may be the same or different, but they are all smaller than the first insulating part 2a (or the first absolutely Insulation layer 21) thermal expansion coefficient. For example, the CTEs of the second insulating layers 22 , 23 , 24 , 25 can decrease or increase towards the outer side 20 b.

Furthermore, the material forming the first insulating layer 21 is Ajinomoto Build-up Film (ABF for short) or other high CTE dielectric materials, and the second insulating layers 22, 23 are formed ,24,25 are made of materials such as prepreg (PP for short) or other low CTE dielectric materials.

In addition, the package substrate 2 may include an insulating protection layer such as a solder resist layer, which is disposed on the first and second insulating portions 2a, 2b and exposes the circuit layer 20 for the circuit layer 20 to be combined with other components. For example, the first insulating protection layer 26a is arranged on the first insulating layer 21 and exposes part of the surface of the circuit layer 20, and the second insulating protection layer 26b is arranged on the second insulating layer 25 and exposes the circuit layer. Partial surface of 20.

In addition, the thickness t of the first insulating layer 21 and the second insulating layer 22, 23, 24, 25 can be adjusted according to requirements, and the thickness t of each insulating layer can be the same or different, and the number of insulating layers can be singular or an even number, and is not particularly limited.

The circuit layer 20 is embedded in the first insulating layer 21 and the second insulating layer 22, 23, 24, 25, and includes a plurality of conductive traces 201 and conductive traces 201 electrically connected to each layer. Conductive blind vias 202 . In other words, each of the conductive traces 201 and the conductive blind vias 202 does not protrude from the first insulating layer 21 and the second insulating layer 22 , 23 , 24 , 25 that embed them.

In this embodiment, the circuit layer 20 is provided with a plurality of electrical connection pads 203 corresponding to the die-mounting side 20a, and a plurality of welding pads 204 are disposed corresponding to the external connection side 20b, so that these electrical connections The pads 203 are exposed on the first insulating protection layer 26a, and the pads 204 are exposed on the second insulating protection layer 26b.

Therefore, in the packaging substrate 2 of the present invention, the thermal expansion coefficient of the first insulating layer 21 is greater than the thermal expansion coefficient of the second insulating layer 22, 23, 24, 25, so in the packaging process, the packaging substrate 2 undergoes temperature cycling. , the expansion and contraction of the first insulating layer 21 and the second insulating layer 22, 23, 24, 25 are different, so as to adjust the warping direction and balance the warping degree of the packaging substrate 2 (for example, the packaging substrate 2 can be reduced Figure 1B 10% to 60% of the warping deformation shown), so that the packaging substrate 2 can greatly reduce the warping degree during the temperature rise and fall.

Furthermore, since the warping of the packaging substrate 2 is greatly reduced, the conductive traces 201 will not be too close due to warping, so the circuit layer 20 is conducive to the design of fine pitch/fine lines, so the conductive blind The holes 202, the electrical connection pads 203 and the welding pads 204 can be designed as fine-pitch/thin-line specifications according to requirements, so as to meet the requirements of high-density contacts of semiconductor chips.

Also, since the circuit layer 20 can meet the requirements of fine pitch/fine circuit, under the same amount of wiring, the amount of metal material used to make the circuit layer 20 in the package substrate 2 is less than that used in the conventional package substrate 1b. The amount of metal material used in the circuit layer 12 can reduce the manufacturing cost of the packaging substrate 2 .

In addition, since the dielectric material with a larger CTE is relatively cheap, choosing a dielectric material with a larger CTE as the first insulating layer 21 at the die placement side 20 a can also effectively reduce the manufacturing cost of the packaging substrate 2 .

As shown in FIG. 2B , in subsequent applications, the package substrate 2 can be bonded to at least one semiconductor chip 30 on the plurality of electrical connection pads 203 , and bonded on the pads 204 such as solder balls or other metal bumps. The conductive elements 32 are used to form an electronic package, and the electronic package is connected to a circuit board (not shown) through the conductive elements 32 .

The electronic component 30 is an active component, a passive component or a combination thereof, wherein the active component is such as a semiconductor chip, and the passive component is such as a resistor, capacitor and inductor.

In the present embodiment, the electronic component 30 is a semiconductor chip, which has an opposite active surface 30a and a non-active surface 30b. There are a plurality of electrode pads 300 on the active surface 30a, and the electronic component 30 is borrowed by its electrode pad 300. A plurality of conductive bumps 31 are flip-chip bonded and electrically connected to the electrical connection pad 203, and then a primer (not shown) is formed between the electronic component 30 and the chip side 20a to cover the conductive bumps 31; or, the electrode pad 300 of the electronic component 30 can be electrically connected to the electrical connection pad 203 by a plurality of bonding wires (not shown) in a wire bonding manner. Or, the electrode pad 300 of the electronic component 30 can be without the first insulating protective layer 26a directly contacts the electrical connection pad 203 . However, the manner in which the electronic component 30 is electrically connected to the circuit layer 20 is not limited to the above.

The conductive element 32 is electrically connected to the circuit layer 20 and the circuit board.

FIG. 3 is a schematic cross-sectional view of another embodiment of the packaging substrate 3 of the present invention. As shown in FIG. 3 , the packaging substrate 3 of this embodiment is coreless, and its first insulating portion 3 a includes a plurality of stacked first insulating layers 21 .

Therefore, the packaging substrate 3 of the present invention is due to the thermal expansion coefficient of the first insulating portion 3a being greater than the thermal expansion coefficient of the second insulating portion 2b, so in the packaging process, when the packaging substrate 3 is in a temperature cycle, the first insulating The expansion and contraction of the portion 3 a and the second insulating portion 2 b are different, so as to adjust the warping direction and balance the warping degree of the packaging substrate 3 , so that the warping degree of the packaging substrate 3 is greatly reduced during the temperature rise and fall process.

Furthermore, since the warpage of the packaging substrate 3 is greatly reduced, the conductive traces 201 will not be too close to each other due to the warpage, so the circuit layer 20 is conducive to the design of fine pitches/fine lines to meet the needs of semiconductor chips. The demand for high-density contacts.

Also, since the circuit layer 20 can meet the requirements of fine pitch/fine circuit, under the same amount of wiring, the amount of metal material used to make the circuit layer 20 in the package substrate 3 is less than that used in the conventional package substrate 1b. The amount of metal material used in the circuit layer 12 can reduce the manufacturing cost of the packaging substrate 3 .

In addition, since the dielectric material with a larger CTE is relatively cheap, choosing a dielectric material with a larger CTE as the first insulating portion 2 a at the die placement side 20 a can also effectively reduce the manufacturing cost of the packaging substrate 3 .

It should be understood that the number of layers of the first insulating portion and the number of layers of the second insulating portion can be configured according to requirements, and there is no special limitation.

To sum up, the packaging substrate of the present invention uses the coefficient of thermal expansion of the first insulating portion to be greater than that of the second insulating portion, so that the amount of expansion and contraction of the first insulating portion on the side where the chip is placed can be used to adjust the The degree of warpage of the packaging substrate, so compared with the conventional technology, the packaging substrate of the present invention does not need to increase The thickness of each insulating layer can reduce the warping deformation of the package substrate, thereby not only improving the yield rate of products, but also meeting the requirements of lightness, thinness and shortness.

The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of the patent application described later.

2: Package substrate

2a: the first insulating part

2b: Second insulating part

20: Line layer

20a: crystal side

20b: External side

201: Conductive trace

202: Conductive blind hole

203: Electrical connection pad

204: welding pad

21: The first insulating layer

22,23,24,25: second insulating layer

26a: the first insulation protection layer

26b: the second insulation protection layer

t: thickness

Claims (8)

A packaging substrate, comprising: a first insulating portion comprising at least one first insulating layer; a second insulating portion comprising a plurality of second insulating layers, which is stacked on the first insulating portion to form an insulating structure, and The insulating structure has opposite crystal side and external side, so that the first insulating layer is correspondingly disposed on the crystal side, and the second insulating layer is correspondingly disposed on the external side, wherein the first insulating part The coefficient of thermal expansion is greater than that of the second insulating part, and the coefficient of thermal expansion of the plurality of second insulating layers decreases or increases toward the outer side; and the circuit layer is embedded in the first insulating part and the second insulating layer. In the second insulation part. The package substrate according to claim 1, wherein at least two of the plurality of second insulating layers have the same or different coefficients of thermal expansion. The packaging substrate according to claim 1, wherein the material forming the first insulating layer is an Ajinomoto build-up film. The packaging substrate according to claim 1, wherein the material forming the second insulating layer is a prepreg material. The packaging substrate as claimed in claim 1, wherein the thicknesses of the first insulating layer and the second insulating layer are the same or different. The packaging substrate as claimed in claim 1 further includes an insulating protective layer disposed on the first and/or second insulating portion and exposing part of the circuit layer. An electronic package, comprising: the package substrate as claimed in Claim 1; and an electronic component disposed on the die side and electrically connected to the circuit layer. The electronic package according to claim 7, wherein a plurality of conductive elements electrically connected to the circuit layer are disposed on the external side.

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