TWI691025B - Electronic package and manufacturing method thereof and carrier structure - Google Patents
Electronic package and manufacturing method thereof and carrier structure Download PDFInfo
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- TWI691025B TWI691025B TW108113602A TW108113602A TWI691025B TW I691025 B TWI691025 B TW I691025B TW 108113602 A TW108113602 A TW 108113602A TW 108113602 A TW108113602 A TW 108113602A TW I691025 B TWI691025 B TW I691025B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
本發明係有關一種封裝結構,尤指一種電子封裝件及其製法與承載結構。 The invention relates to a packaging structure, in particular to an electronic packaging and its manufacturing method and bearing structure.
隨著電子產品在功能及處理速度之需求的提升,作為電子產品之核心組件的半導體晶片需具有更高密度之電子元件(Electronic Components)及電子電路(Electronic Circuits),故半導體晶片在運作時將隨之產生更大量的熱能,且包覆該半導體晶片之封裝膠體係為一種導熱係數僅0.8Wm-1k-1之不良傳熱材質(即熱量之逸散效率不佳),因而若不能有效逸散所產生之熱量,將會造成半導體晶片之損害或產品信賴性問題。 With the increasing demand for functions and processing speed of electronic products, semiconductor chips as the core components of electronic products need to have higher density of electronic components (Electronic Components) and electronic circuits (Electronic Circuits). A larger amount of heat energy is generated, and the encapsulant system covering the semiconductor chip is a poor heat transfer material with a thermal conductivity of only 0.8Wm-1k-1 (that is, the heat dissipation efficiency is not good), so if it cannot be effectively escaped The generated heat will cause damage to the semiconductor chip or product reliability issues.
因此,為了能迅速將熱能散逸至大氣中,業界通常會在半導體封裝結構中配置散熱片(Heat Sink或Heat Spreader),該散熱片一般藉由散熱膠,如導熱介面材(Thermal Interface Material,簡稱TIM),結合至半導體晶片背面,以藉散熱膠與散熱片逸散出半導體晶片所產生之熱量,再者,通常令散熱片之頂面外露出封裝膠體或直接外露於大氣中為佳,俾取得較佳之散熱效果。 Therefore, in order to quickly dissipate heat energy into the atmosphere, the industry usually configures a heat sink (Heat Sink or Heat Spreader) in the semiconductor package structure. The heat sink is generally made of heat dissipation adhesive, such as thermal interface material (Thermal Interface Material, abbreviation) TIM), which is bonded to the back of the semiconductor chip to dissipate the heat generated by the semiconductor chip through the heat dissipation adhesive and the heat sink. In addition, it is usually better to expose the top surface of the heat sink to the packaging gel or directly to the atmosphere. Get better heat dissipation effect.
習知TIM層係為低溫熔融之熱傳導材料(如銲錫材料),其設於半導體晶片背面與散熱片之間。 The conventional TIM layer is a low-temperature melting heat conductive material (such as solder material), which is disposed between the back surface of the semiconductor wafer and the heat sink.
如第1圖所示,習知半導體封裝件1之製法係先將一半導體晶片11以其作用面11a利用覆晶接合方式(即透過導電凸塊110與底膠111)設於一封裝基板10上,再將一散熱件13以其頂片130藉由TIM層12(其包含銲錫層與助焊劑)回銲結合於該半導體晶片11之非作用面11b上,且該散熱件13之支撐腳131藉由黏著層14架設於該封裝基板10上。接著,進行封裝壓模作業,以供封裝膠體(圖略)包覆該半導體晶片11及散熱件13,並使該散熱件13之頂片130外露出封裝膠體而直接與大氣接觸。之後,將該半導體封裝件1以其封裝基板10藉由複數銲球15接置於一電路板9上。
As shown in FIG. 1, the conventional manufacturing method of the semiconductor package 1 is to first place a
於運作時,該半導體晶片11所產生之熱能係經由該非作用面11b、TIM層12而傳導至該散熱件13之頂片130以散熱至該半導體封裝件1之外部。
During operation, the thermal energy generated by the
惟,習知半導體封裝件1中,該些銲球15係位於該封裝基板10之佈線區,故於熱循環(thermal cycle)時,應力會集中在該封裝基板10之非佈線區,使該封裝基板10發生翹曲,導致該半導體晶片11與該封裝基板10分離,即產生脫層(delaminating)問題,造成該半導體晶片11無法有效電性連接至該電路板9或該半導體封裝件1無法通過可靠度測試,致使產品之良率不佳。
However, in the conventional semiconductor package 1, the
再者,當該半導體封裝件1之尺寸增大時,重量也隨之增加,故於回銲該銲球15而使該銲球15呈熔融狀態時,該些銲球15因無法承受其
上方之構件重量而將被壓扁、變形(如第1圖所示之虛線處),導致相鄰銲球15容易發生橋接(Ball bridge)現象而產生電性短路之問題。
Furthermore, when the size of the semiconductor package 1 increases, the weight also increases. Therefore, when the
因此,如何克服上述習知技術之種種問題,實已成為目前業界亟待克服之難題。 Therefore, how to overcome the problems of the above-mentioned conventional technologies has become a problem that the industry urgently needs to overcome.
鑑於上述習知技術之種種缺失,本發明提供一種電子封裝件,係包括:承載件,係具有至少一穿孔;電子元件,係設於該承載件上並電性連接該承載件;以及強化體,係設於該穿孔中並凸出該承載件,其中,該強化體未電性連接該承載件及該電子元件。 In view of the above-mentioned defects of the prior art, the present invention provides an electronic package including: a carrier having at least one perforation; an electronic component provided on the carrier and electrically connected to the carrier; and a reinforcement body , Which is arranged in the through hole and protrudes from the carrier, wherein the reinforcing body is not electrically connected to the carrier and the electronic component.
本發明亦提供一種電子封裝件之製法,係包括:提供具有至少一穿孔之承載件;以及將電子元件設於該承載件上,並使該電子元件電性連接該承載件,且形成強化體於該穿孔中,並使該強化體凸出該承載件,其中,該強化體未電性連接該承載件及該電子元件。 The invention also provides a method for manufacturing an electronic package, comprising: providing a carrier with at least one perforation; and disposing the electronic component on the carrier, and electrically connecting the electronic component to the carrier and forming a reinforcement The reinforced body protrudes from the carrier in the through hole, wherein the reinforced body is not electrically connected to the carrier and the electronic component.
前述之電子封裝件及其製法中,該承載件係具有相對之第一表面與第二表面,使該電子元件設於該承載件之第一表面上,且該強化體凸出該承載件之第一表面。例如,復包括設置板塊體於該承載件之第二表面上,且該板塊體連接該強化體但未電性連接該承載件及該電子元件。 In the aforementioned electronic package and its manufacturing method, the carrier has a first surface and a second surface opposite to each other, so that the electronic component is disposed on the first surface of the carrier, and the reinforcement body protrudes from the carrier First surface. For example, the method includes disposing a block body on the second surface of the carrier, and the block body is connected to the reinforcement body but not electrically connected to the carrier and the electronic component.
前述之電子封裝件及其製法中,該承載件係具有相對之第一表面與第二表面,使該電子元件設於該承載件之第一表面上,且該強化體凸出該承載件之第二表面。例如,復包括設置板塊體於該承載件之第一表面上,且該板塊體連接該強化體但未電性連接該承載件及該電子元件。 In the aforementioned electronic package and its manufacturing method, the carrier has a first surface and a second surface opposite to each other, so that the electronic component is disposed on the first surface of the carrier, and the reinforcement body protrudes from the carrier Second surface. For example, the method includes placing a block body on the first surface of the carrier, and the block body is connected to the reinforcing body but not electrically connected to the carrier and the electronic component.
前述之電子封裝件及其製法中,該承載件之表面係定義有佈線區與鄰接該佈線區之空曠區,以令該電子元件配置於該佈線區,且該強化體係配置於該空曠區。 In the aforementioned electronic package and its manufacturing method, the surface of the carrier defines a wiring area and an empty area adjacent to the wiring area, so that the electronic component is arranged in the wiring area, and the reinforcement system is arranged in the empty area.
前述之電子封裝件及其製法中,該穿孔係位於該承載件之其中一表面之邊緣處而未連通該邊緣。 In the aforementioned electronic package and its manufacturing method, the perforation is located at the edge of one of the surfaces of the carrier without connecting the edge.
前述之電子封裝件及其製法中,該穿孔係為形成於該承載件側面之缺口。 In the aforementioned electronic package and its manufacturing method, the through hole is a notch formed on the side of the carrier.
前述之電子封裝件及其製法中,復包括形成絕緣體於該承載件上,以包覆該強化體凸出該承載件之部分。 In the aforementioned electronic package and its manufacturing method, it includes forming an insulator on the carrier to cover the portion of the reinforcement protruding from the carrier.
前述之電子封裝件及其製法中,復包括設置散熱件於該承載件上。 In the aforementioned electronic package and its manufacturing method, it further includes disposing a heat sink on the carrier.
前述之電子封裝件及其製法中,復包括於該承載件上形成複數電性連接該承載件之導電元件。 In the foregoing electronic package and its manufacturing method, the method includes forming a plurality of conductive elements on the carrier that are electrically connected to the carrier.
本發明另提供一種承載結構,係包括:承載件,係具有至少一穿孔;以及強化體,係設於該穿孔中並凸出該承載件,其中,該強化體未電性連接該承載件。 The invention also provides a bearing structure, which includes: a bearing member having at least one perforation; and a reinforcement body disposed in the perforation and protruding from the bearing member, wherein the reinforcement body is not electrically connected to the bearing member.
前述之承載結構中,復包括設於該承載件上之板塊體,其連接該強化體,且該板塊體未電性連接該承載件。 In the aforementioned load-bearing structure, it further includes a block body provided on the load-bearing member, which is connected to the reinforcement body, and the block body is not electrically connected to the load-bearing member.
前述之承載結構中,該穿孔係位於該承載件之其中一表面之邊緣處而未連通該邊緣。 In the aforementioned load-bearing structure, the perforation is located at the edge of one of the surfaces of the load-bearing member without connecting the edge.
前述之承載結構中,該穿孔係為形成於該承載件側面之缺口。 In the aforementioned bearing structure, the perforation is a notch formed on the side of the bearing.
前述之承載結構中,復包括形成於該承載件上之絕緣體,以包覆該強化體凸出該承載件之部分。 In the aforementioned load-bearing structure, it includes an insulator formed on the load-bearing member to cover the portion of the reinforcement body that protrudes from the load-bearing member.
前述之承載結構中,復包括形成於該承載件上以電性連接該承載件之複數導電元件。 In the aforementioned supporting structure, the plurality includes a plurality of conductive elements formed on the supporting member to electrically connect the supporting member.
由上可知,本發明之電子封裝件及其製法與承載結構中,主要藉由該強化體穿過該承載件之設計,以有效分散熱應力,故相較於習知技術,本發明能避免該電子元件與該承載件分離,因而該電子元件能有效電性連接至該電路板或該電子封裝件能通過可靠度測試。 It can be seen from the above that in the electronic package of the present invention and its manufacturing method and supporting structure, the design of the reinforcement body passing through the supporting member is used to effectively disperse the thermal stress, so compared with the conventional technology, the present invention can avoid The electronic component is separated from the carrier, so the electronic component can be effectively electrically connected to the circuit board or the electronic package can pass the reliability test.
再者,當該電子封裝件之尺寸增大時,重量也隨之增加,故於該導電元件呈熔融狀態時,藉由該強化體或板塊體支撐下壓力度,使該些導電元件受壓至一定程度後能呈現預定形狀,使相鄰之導電元件不會發生橋接現象,因而能避免發生電性短路之問題。 Furthermore, as the size of the electronic package increases, the weight also increases, so when the conductive element is in a molten state, the conductive element is pressed by the reinforcement or the block body to support the pressure After a certain degree, it can assume a predetermined shape, so that adjacent conductive elements will not bridge, so that the problem of electrical short circuit can be avoided.
1‧‧‧半導體封裝件 1‧‧‧Semiconductor package
10‧‧‧封裝基板 10‧‧‧Package substrate
11‧‧‧半導體晶片 11‧‧‧Semiconductor chip
11a,21a‧‧‧作用面 11a, 21a‧‧‧action surface
11b,21b‧‧‧非作用面 11b, 21b‧‧‧non-acting surface
110,210‧‧‧導電凸塊 110,210‧‧‧ conductive bump
111,22‧‧‧底膠 111,22‧‧‧ Primer
12‧‧‧TIM層 12‧‧‧TIM layer
13,2a,4a‧‧‧散熱件 13,2a,4a‧‧‧Cooling parts
130‧‧‧頂片 130‧‧‧Top film
131,27,47‧‧‧支撐腳 131,27,47‧‧‧support feet
14‧‧‧黏著層 14‧‧‧ Adhesive layer
15‧‧‧銲球 15‧‧‧solder ball
2,3,4‧‧‧電子封裝件 2,3,4‧‧‧Electronic package
20‧‧‧承載件 20‧‧‧Carrier
20a‧‧‧第一表面 20a‧‧‧First surface
20b‧‧‧第二表面 20b‧‧‧Second surface
20c‧‧‧側面 20c‧‧‧Side
200,300‧‧‧穿孔 200,300‧‧‧Perforation
201,202‧‧‧線路層 201,202‧‧‧ line layer
21‧‧‧電子元件 21‧‧‧Electronic components
23,33,43‧‧‧強化體 23,33,43‧‧‧Reinforcement
23a,33b‧‧‧端部 23a, 33b ‧‧‧ end
24,34,44‧‧‧板塊體 24,34,44 ‧‧‧ plate
25‧‧‧絕緣體 25‧‧‧Insulator
26‧‧‧結合層 26‧‧‧Combination layer
28,48‧‧‧散熱體 28,48‧‧‧heat radiator
280‧‧‧導熱介面層 280‧‧‧thermal interface layer
29,29’‧‧‧導電元件 29,29’‧‧‧conductive element
4b‧‧‧一體成形結構 4b‧‧‧Integrated forming structure
9‧‧‧電路板 9‧‧‧ circuit board
A‧‧‧佈線區 A‧‧‧Wiring area
B‧‧‧空曠區 B‧‧‧ open area
L‧‧‧長度 L‧‧‧Length
H‧‧‧高度 H‧‧‧ Height
第1圖係為習知半導體封裝件之剖視示意圖。 FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package.
第2A至2D圖係為本發明之電子封裝件之製法之第一實施例之剖視示意圖。 2A to 2D are schematic cross-sectional views of the first embodiment of the manufacturing method of the electronic package of the present invention.
第2A’圖係為第2A圖之局部上視示意圖。 Figure 2A' is a schematic partial top view of Figure 2A.
第3A至3C圖係為本發明之電子封裝件之製法之第二實施例之剖視示意圖。 3A to 3C are schematic cross-sectional views of a second embodiment of the method for manufacturing an electronic package of the present invention.
第3A’圖係為第3A圖之局部上視示意圖。 Figure 3A' is a schematic partial top view of Figure 3A.
第3A”圖係為第3A’圖沿剖面線P-P之剖視示意圖。 Fig. 3A" is a schematic cross-sectional view of Fig. 3A' taken along section line P-P.
第3B’圖係為第3B圖之局部上視示意圖。 Figure 3B' is a schematic partial top view of Figure 3B.
第3B”圖係為第3B’圖沿剖面線P-P之剖視示意圖。 Fig. 3B" is a schematic cross-sectional view of Fig. 3B' taken along section line P-P.
第3C’圖係為第3C圖之另一視角之剖視示意圖。 Fig. 3C' is a schematic cross-sectional view of Fig. 3C from another perspective.
第4A圖係為第3C圖之另一實施例之局部放大剖視示意圖。 FIG. 4A is a partially enlarged schematic cross-sectional view of another embodiment of FIG. 3C.
第4B圖係為本發明之電子封裝件之製法之其它實施例之剖視示意圖。 FIG. 4B is a schematic cross-sectional view of another embodiment of the manufacturing method of the electronic package of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following describes the implementation of the present invention by specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structure, ratio, size, etc. shown in the drawings of this specification are only used to match the content disclosed in the specification, for those who are familiar with this skill to understand and read, not to limit the implementation of the present invention The limited conditions do not have technical significance. Any modification of structure, change of proportional relationship or adjustment of size should still fall within the scope of the invention without affecting the efficacy and the purpose of the invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "upper", "first", "second" and "one" cited in this specification are only for the convenience of description, not to limit the scope of the invention, Changes or adjustments in the relative relationship are considered to be within the scope of the invention without substantial changes in the technical content.
第2A至2D圖係為本發明之電子封裝件之製法之第一實施例之剖面示意圖。 2A to 2D are schematic cross-sectional views of the first embodiment of the manufacturing method of the electronic package of the present invention.
如第2A及2A’圖所示,提供一佈設有至少一電子元件21之承載件20,且該承載件20係具有相對之第一表面20a與第二表面20b,並形成複數連通該第一與第二表面20a,20b之穿孔200。
As shown in FIGS. 2A and 2A′, a
於本實施例中,該承載件20例如為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構,其係於介電材上形成線路層201,202,如扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL),以於其第一表面20a(或第二表面20b)上定義出佈線區A(於本實施例中係以第一表面20a做為說明,即佈設線路層201之區域,如I/O接點)與空曠區B(如I/O接點周圍)。應可理解地,該承載件20亦可為其它可供承載如晶片等電子元件之承載結構,例如矽中介板(silicon interposer)、晶圓(wafer)、或其它具有金屬佈線(routing)之載板等,並不限於上述。
In this embodiment, the
再者,該電子元件21係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如為半導體晶片,且該被動元件係例如為電阻、電容及電感。例如,於本實施例中,該電子元件21係為半導體晶片,其具有相對之作用面21a與非作用面21b,且該作用面21a藉由覆晶方式(透過導電凸塊210)設於佈線區以電性連接該線路層201,並以底膠22包覆該些導電凸塊210;或者,該電子元件21亦可藉由複數銲線(圖略)以打線方式電性連接該線路層201;亦或,該電子元件21可直接接觸該線路層201。然而,有關該電子元件21電性連接線路層201之方式不限於上述。
Furthermore, the
又,該穿孔200係位於該承載件20之其中一表面(如第一表面20a或第二表面20b)之邊緣處而未連通該邊緣,即位於該承載件20於製程中較易產生應力集中區(如空曠區B)之處。
Moreover, the
如第2B圖所示,將複數強化體23穿設於該穿孔200中且凸出該承載件20之第一表面20a。
As shown in FIG. 2B, a plurality of reinforcing
於本實施例中,該強化體23係為柱體,其端部23a凸出該承載件20之第一表面20a。例如,先將該強化體23形成於一板塊體24上以形
成框架結構,再將該板塊體24結合至該承載件20之第二表面20b,以順勢將該強化體23插過該穿孔200。例如,該強化體23與該板塊體24係以如銅材之金屬材製作,且兩者可一體成形或以接合方式組構,使該板塊體24可作為散熱用,而使該強化體23作為散熱腳。
In this embodiment, the reinforcing
再者,該強化體23係未電性連接該承載件20與該電子元件21,且該板塊體24亦未電性連接該承載件20與該電子元件21。
Furthermore, the reinforcing
如第2C圖所示,形成一絕緣體25於該承載件20之第一表面20b以包覆該強化體23凸出該承載件20之端部23a。
As shown in FIG. 2C, an
於本實施例中,該絕緣體25係為膠材,以將該強化體23與該板塊體24固定於該承載件20上,且可保護該強化體23之端部23a,以避免於製程中碰觸其它導電體。
In this embodiment, the
再者,於該承載件20之第一表面20b上可形成如膠材之結合層26,且可於該電子元件21之非作用面21b上形成一導熱介面層280。例如,該導熱介面層280係為TIM,如低溫熔融之熱傳導材料,其可由固態金屬或液態金屬(如銲錫材料)形成。
Furthermore, a
如第2D圖所示,將一包含有支撐腳27及散熱體28之散熱件2a以其支撐腳27藉由該結合層26結合於該承載件24之第一表面20a上,且使該散熱件2a之散熱體28藉由該導熱介面層280結合該電子元件21。
As shown in FIG. 2D, a
於本實施例中,該複數支撐腳27係一體成形於該散熱體28上;或者,該複數支撐腳27亦可以接合方式設於該散熱體28上。
In this embodiment, the plurality of
再者,於該承載件20之第二表面20b之線路層202上可形成複數導電元件29,以製得本發明之電子封裝件2,並可於後續製程中回銲該導電元件29而接置一如電路板9之電子裝置。具體地,該導電元件29係為如銅塊之金屬塊、銲錫凸塊或具有銅核心的錫球等。例如,部分該導電元
件29’可依需求接觸該板塊體24以作為散熱用,而非作為電路用。應可理解地,有關該導電元件之種類繁多,並不限於上述。
Furthermore, a plurality of
又,該導熱介面層280亦可先形成於該散熱體28上,再將該散熱體28以該導熱介面層280結合至該電子元件21之非作用面21b上。同理地,該結合層26亦可先形成於該支撐腳27上,再將該支撐腳27藉由該結合層26結合至該承載件24之第一表面20a上。
In addition, the thermally
另外,為了提升TIM與電子元件21之間的接著強度,可於該電子元件21之表面上覆金(即所謂之Coating Gold On Chip Back)。具體地,於該電子元件21之非作用面21b與該散熱體28之表面上形成一金層,且進一步配合助焊劑(flux),以利於該導熱介面層280接著於該金層上。
In addition, in order to improve the bonding strength between the TIM and the
因此,本發明之製法所形成之電子封裝件2,主要藉由該強化體23佈設於該承載件20之空曠區B,以於熱循環(thermal cycle)時,分散應力,使應力不會集中在該承載件20之空曠區B,故相較於習知技術,本發明之製法能避免該電子元件21與該承載件20分離,即避免產生脫層(delaminating)問題,因而該電子元件21能有效電性連接至該電路板9或該電子封裝件2能通過可靠度測試,以提升產品之良率。
Therefore, the electronic package 2 formed by the manufacturing method of the present invention is mainly disposed in the open area B of the
再者,當該電子封裝件2之尺寸增大時,重量也隨之增加,故於回銲該導電元件29而使該導電元件29呈熔融狀態時,藉由該板塊體24支撐下壓力度,使該些導電元件29受壓至一定程度後(即當該板塊體24抵靠該電路板9時)能呈現預定形狀,使相鄰之導電元件29不會發生橋接(Ball bridge)現象,因而能避免發生電性短路之問題。
Furthermore, as the size of the electronic package 2 increases, the weight also increases, so when the
第3A至3C圖係為本發明之電子封裝件3之製法之第二實施例之剖面示意圖。本實施例與第一實施例之差異在於強化體與板塊體之配置,其它製程大致相同,故以下不再贅述相同處。
3A to 3C are schematic cross-sectional views of the second embodiment of the method for manufacturing the
如第3A及3A”圖所示,提供一佈設有至少一電子元件21之承載件20,且該承載件20係具有相對之第一表面20a與第二表面20b,並形成複數連通該第一與第二表面20a,20b之穿孔300。
As shown in FIGS. 3A and 3A, a
於本實施例中,如第3A’圖所示,該穿孔300係位於該承載件20之側面20c(較易產生應力集中區之處)以形成缺口狀。
In this embodiment, as shown in FIG. 3A', the
再者,第3A圖之視角係從第3A’圖之承載件20之側面20c方向(如第3A’圖所示之箭頭方向,即左方或右方)觀視之,第3A”圖係為第3A’圖沿剖面線P-P之剖視示意圖。
Furthermore, the angle of view of FIG. 3A is viewed from the
如第3B、3B’及3B”圖所示,將複數金屬強化體33穿設於該穿孔300中,且該強化體33之端部33b凸出該承載件20之第二表面20b,而該板塊體34結合至該承載件20之第一表面20a以遮蓋該穿孔300。
As shown in FIGS. 3B, 3B′ and 3B”, a plurality of
於本實施例中,第3B圖之視角係從第3B’圖之承載件20之側面20c方向(如第3B’圖所示之箭頭方向,即左方或右方)觀視之,第3B”圖係為第3B’圖沿剖面線P-P之剖視示意圖。
In this embodiment, the viewing angle of FIG. 3B is viewed from the
如第3C圖所示,將一散熱件2a以其支撐腳27藉由結合層26結合於該板塊體34上,且使該散熱件2a之散熱體28藉由導熱介面層280結合該電子元件21。
As shown in FIG. 3C, a
於本實施例中,於該承載件20之第二表面20b上可形成複數導電元件29,以於後續製程中回銲該導電元件29而接置一如電路板9之電子裝置。例如,該強化體33凸出該承載件20之端部33b係位於該些導電元件29之間,使該強化體33不會接觸該些導電元件29。進一步,如第4圖所
示,該強化體33凸出該承載件20之端部33b之長度L係為該導電元件29之高度H之2/3(L=2/3H)。
In this embodiment, a plurality of
再者,應可理解地,亦可形成絕緣體25包覆該強化體33凸出該承載件20之端部33b。
Furthermore, it should be understood that an
因此,本發明之製法所形成之電子封裝件3,主要藉由該強化體33佈設於該承載件20之空曠區B,以於熱循環(thermal cycle)時,分散應力,使應力不會集中在該承載件20之空曠區B,故相較於習知技術,本發明之製法能避免該電子元件21與該承載件20分離,即避免產生脫層(delaminating)問題,因而該電子元件21能有效電性連接至該電路板9或該電子封裝件3能通過可靠度測試,以提升產品之良率。
Therefore, the
再者,當該電子封裝件3之尺寸增大時,重量也隨之增加,故於回銲該導電元件29而使該導電元件29呈熔融狀態時,藉由該強化體33之端部33b支撐下壓力度,使該些導電元件29受壓至一定程度後(即當該強化體33之端部33b抵靠該電路板9時)能呈現預定形狀,使相鄰之導電元件29不會發生橋接(Ball bridge)現象,因而能避免發生電性短路之問題。
Furthermore, when the size of the
又,如第4B圖所示之電子封裝件4,該散熱件4a、該金屬強化體33與該板塊體34可一體成形。例如,該支撐腳47、散熱體48、該金屬強化體43與該板塊體44係為一體成形結構4b,其藉由金屬強化體43穿設於該穿孔300中,以定位該一體成形結構4b,故不僅可簡化製程步驟(無需依序配置該金屬強化體33與該板塊體34及該散熱件4a),且可省略結合層26之使用,以降低製作成本。
Furthermore, as in the electronic package 4 shown in FIG. 4B, the
本發明復提供一種電子封裝件2,3,4,係包括:一具有至少一穿孔200,300之承載件20、至少一設於該承載件20上並電性連接該承載
件20之電子元件21、以及至少一設於該穿孔200,300中並凸出該承載件20之強化體23,33,43。
The present invention further provides an
所述之強化體23,33,43係未電性連接該承載件20及該電子元件21。
The reinforced
於一實施例中,該承載件20係具有相對之第一表面20a與第二表面20b,使該電子元件21設於該承載件20之第一表面20a上,且該強化體23凸出該承載件20之第一表面20a而齊平(或未凸出)該第二表面20b。又包括至少一設於該承載件20之第二表面20b上之板塊體24,其連接該強化體23而未電性連接該承載件20及該電子元件21。
In an embodiment, the
於一實施例中,該承載件20係具有相對之第一表面20a與第二表面20b,使該電子元件21設於該承載件20之第一表面20a上,且該強化體33,43凸出該承載件20之第二表面20b而齊平(或未凸出)該第一表面20a。又包括至少一設於該承載件20之第一表面20a上之板塊體34,44,其連接該強化體33,44而未電性連接該承載件20及該電子元件21。
In one embodiment, the
於一實施例中,該承載件20之第一表面20a係定義有佈線區A與鄰接該佈線區A之空曠區B,以令該電子元件21配置於該佈線區A,且該強化體23,33係配置於該空曠區B。
In an embodiment, the
於一實施例中,該穿孔300係為形成於該承載件20側面20c之缺口。
In one embodiment, the through
於一實施例中,該電子封裝件2復包括至少一形成於該承載件20上之絕緣體25,以包覆該強化體23,33凸出該承載件20之部分(如端部23a,33b)。
In one embodiment, the electronic package 2 includes at least one
於一實施例中,該電子封裝件2,3,4復包括設於該承載件20上之散熱件2a,4a。
In one embodiment, the
於一實施例中,該電子封裝件2,3,4復包括形成於該承載件20上以電性連接該承載件20之複數導電元件29。
In one embodiment, the
本發明另提供一種承載結構,係包括:一具有至少一穿孔200,300之承載件20、以及至少一設於該穿孔200,300中並凸出該承載件20之強化體23,33,43,其中,該強化體23,33,43未電性連接該承載件20。
The present invention also provides a bearing structure including: a bearing
於一實施例中,該承載結構復包括至少一設於該承載件20上之板塊體24,34,44,其連接該強化體23,33,44,且該板塊體24,34,44未電性連接該承載件20。
In one embodiment, the load-bearing structure includes at least one
於一實施例中,該穿孔300係為形成於該承載件20側面20c之缺口。
In one embodiment, the through
於一實施例中,該承載結構復包括至少一形成於該承載件20上之絕緣體25,以包覆該強化體23,33,43凸出該承載件20之部分(如端部23a)。
In one embodiment, the carrying structure further includes at least one
於一實施例中,該承載結構復包括形成於該承載件20上以電性連接該承載件20之複數導電元件29。
In one embodiment, the carrier structure includes a plurality of
綜上所述,本發明之電子封裝件及其製法與承載結構,係藉由該強化體之設計,以分散應力,故本發明能避免該電子元件與該承載件分離,因而該電子元件能有效電性連接至該電路板或該電子封裝件能通過可靠度測試。 In summary, the electronic package of the present invention, its manufacturing method and the supporting structure are designed to disperse the stress by the design of the reinforcement body, so the present invention can avoid the separation of the electronic component and the supporting component, so the electronic component can The electrical connection to the circuit board or the electronic package can pass the reliability test.
再者,當該電子封裝件之尺寸增大時,重量也隨之增加,故於該導電元件呈熔融狀態時,藉由該強化體或板塊體支撐下壓力度,使該些導電元件受壓至一定程度後能呈現預定形狀,使相鄰之導電元件不會發生橋接現象,因而能避免發生電性短路之問題。 Furthermore, as the size of the electronic package increases, the weight also increases, so when the conductive element is in a molten state, the conductive element is pressed by the reinforcement or the block body to support the pressure After a certain degree, it can assume a predetermined shape, so that adjacent conductive elements will not be bridged, so that the problem of electrical short circuit can be avoided.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are used to exemplify the principles and effects of the present invention, rather than to limit the present invention. Anyone who is familiar with this skill can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be as listed in the scope of patent application mentioned later.
2‧‧‧電子封裝件 2‧‧‧Electronic package
2a‧‧‧散熱件 2a‧‧‧Cooling parts
20‧‧‧承載件 20‧‧‧Carrier
20a‧‧‧第一表面 20a‧‧‧First surface
20b‧‧‧第二表面 20b‧‧‧Second surface
200‧‧‧穿孔 200‧‧‧Perforation
202‧‧‧線路層 202‧‧‧ Line layer
21‧‧‧電子元件 21‧‧‧Electronic components
23‧‧‧強化體 23‧‧‧Reinforcement
24‧‧‧板塊體 24‧‧‧Plate
25‧‧‧絕緣體 25‧‧‧Insulator
26‧‧‧結合層 26‧‧‧Combination layer
27‧‧‧支撐腳 27‧‧‧Support feet
28‧‧‧散熱體 28‧‧‧heat radiator
280‧‧‧導熱介面層 280‧‧‧thermal interface layer
29,29’‧‧‧導電元件 29,29’‧‧‧conductive element
9‧‧‧電路板 9‧‧‧ circuit board
Claims (22)
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TW200531232A (en) * | 2004-03-09 | 2005-09-16 | Siliconware Precision Industries Co Ltd | Semiconductor package with heatsink and method for fabricating the same and stiffner |
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TW201546954A (en) * | 2014-01-28 | 2015-12-16 | 台灣積體電路製造股份有限公司 | Semiconductor device structure and fabricating method thereof |
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WO2008120280A1 (en) * | 2007-03-29 | 2008-10-09 | Fujitsu Limited | Distortion reduction fixing structure |
US9041192B2 (en) * | 2012-08-29 | 2015-05-26 | Broadcom Corporation | Hybrid thermal interface material for IC packages with integrated heat spreader |
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CN1581501A (en) * | 2003-08-01 | 2005-02-16 | 富士胶片株式会社 | Solid-state imaging device and method for manufacturing the same |
TW200531232A (en) * | 2004-03-09 | 2005-09-16 | Siliconware Precision Industries Co Ltd | Semiconductor package with heatsink and method for fabricating the same and stiffner |
TW200939423A (en) * | 2008-03-11 | 2009-09-16 | Powertech Technology Inc | Semiconductor package structure with heat sink |
TW201546954A (en) * | 2014-01-28 | 2015-12-16 | 台灣積體電路製造股份有限公司 | Semiconductor device structure and fabricating method thereof |
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