TWI735398B - Electronic package and manufacturing method thereof - Google Patents

Abstract

An electronic package in which an electronic element is arranged in a die-bond region of a carrier and electrically connected to the carrier, and a bonding layer is arranged outside the die-bond to surround the electronic element, and then a heat sink is combined with the bonding layer in order to be arranged on the carrier and cover the electronic element, such that the electronic element is deflected relative to the die-bond region and mounted on the carrier so as to make the outline of the electronic element not correspond to the boundary of the die-bond region to balance a stress distribution of the electronic package and avoid delamination between the heat sink and the electronic element.

Description

Electronic package and its manufacturing method

The present invention relates to a semiconductor device, in particular to an electronic package with a heat sink and its manufacturing method.

With the increase in the function and processing speed of electronic products, semiconductor chips, which are the core components of electronic products, need to have higher density of electronic components (Electronic Components) and electronic circuits (Electronic Circuits). In order to quickly dissipate heat to the atmosphere, a heat sink (Heat Sink or Heat Spreader) is usually arranged in the semiconductor package structure. The heat sink is usually bonded to the back of the chip by a heat sink, so that the heat sink and the heat sink can escape the semiconductor The heat generated by the chip.

As shown in FIG. 1A, the conventional heat-dissipating semiconductor package 1 is made by first placing a semiconductor chip 11 with its active surface 11a in a flip-chip bonding method (that is, through conductive bumps 110 and primer 111). On the wafer placement area A of the substrate 10 (as shown in FIG. 1A'), a heat dissipation element 13 is bonded to the non-acting surface 11b of the semiconductor chip 11 with its top sheet 130 through the thermally conductive layer 12, and the heat dissipation element The supporting legs 131 of 13 are erected on the packaging substrate 10 via the adhesive layer 14. Then, a packaging press molding operation is performed to provide a packaging compound (not shown in the figure) to cover the semiconductor chip 11 and the heat sink 13, and to expose the packaging compound to the top sheet 130 of the heat sink 13 to directly contact the atmosphere.

During operation, the heat energy generated by the semiconductor chip 11 is conducted to the heat sink 13 via the non-acting surface 11b and the heat conducting layer 12 to dissipate heat to the outside of the semiconductor package 1.

However, in the conventional semiconductor package 1, the contour of the semiconductor chip 11 after installation corresponds to the boundary of the crystal placement area A (as shown in FIG. 1A'), so that both the heat sink 13 and the semiconductor chip 11 are different from each other. The thermal expansion coefficient difference (CTE Mismatch) with the thermally conductive layer 12 is extremely large, and the stress generated cannot be dispersed, causing the semiconductor package 1 to deform (ie warp), as shown in FIG. 1B, resulting in the heat sink 13 The top sheet 130 and the deformed thermally conductive layer 12' (or the semiconductor chip 11) are prone to delamination (the gap t shown in FIG. 1B), which not only reduces the thermal conductivity, but also reduces the semiconductor package 1 The reliability.

Therefore, how to overcome the various problems of the above-mentioned conventional technology has actually become a problem that the industry urgently needs to overcome.

In view of the various deficiencies of the above-mentioned conventional technologies, the present invention provides an electronic package, which includes: a carrier, which defines a die placement area; and an electronic component, which is arranged in the die placement area of the carrier and is electrically connected to the A carrier, wherein the outline of the electronic component disposed on the carrier does not correspond to the boundary of the die placement region; the bonding layer is provided on the carrier and located outside the die placement region to surround the electronic component; and The heat dissipation element is combined with the bonding layer to be arranged on the carrier and cover the electronic element.

The present invention also provides a method for manufacturing an electronic package, which includes: providing a carrier defining a die placement area; arranging electronic components in the die placement area of the carrier and electrically connecting the carrier, and attaching a bonding layer Is arranged outside the chip placement area of the carrier and surrounds the electronic element, wherein the electronic element is arranged on the The contour on the carrier does not correspond to the boundary of the crystal placement area; and the heat dissipation element is combined with the bonding layer so that the heat dissipation element is disposed on the carrier and covers the electronic component.

In the aforementioned electronic package and its manufacturing method, the die placement area is rectangular, and the electronic component has a quadrilateral outline, so that the corner of the electronic component is located on the edge of the die placement area. For example, the corners of the electronic component are aligned with the bonding layer.

In the aforementioned electronic package and its manufacturing method, the bonding layer is a ring with a plurality of notches, wherein the positions of the plurality of notches are aligned or not aligned with each other. For example, the electronic component has a rectangular outline, and its corners are not aligned with the notch. Alternatively, the ring system is rectangular, and the plurality of notches are respectively located on different ring sides of the ring body. Preferably, the size of the notch on a single ring side of the ring body is 1/the size of the ring side 10.

In the aforementioned electronic package and its manufacturing method, the bonding layer includes a first section and a second section that are separated to form a plurality of gaps between the first section and the second section, and the first section The shape of one section is different from the shape of the second section. For example, the area of the carrier for contacting and joining the first section is the same as the area of the carrier for contacting and joining the second section.

It can be seen from the above that in the electronic package and the manufacturing method of the present invention, the outline of the electronic component after being placed on the carrier does not correspond to the boundary of the crystal placement region, so that the carrier can effectively balance the stress on it Therefore, compared with the prior art, the electronic package can maintain the distance between the heat sink and the carrier, so as to avoid delamination between the heat sink and the electronic component, thereby improving the electronic package The reliability.

Furthermore, in the present invention, the position of the notch does not face the corner of the electronic component, so as to improve the coverage and flatness of the heat sink, thereby effectively reducing the degree of warpage of the electronic package.

In addition, in the present invention, the size of the notch on the single ring edge of the bonding layer is designed to be 1/10 of the size of the ring edge, so as to facilitate the load-bearing member to balance the stress distribution thereon, thereby effectively reducing the electrons. The degree of warpage of the package.

In addition, in the present invention, the outline of the electronic component after being placed on the carrier does not correspond to the boundary of the crystal placement region, so that the circuit layout of the carrier can effectively match the specially designed electronic components, thereby enhancing the electronic components. The computing power of the component.

1: Semiconductor package

10: Package substrate

11: Semiconductor wafer

11a, 21a: action surface

11b, 21b: non-acting surface

110, 210: conductive bump

111,211: primer

12,12’,22: Thermally conductive layer

13,23: Heat sink

130: top piece

131,231: Support feet

14: Adhesive layer

2: Electronic package

20: Carrier

21: Electronic components

230: heat sink

24, 34: Bonding layer

24a, 24b, 24c, 24d: ring edge

240,340: gap

341: The first section

342: Second Section

A: Placement area

D, R: area

L: Sideline

t: gap

X1, X2: diagonal

Y: axis

FIG. 1A is a schematic cross-sectional view of a conventional semiconductor package.

Fig. 1A' is a schematic top plan view of Fig. 1A.

FIG. 1B is a schematic cross-sectional view of a bad state of a conventional semiconductor package.

2A to 2B are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.

Fig. 3A is a schematic top plan view of Fig. 2A.

3B and 3C are schematic top plan views of different aspects of FIG. 3A.

The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structure, ratio, size, etc. shown in the drawings in this manual are only used to match the content disclosed in the manual for the understanding and reading of those who are familiar with the art, and are not intended to limit the implementation of the present invention. Therefore, it does not have any technical significance. Any structural modification, proportional relationship change or size adjustment should still fall within the original The technical content disclosed by the invention can be covered. At the same time, in this manual The quoted terms such as "on", "first", "second", "one", etc. are also only for ease of description, and are not used to limit the scope of implementation of the present invention, and changes in their relative relationships Or adjustments, without substantive changes to the technical content, should also be regarded as the scope of the present invention can be implemented.

2A to 2B are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A, at least one electronic component 21 is disposed on a carrier 20 and a bonding layer 24 is formed so that the electronic component 21 is electrically connected to the carrier 20, wherein the carrier 20 is defined with at least one function The chip placement area A of the electronic component 21 (as shown in FIG. 3A) is set, and the outline of the electronic component 21 after being placed on the carrier 20 does not correspond to the boundary of the chip placement area A.

In this embodiment, the carrier 20 is, for example, a package substrate with a core layer and a circuit structure or a coreless circuit structure, which forms a circuit layer on a dielectric material, such as fan-out ( Fan out) type redistribution layer (RDL). For example, the die placement area A of the carrier 20 is defined as a rectangle, such as a square as shown in FIG. 3A. It should be understood that the supporting member 20 can also be other supporting structures capable of supporting electronic components such as chips, such as a lead frame or a silicon interposer, and is not limited to the above.

Furthermore, the electronic component 21 is an active component, a passive component, or a combination of the two, etc., which has a rectangular quadrilateral sheet body (a square sheet body as shown in FIG. 3A), so that the electronic component 21 is positioned relative to the The deflection configuration of the die region A, such as turning a 90 degree angle, makes the corner of the electronic component 21 located on the edge line L of the die placement region A without correspondingly located at the corner of the die placement region A, wherein the active component is For example, it is a semiconductor chip, and the passive element is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 21 has an opposite active surface 21a and a non-active surface 21b, and the active surface 21a is provided with a plurality of conductive bumps 210, so that the electronic component 21 is combined and electrically connected by the conductive bumps 210 in a flip chip manner. The carrier 20 is sexually connected, and the conductive bumps 210 can be covered with a primer 211. However, there are many ways for the electronic component 21 to connect to the carrier 20, such as wire bonding and packaging, which are not limited to the above.

In addition, the non-acting surface 21b of the electronic component 21 may be formed with a thermally conductive layer 22 such as a thermal interface material (TIM) or a general thermally conductive adhesive.

In addition, the bonding layer 24 is an adhesive layer such as glue, which is located at the edge of the carrier 20 to surround the periphery of the electronic component 21, so that the bonding layer 24 presents a rectangular ring with a plurality of notches 240, and The plurality of notches 240 are formed on two of the four ring edges 24a, 24b, 24c, and 24d, as shown in FIGS. 3A and 3B. For example, the notches 240 are formed on the two opposite ring edges 24a, 24b, and the positions of the notches 240 can be aligned with each other (the same axis Y as shown in FIG. 3A) or not aligned (as shown in FIG. 3B) , So that the corners of the electronic component 21 are aligned with the bonding layer 24 and not aligned with the notches 240, that is, the diagonal lines X1, X2 of the electronic component 21 will not extend through the notches 240. Preferably, in one of the two ring sides 24a, 24b of the bonding layer 24 having the notches 240, as shown in FIG. 3B, the supporting member 20 corresponds to the area (length) R exposed to the notch 240 It is 1/10 of the area (length) D of the carrying member 20 for contacting and joining the ring side 24a.

As shown in FIG. 2B, a heat dissipation element 23 is combined with the bonding layer 24 to be disposed on the carrier 20, and the heat dissipation element 23 is disposed on the electronic component 21 through the thermally conductive layer 22 to cover the electronic component 21.

In this embodiment, the heat sink 23 has a heat sink 230 and a plurality of supporting legs 231 disposed on the lower side of the heat sink 230. The heat sink 230 is a heat sink and contacts the heat conducting layer 22 on the lower side, and The supporting legs 231 are connected to the bonding layer 24 with their ends. For example, the heat dissipating member 23 is arranged on the supporting member 20 in a pressing manner, and the pressing temperature (that is, the heat-resistant temperature of the supporting member 20) is at least 120°C, preferably 125°C.

Furthermore, the heat sink 230 and the support leg 231 are integrally formed; in other embodiments, the heat sink 230 and the support leg 231 may be manufactured separately instead of being integrally formed. It should be understood that there are many types of the heat sink, which are not limited to the above.

In addition, the layout area of the bonding layer 24 can be designed according to requirements. For example, the bonding layer 34 may include a first section 341 and a second section 342 separated from each other, as shown in FIG. 3C, so that the first section 341 A plurality of notches 340 are formed between the end and the end of the second section 342, and the shape of the first section 341 is different from the shape of the second section 342. Preferably, the area of the supporting member 20 for contacting and joining the first section 341 is the same as the area of the supporting member 20 for contacting and joining the second section 342.

The manufacturing method of the present invention mainly uses the deflection arrangement of the electronic component 21 relative to the die placement area A, so that the contour of the electronic component 21 after being placed on the carrier 20 does not correspond to the boundary of the die placement area A, so that the carrier The component 20 can effectively balance the stress distribution thereon, so compared to the prior art, the electronic package 2 can maintain the distance between the heat sink 230 (or the heat sink 23) and the carrier 20 to avoid the heat dissipation Delamination occurs between the body 230 (or the heat sink 23) and the thermally conductive layer 22 (or the electronic component 21), which can improve the reliability of the electronic package 2. It should be understood that the appearance contour of the electronic component 21 can also be changed so that the contour after being disposed on the carrier 20 does not correspond to the boundary of the crystal placement area A, such as a diamond-shaped quadrilateral chip body.

Furthermore, the design of the notches 240 and 340 not facing the corners of the electronic component 21 helps to improve the coverage and flatness of the heat sink 230 (or the heat sink 23), thereby effectively reducing the electronic package The degree of warpage of part 2.

In addition, the size (such as area R or length) of the notch 240 on the single ring side 24a of the bonding layer 24 is designed to be 1/10 of the size (such as area D or length) of the ring side 24a, so as to facilitate The carrier 20 balances the stress distribution thereon, so that the warpage of the electronic package 2 can be effectively reduced.

In addition, the outline of the electronic component 21 after being disposed on the carrier 20 does not correspond to the design of the boundary of the crystal placement area A, which facilitates the circuit layout of the carrier 20 to effectively match the specially designed electronic component 21. The computing power of the electronic component 21 can be enhanced.

The present invention further provides an electronic package 2, which includes: a carrier 20, at least one electronic component 21, a bonding layer 24, 34, and a heat sink 23.

The carrier 20 has at least one crystal placement area A.

The electronic component 21 is disposed on the carrier 20 and is located in the crystal placement area A and electrically connected to the carrier 20, wherein the contour of the electronic component 21 after being disposed on the carrier 20 is not aligned The boundary of the crystal area A should be set.

The bonding layers 24 and 34 are formed on the carrier 20 and located outside the crystal placement area A to surround the electronic component 21.

The heat sink 23 is combined with the bonding layers 24 and 34 to be arranged on the carrier 20 and cover the electronic component 21.

In one embodiment, the die placement area A is rectangular, and the electronic component 21 has a quadrilateral profile, so that the corners of the electronic component 21 are located on the edge line L of the die placement area A. For example, the corners of the electronic component 21 are aligned with the bonding layers 24 and 34.

In one embodiment, the bonding layer 24, 34 is a ring with a plurality of notches 240, 340, and the positions of the plurality of notches 240, 340 are aligned or not aligned with each other. For example, the electronic component 21 has a rectangular outline, and its corners are not aligned with the notches 240 and 340. Alternatively, the ring system is rectangular, and the plurality of notches 240 are respectively located on different ring sides 24a, 24b of the ring body. Preferably, the size of the notch 240 on a single ring side 24a of the ring body is that of the ring. 1/10 of the size of side 24a.

In one embodiment, the bonding layer 34 includes a first section 341 and a second section 342 separated from each other, so as to form a plurality of sections between the end of the first section 341 and the end of the second section 342 There is a gap 340, and the shape of the first section 341 is different from the shape of the second section 342. For example, the area of the supporting member 20 for contacting and joining the first section 341 is the same as the area of the supporting member 20 for contacting and joining the second section 342.

In summary, the electronic package and its manufacturing method of the present invention balance the overall stress distribution of the electronic package by the fact that the outline of the electronic component after being disposed on the carrier does not correspond to the boundary of the crystal placement region. Therefore, the electronic package can maintain the distance between the heat sink and the carrier, so as to avoid delamination between the heat sink and the electronic component, thereby improving the reliability of the electronic package.

Furthermore, since the position of the notch does not face the corner of the electronic component, the coverage and flatness of the heat sink can be improved, and the warpage of the electronic package can be effectively reduced.

In addition, the size of the notch on the single ring edge of the bonding layer is designed to be 1/10 of the size of the ring edge, which is beneficial to balance the stress distribution on the carrier, thereby effectively reducing the size of the electronic package. The degree of warpage.

The above-mentioned embodiments are used to exemplify the principles and effects of the present invention, but not to limit the present invention. Anyone familiar with this technique can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

20: Carrier

21: Electronic components

24: Bonding layer

240: gap

A: Placement area

L: Sideline

X1, X2: diagonal

Y: axis

Claims (18)

An electronic package includes: a carrier, which defines a die placement area; an electronic component, which is arranged in the die placement area of the carrier and is electrically connected to the carrier, wherein the electronic component is placed on the carrier The outline on the top does not correspond to the boundary of the crystal placement area; the bonding layer is a ring with a plurality of notches, which is placed on the carrier and located outside the crystal placement area to surround the electronic component; and the heat sink is bonded The bonding layer is arranged on the carrier and covers the electronic element. The electronic package according to claim 1, wherein the die placement area is rectangular, and the electronic component has a quadrilateral outline, so that the corner of the electronic component is located on the edge of the die placement area. The electronic package according to claim 2, wherein the corner of the electronic component is aligned with the bonding layer. The electronic package according to claim 1, wherein the positions of the plurality of notches are aligned or misaligned with each other. The electronic package according to claim 1, wherein the electronic component has a rectangular outline, and its corners are not aligned with the notch. The electronic package according to claim 1, wherein the ring system is rectangular, and the plurality of notches are respectively located on different ring sides of the ring body. The electronic package according to claim 6, wherein the size of the notch on the single ring side of the ring body is 1/10 of the size of the ring side. The electronic package according to claim 1, wherein the bonding layer includes a first section and a second section separated from each other, so as to form a plurality of gaps between the first section and the second section, And the shape of the first section is different from the shape of the second section. The electronic package according to claim 8, wherein the area of the carrier for contacting and joining the first section is the same as the area of the carrier for contacting and joining the second section. A manufacturing method of an electronic package includes: providing a carrier defining a die placement area; arranging electronic components in the die placement area of the carrier and electrically connecting the carrier, and arranging a bonding layer on the carrier The chip placement area of the device is outside and surrounds the electronic device, wherein the outline of the electronic device disposed on the carrier does not correspond to the boundary of the chip placement area, and the bonding layer is a ring body with a plurality of notches; and The heat dissipation element is combined with the bonding layer, so that the heat dissipation element is arranged on the carrier and covers the electronic element. The method for manufacturing an electronic package according to claim 10, wherein the die placement area is rectangular, and the electronic component has a quadrilateral outline, so that the corner of the electronic component is located on the edge of the die placement area. The method for manufacturing an electronic package according to claim 11, wherein the corner of the electronic component is aligned with the bonding layer. The method for manufacturing an electronic package according to claim 10, wherein the positions of the plurality of notches are aligned or misaligned with each other. The method for manufacturing an electronic package according to claim 10, wherein the electronic component has a rectangular outline, and its corners are not aligned with the notch. The method for manufacturing an electronic package according to claim 10, wherein the ring system is rectangular, and the plurality of notches are respectively located on different ring sides of the ring body. The method for manufacturing an electronic package according to claim 15, wherein the size of the notch on a single ring side of the ring body is 1/10 of the size of the ring side. The method for manufacturing an electronic package according to claim 10, wherein the bonding layer includes a first section and a second section separated from each other, so as to form a plurality of parts between the first section and the second section Notches, and the shape of the first section is different from the shape of the second section. The method for manufacturing an electronic package according to claim 17, wherein the area of the carrier for contacting and joining the first section is the same as the area of the carrier for contacting and joining the second section.

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