TWI735398B - Electronic package and manufacturing method thereof - Google Patents
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- TWI735398B TWI735398B TW109145277A TW109145277A TWI735398B TW I735398 B TWI735398 B TW I735398B TW 109145277 A TW109145277 A TW 109145277A TW 109145277 A TW109145277 A TW 109145277A TW I735398 B TWI735398 B TW I735398B
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- 239000000306 component Substances 0.000 description 61
- 239000010410 layer Substances 0.000 description 38
- 239000004065 semiconductor Substances 0.000 description 21
- 238000004806 packaging method and process Methods 0.000 description 5
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- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
Description
本發明係有關一種半導體裝置,尤指一種具散熱件之電子封裝件及其製法。 The present invention relates to a semiconductor device, in particular to an electronic package with a heat sink and its manufacturing method.
隨著電子產品在功能及處理速度之需求的提升,作為電子產品之核心組件的半導體晶片需具有更高密度之電子元件(Electronic Components)及電子電路(Electronic Circuits)。為了迅速將熱能散逸至大氣中,通常在半導體封裝結構中配置散熱片(Heat Sink或Heat Spreader),該散熱片通常藉由散熱膠結合至晶片背面,以藉散熱膠與散熱片逸散出半導體晶片所產生之熱量。 With the increase in the function and processing speed of electronic products, semiconductor chips, which are the core components of electronic products, need to have higher density of electronic components (Electronic Components) and electronic circuits (Electronic Circuits). In order to quickly dissipate heat to the atmosphere, a heat sink (Heat Sink or Heat Spreader) is usually arranged in the semiconductor package structure. The heat sink is usually bonded to the back of the chip by a heat sink, so that the heat sink and the heat sink can escape the semiconductor The heat generated by the chip.
如圖1A所示,習知散熱型之半導體封裝件1之製法係先將一半導體晶片11以其作用面11a利用覆晶接合方式(即透過導電凸塊110與底膠111)設於一封裝基板10之置晶區A(如圖1A’所示)上,再將一散熱件13以其頂片130藉由導熱層12結合於該半導體晶片11之非作用面11b上,且該散熱件13之支撐腳131藉由黏著層14架設於該封裝基板10上。接著,進行封裝壓模作業,以供封裝膠體(圖略)包覆該半導體晶片11及散熱件13,並使該散熱件13之頂片130外露出封裝膠體而直接與大氣接觸。
As shown in FIG. 1A, the conventional heat-dissipating semiconductor package 1 is made by first placing a
於運作時,該半導體晶片11所產生之熱能係經由該非作用面11b、導熱層12而傳導至該散熱件13以散熱至該半導體封裝件1之外部。
During operation, the heat energy generated by the
惟,習知半導體封裝件1中,該半導體晶片11於設置後之輪廓係對應該置晶區A之邊界(如圖1A’所示),使該散熱件13及該半導體晶片11兩者因與該導熱層12具有極大之熱膨脹係數差異(CTE Mismatch)而所產生之應力無法分散,導致該半導體封裝件1發生變形的情況(即翹曲),如圖1B所示,致使該散熱件13之頂片130與變形之導熱層12’(或與該半導體晶片11)之間容易發生脫層(如圖1B所示之間隙t),不僅造成導熱效果下降,且會降低該半導體封裝件1之信賴性。
However, in the conventional semiconductor package 1, the contour of the
因此,如何克服上述習知技術之種種問題,實已成為目前業界亟待克服之難題。 Therefore, how to overcome the various problems of the above-mentioned conventional technology has actually become a problem that the industry urgently needs to overcome.
鑑於上述習知技術之種種缺失,本發明係提供一種電子封裝件,係包括:承載件,係定義有置晶區;電子元件,係設於該承載件之置晶區內並電性連接該承載件,其中,該電子元件設置於該承載件上之輪廓並未對應該置晶區之邊界;結合層,係設該承載件上且位於該置晶區外,以環繞該電子元件;以及散熱件,係結合該結合層以設於該承載件上並遮蓋該電子元件。 In view of the various deficiencies of the above-mentioned conventional technologies, the present invention provides an electronic package, which includes: a carrier, which defines a die placement area; and an electronic component, which is arranged in the die placement area of the carrier and is electrically connected to the A carrier, wherein the outline of the electronic component disposed on the carrier does not correspond to the boundary of the die placement region; the bonding layer is provided on the carrier and located outside the die placement region to surround the electronic component; and The heat dissipation element is combined with the bonding layer to be arranged on the carrier and cover the electronic element.
本發明亦提供一種電子封裝件之製法,係包括:提供一定義有置晶區之承載件;將電子元件設於該承載件之置晶區內並電性連接該承載件,且將結合層設於該承載件之置晶區外並環繞該電子元件,其中,該電子元件設置於該 承載件上之輪廓並未對應該置晶區之邊界;以及將散熱件結合該結合層,使該散熱件設於該承載件上並遮蓋該電子元件。 The present invention also provides a method for manufacturing an electronic package, which includes: providing a carrier defining a die placement area; arranging electronic components in the die placement area of the carrier and electrically connecting the carrier, and attaching a bonding layer Is arranged outside the chip placement area of the carrier and surrounds the electronic element, wherein the electronic element is arranged on the The contour on the carrier does not correspond to the boundary of the crystal placement area; and the heat dissipation element is combined with the bonding layer so that the heat dissipation element is disposed on the carrier and covers the electronic component.
前述之電子封裝件及其製法中,該置晶區為矩形,且該電子元件係呈四邊形輪廓,以令該電子元件之角落位於該置晶區之邊線上。例如,該電子元件之角落係對準該結合層。 In the aforementioned electronic package and its manufacturing method, the die placement area is rectangular, and the electronic component has a quadrilateral outline, so that the corner of the electronic component is located on the edge of the die placement area. For example, the corners of the electronic component are aligned with the bonding layer.
前述之電子封裝件及其製法中,該結合層係為具有複數缺口之環體,其中,該複數缺口之位置係相互對齊或未對齊。例如,該電子元件係呈矩形輪廓,其角落未對準該缺口。或者,該環體係呈矩形,且該複數缺口係分別位於該環體之不同環邊上,較佳者,該環體之單一環邊上之缺口之尺寸係為該環邊之尺寸的1/10。
In the aforementioned electronic package and its manufacturing method, the bonding layer is a ring with a plurality of notches, wherein the positions of the plurality of notches are aligned or not aligned with each other. For example, the electronic component has a rectangular outline, and its corners are not aligned with the notch. Alternatively, the ring system is rectangular, and the plurality of notches are respectively located on different ring sides of the ring body. Preferably, the size of the notch on a single ring side of the ring body is 1/the size of the
前述之電子封裝件及其製法中,該結合層係包含相分離之第一區段與第二區段,以於該第一區段與該第二區段之間形成複數缺口,且該第一區段之形狀與該第二區段之形狀不相同。例如,該承載件用以接觸結合該第一區段之面積與該承載件用以接觸結合該第二區段之面積係相同。 In the aforementioned electronic package and its manufacturing method, the bonding layer includes a first section and a second section that are separated to form a plurality of gaps between the first section and the second section, and the first section The shape of one section is different from the shape of the second section. For example, the area of the carrier for contacting and joining the first section is the same as the area of the carrier for contacting and joining the second section.
由上可知,本發明之電子封裝件及其製法中,主要藉由該電子元件於設置於該承載件上後之輪廓未對應該置晶區之邊界,使該承載件能有效平衡其上應力分佈,故相較於習知技術,該電子封裝件能維持該散熱件與該承載件之間的距離,以避免該散熱件與該電子元件之間發生脫層,進而能提升該電子封裝件之信賴性。 It can be seen from the above that in the electronic package and the manufacturing method of the present invention, the outline of the electronic component after being placed on the carrier does not correspond to the boundary of the crystal placement region, so that the carrier can effectively balance the stress on it Therefore, compared with the prior art, the electronic package can maintain the distance between the heat sink and the carrier, so as to avoid delamination between the heat sink and the electronic component, thereby improving the electronic package The reliability.
再者,本發明藉由該缺口之位置不會朝向該電子元件之角落之設計,以利於提升該散熱件的覆蓋率及平面度,因而能有效降低該電子封裝件之翹曲程度。 Furthermore, in the present invention, the position of the notch does not face the corner of the electronic component, so as to improve the coverage and flatness of the heat sink, thereby effectively reducing the degree of warpage of the electronic package.
又,本發明藉由該結合層之單一環邊上之缺口之尺寸係為該環邊之尺寸的1/10之設計,以利於該承載件平衡其上之應力分佈,因而能有效降低該電子封裝件之翹曲程度。 In addition, in the present invention, the size of the notch on the single ring edge of the bonding layer is designed to be 1/10 of the size of the ring edge, so as to facilitate the load-bearing member to balance the stress distribution thereon, thereby effectively reducing the electrons. The degree of warpage of the package.
另外,本發明藉由該電子元件於設置於該承載件上後之輪廓未對應該置晶區之邊界,以利於該承載件之線路佈設能有效搭配特殊設計之電子元件,因而能增強該電子元件之運算能力。 In addition, in the present invention, the outline of the electronic component after being placed on the carrier does not correspond to the boundary of the crystal placement region, so that the circuit layout of the carrier can effectively match the specially designed electronic components, thereby enhancing the electronic components. The computing power of the component.
1:半導體封裝件 1: Semiconductor package
10:封裝基板 10: Package substrate
11:半導體晶片 11: Semiconductor wafer
11a,21a:作用面 11a, 21a: action surface
11b,21b:非作用面 11b, 21b: non-acting surface
110,210:導電凸塊 110, 210: conductive bump
111,211:底膠 111,211: primer
12,12’,22:導熱層 12,12’,22: Thermally conductive layer
13,23:散熱件 13,23: Heat sink
130:頂片 130: top piece
131,231:支撐腳 131,231: Support feet
14:黏著層 14: Adhesive layer
2:電子封裝件 2: Electronic package
20:承載件 20: Carrier
21:電子元件 21: Electronic components
230:散熱體 230: heat sink
24,34:結合層 24, 34: Bonding layer
24a,24b,24c,24d:環邊 24a, 24b, 24c, 24d: ring edge
240,340:缺口 240,340: gap
341:第一區段 341: The first section
342:第二區段 342: Second Section
A:置晶區 A: Placement area
D,R:面積 D, R: area
L:邊線 L: Sideline
t:間隙 t: gap
X1,X2:對角線 X1, X2: diagonal
Y:軸線 Y: axis
圖1A係為習知半導體封裝件之剖視示意圖。 FIG. 1A is a schematic cross-sectional view of a conventional semiconductor package.
圖1A’係為圖1A之上視平面示意圖。 Fig. 1A' is a schematic top plan view of Fig. 1A.
圖1B係為習知半導體封裝件之不良狀態之剖視示意圖。 FIG. 1B is a schematic cross-sectional view of a bad state of a conventional semiconductor package.
圖2A至圖2B係為本發明之電子封裝件之製法之剖視示意圖。 2A to 2B are schematic cross-sectional views of the manufacturing method of the electronic package of the present invention.
圖3A係為圖2A之上視平面示意圖。 Fig. 3A is a schematic top plan view of Fig. 2A.
圖3B及圖3C係為圖3A之不同態樣之上視平面示意圖。 3B and 3C are schematic top plan views of different aspects of FIG. 3A.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the other advantages and effects of the present invention from the contents disclosed in this specification.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中 所引用之如「上」、「第一」、「第二」、「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structure, ratio, size, etc. shown in the drawings in this manual are only used to match the content disclosed in the manual for the understanding and reading of those who are familiar with the art, and are not intended to limit the implementation of the present invention. Therefore, it does not have any technical significance. Any structural modification, proportional relationship change or size adjustment should still fall within the original The technical content disclosed by the invention can be covered. At the same time, in this manual The quoted terms such as "on", "first", "second", "one", etc. are also only for ease of description, and are not used to limit the scope of implementation of the present invention, and changes in their relative relationships Or adjustments, without substantive changes to the technical content, should also be regarded as the scope of the present invention can be implemented.
圖2A至圖2B係為本發明之電子封裝件2之製法之剖面示意圖。
2A to 2B are schematic cross-sectional views of the manufacturing method of the
如圖2A所示,於一承載件20上設置至少一電子元件21及形成結合層24,以令該電子元件21電性連接該承載件20,其中,該承載件20係定義有至少一用以設置該電子元件21之置晶區A(如圖3A所示),且令該電子元件21於設置於該承載件20上後之輪廓未對應該置晶區A之邊界。
As shown in FIG. 2A, at least one
於本實施例中,該承載件20例如為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之線路結構,其係於介電材上形成線路層,如扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL)。例如,該承載件20之置晶區A係定義為矩形,如圖3A所示之正方形。應可理解地,該承載件20亦可為其它可供承載如晶片等電子元件之承載結構,例如導線架(lead frame)或矽中介板(silicon interposer),並不限於上述。
In this embodiment, the
再者,該電子元件21係為主動元件、被動元件或其二者組合等,其呈如矩形之四邊形片體(如圖3A所示之正方形片體),以令該電子元件21相對該置晶區A偏轉配置,如轉90度角,使該電子元件21之角落位於該置晶區A之邊線L上而未對應配合坐落於該置晶區A之角落處,其中,該主動元件係例如為半導體晶片,且該被動元件係例如為電阻、電容及電感。例如,該電子元件21具有相對之作用面21a及非作用面21b,且該作用面21a設有複數導電凸塊210,使該電子元件21藉該些導電凸塊210以覆晶方式結合並電性連接該承載件20,並可以底膠211包覆該些導電凸塊210。然而,有關該電子元件21連接該承載件20之方式繁多,如打線封裝方式,並不限於上述。
Furthermore, the
又,該電子元件21之非作用面21b上可形成如導熱介面材(Thermal Interface Material,簡稱TIM)或一般導熱膠之導熱層22。
In addition, the
另外,該結合層24係為如膠材之黏著層,其位於於該承載件20之邊緣,以環繞該電子元件21之外圍,使該結合層24呈現具有複數缺口240之矩形環體,且該複數缺口240係形成於四個環邊24a,24b,24c,24d之其中兩者上,如圖3A及圖3B所示。例如,該些缺口240係形成於相對之兩環邊24a,24b上,且該些缺口240之位置可相互對齊(如圖3A所示之同一軸線Y)或未對齊(如圖3B所示),以令該電子元件21之角落係對準該結合層24,而不會對準該些缺口240,即該電子元件21之對角線X1,X2不會延伸通過該些缺口240。較佳地,於該結合層24之具有該些缺口240之兩環邊24a,24b之其中一者中,如圖3B所示,該承載件20對應外露於該缺口240的面積(長度)R係為該承載件20用以接觸結合該環邊24a之面積(長度)D的1/10。
In addition, the
如圖2B所示,將一散熱件23結合該結合層24,以設於該承載件20上,且該散熱件23藉由導熱層22設於該電子元件21上以遮蓋該電子元件21。
As shown in FIG. 2B, a
於本實施例中,該散熱件23係具有一散熱體230與複數設於該散熱體230下側之支撐腳231,該散熱體230係為散熱片並以下側接觸該導熱層22,且該支撐腳231係以其端部結合該結合層24上。例如,該散熱件23係以壓合方式設於該承載件20上,且該壓合溫度(即該承載件20之耐熱溫度)係至少為120℃,最佳為125℃。
In this embodiment, the
再者,該散熱體230與該支撐腳231係為一體成形;於其它實施例中,該散熱體230與該支撐腳231可為分開製作,而非一體成形。應可理解地,有關該散熱件之種類繁多,並不限於上述。
Furthermore, the
又,該結合層24之佈設面積係可依需求設計。例如,該結合層34可包含相分離之第一區段341與第二區段342,如圖3C所示,以於該第一區段341
端處與該第二區段342端處之間形成複數缺口340,且該第一區段341之形狀與該第二區段342之形狀不相同。較佳者,該承載件20用以接觸結合該第一區段341之面積與該承載件20用以接觸結合該第二區段342之面積係相同。
In addition, the layout area of the
本發明之製法主要藉由該電子元件21相對該置晶區A偏轉配置,以令該電子元件21於設置於該承載件20上後之輪廓未對應該置晶區A之邊界,使該承載件20能有效平衡其上應力分佈,故相較於習知技術,該電子封裝件2能維持該散熱體230(或該散熱件23)與該承載件20之間的距離,以避免該散熱體230(或該散熱件23)與該導熱層22(或該電子元件21)之間發生脫層(delamination),進而能提升該電子封裝件2之信賴性。應可理解地,亦可改變該電子元件21之外觀輪廓,使其於設置於該承載件20上後之輪廓未對應該置晶區A之邊界,如菱形之四邊形晶片本體。
The manufacturing method of the present invention mainly uses the deflection arrangement of the
再者,藉由該缺口240,340之位置不會朝向該電子元件21之角落之設計,以利於提升該散熱體230(或該散熱件23)的覆蓋率及平面度,因而能有效降低該電子封裝件2之翹曲程度。
Furthermore, the design of the
又,藉由該結合層24之單一環邊24a上之缺口240之尺寸(如面積R或長度)係為該環邊24a之尺寸(如面積D或長度)的1/10之設計,以利於該承載件20平衡其上之應力分佈,因而能有效降低該電子封裝件2之翹曲程度。
In addition, the size (such as area R or length) of the
另外,藉由該電子元件21於設置於該承載件20上後之輪廓未對應該置晶區A之邊界之設計,以利於該承載件20之線路佈設有效搭配特殊設計之電子元件21,因而能增強該電子元件21之運算能力。
In addition, the outline of the
本發明復提供一種電子封裝件2,係包括:一承載件20、至少一電子元件21、一結合層24,34以及一散熱件23。
The present invention further provides an
所述之承載件20係具有至少一置晶區A。
The
所述之電子元件21係設於該承載件20上且位於該置晶區A內並電性連接該承載件20,其中,該電子元件21於設置於該承載件20上後之輪廓未對應該置晶區A之邊界。
The
所述之結合層24,34係形成該承載件20上且位於該置晶區A外,以環繞該電子元件21。
The bonding layers 24 and 34 are formed on the
所述之散熱件23係結合該結合層24,34以設於該承載件20上並遮蓋該電子元件21。
The
於一實施例中,該置晶區A為矩形,且該電子元件21係呈四邊形輪廓,以令該電子元件21之角落位於該置晶區A之邊線L上。例如,該電子元件21之角落係對準該結合層24,34。
In one embodiment, the die placement area A is rectangular, and the
於一實施例中,該結合層24,34係為具有複數缺口240,340之環體,且該複數缺口240,340之位置係相互對齊或未對齊。例如,該電子元件21係呈矩形輪廓,其角落未對準該缺口240,340。或者,該環體係呈矩形,且該複數缺口240係分別位於該環體之不同環邊24a,24b上,較佳者,該環體之單一環邊24a上之缺口240之尺寸係為該環邊24a之尺寸的1/10。
In one embodiment, the
於一實施例中,該結合層34係包含相分離之第一區段341與第二區段342,以於該第一區段341端處與該第二區段342端處之間形成複數缺口340,且該第一區段341之形狀與該第二區段342之形狀不相同。例如,該承載件20用以接觸結合該第一區段341之面積與該承載件20用以接觸結合該第二區段342之面積係相同。
In one embodiment, the
綜上所述,本發明之電子封裝件及其製法,係藉由該電子元件於設置於該承載件後之輪廓未對應該置晶區之邊界,以平衡該電子封裝件之整體應力分佈,故該電子封裝件能維持該散熱件與該承載件之間的距離,以避免該散熱件與該電子元件之間發生脫層,進而能提升該電子封裝件之信賴性。 In summary, the electronic package and its manufacturing method of the present invention balance the overall stress distribution of the electronic package by the fact that the outline of the electronic component after being disposed on the carrier does not correspond to the boundary of the crystal placement region. Therefore, the electronic package can maintain the distance between the heat sink and the carrier, so as to avoid delamination between the heat sink and the electronic component, thereby improving the reliability of the electronic package.
再者,因該缺口之位置不會朝向該電子元件之角落,故能提升該散熱件的覆蓋率及平面度,因而能有效降低該電子封裝件之翹曲程度。 Furthermore, since the position of the notch does not face the corner of the electronic component, the coverage and flatness of the heat sink can be improved, and the warpage of the electronic package can be effectively reduced.
又,藉由該結合層之單一環邊上之缺口之尺寸係為該環邊之尺寸的1/10之設計,以利於平衡該承載件上之應力分佈,因而能有效降低該電子封裝件之翹曲程度。 In addition, the size of the notch on the single ring edge of the bonding layer is designed to be 1/10 of the size of the ring edge, which is beneficial to balance the stress distribution on the carrier, thereby effectively reducing the size of the electronic package. The degree of warpage.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above-mentioned embodiments are used to exemplify the principles and effects of the present invention, but not to limit the present invention. Anyone familiar with this technique can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.
20:承載件 20: Carrier
21:電子元件 21: Electronic components
24:結合層 24: Bonding layer
240:缺口 240: gap
A:置晶區 A: Placement area
L:邊線 L: Sideline
X1,X2:對角線 X1, X2: diagonal
Y:軸線 Y: axis
Claims (18)
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US20150228553A1 (en) * | 2012-08-29 | 2015-08-13 | Broadcom Corporation | Hybrid thermal interface material for ic packages with integrated heat spreader |
WO2018063213A1 (en) * | 2016-09-29 | 2018-04-05 | Intel Corporation | Methods of forming flexure based cooling solutions for package structures |
TW202044496A (en) * | 2019-05-15 | 2020-12-01 | 聯發科技股份有限公司 | Electronic package |
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US20150228553A1 (en) * | 2012-08-29 | 2015-08-13 | Broadcom Corporation | Hybrid thermal interface material for ic packages with integrated heat spreader |
WO2018063213A1 (en) * | 2016-09-29 | 2018-04-05 | Intel Corporation | Methods of forming flexure based cooling solutions for package structures |
TW202044496A (en) * | 2019-05-15 | 2020-12-01 | 聯發科技股份有限公司 | Electronic package |
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