TWI555147B - Heat-dissipation package structure and its heat sink - Google Patents
Heat-dissipation package structure and its heat sink Download PDFInfo
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- TWI555147B TWI555147B TW104108923A TW104108923A TWI555147B TW I555147 B TWI555147 B TW I555147B TW 104108923 A TW104108923 A TW 104108923A TW 104108923 A TW104108923 A TW 104108923A TW I555147 B TWI555147 B TW I555147B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Description
本發明係有關一種封裝結構，尤指一種散熱型封裝結構及其散熱件。 The invention relates to a package structure, in particular to a heat dissipation package structure and a heat dissipation member thereof.
隨著電子產品在功能及處理速度之需求的提升，作為電子產品之核心組件的半導體晶片需具有更高密度之電子元件(Electronic Components)及電子電路(Electronic Circuits)，故半導體晶片在運作時將隨之產生更大量的熱能，且包覆該半導體晶片之封裝膠體係為一種導熱係數僅0.8Wm-1k-1之不良傳熱材質(即熱量之逸散效率不佳)，因而若不能有效逸散所產生之熱量，則會造成半導體晶片之損害或造成產品信賴性問題。 As the demand for functions and processing speed of electronic products increases, semiconductor wafers, which are the core components of electronic products, require higher density electronic components and electronic circuits, so semiconductor wafers will operate. A larger amount of thermal energy is generated, and the encapsulant system covering the semiconductor wafer is a poor heat transfer material having a thermal conductivity of only 0.8 Wm -1 k -1 (that is, the heat dissipation efficiency is not good), and thus cannot be effective. The heat generated by the dissipation can cause damage to the semiconductor wafer or cause product reliability problems.
因此，為了迅速將熱能散逸至大氣中，通常在半導體封裝結構中配置散熱片(Heat Sink或Heat Spreader)，且傳統散熱片係藉由散熱膠結合至晶片背面，以藉散熱膠與散熱片逸散出半導體晶片所產生之熱量，通常以散熱片之頂面外露出封裝膠體或直接外露於大氣中為佳，俾取得較佳之散熱效果。 Therefore, in order to quickly dissipate thermal energy into the atmosphere, a heat sink (Heat Sink or Heat Spreader) is usually disposed in the semiconductor package structure, and the conventional heat sink is bonded to the back surface of the wafer by a heat sink adhesive to utilize the heat sink and the heat sink. The heat generated by the semiconductor wafer is usually released from the top surface of the heat sink to expose the encapsulant or directly exposed to the atmosphere, so that a better heat dissipation effect can be obtained.
然而，散熱膠已不符合製程需求，故遂發展出導熱介面材(Thermal Interface Material，簡稱TIM)製程。 However, the thermal adhesive has not met the requirements of the process, so the thermal interface material (TIM) process has been developed.
習知TIM層係為低溫熔融之熱傳導材料(如銲錫材料)，其設於半導體晶片背面與散熱片之間，而為了提升TIM層與晶片背面之間的接著強度，需於晶片背面上覆金(即所謂之Coating Gold On Chip Back)，且需使用助焊劑(flux)，以利於該TIM層接著於該金層上。 The conventional TIM layer is a low-temperature melting heat conductive material (such as a solder material) disposed between the back surface of the semiconductor wafer and the heat sink, and in order to improve the bonding strength between the TIM layer and the back surface of the wafer, it is necessary to apply gold on the back surface of the wafer. (The so-called Coating Gold On Chip Back), and a flux is needed to facilitate the TIM layer to follow the gold layer.
如第1A圖所示，習知半導體封裝結構1之製法係先將一半導體晶片11以其作用面11a利用覆晶接合方式(即透過導電凸塊110與底膠111)設於一封裝基板10上，且將一金層(圖略)形成於該半導體晶片11之非作用面11b上，再將一散熱件13以其頂片130藉由TIM層12(其包含銲錫層與助焊劑)回銲結合於該金層上，且該散熱件13之支撐腳131藉由黏著層14架設於該封裝基板10上。接著，進行封裝壓模作業，以供封裝膠體(圖略)包覆該半導體晶片11及散熱件13，並使該散熱件13之頂片130外露出封裝膠體而直接與大氣接觸。 As shown in FIG. 1A, the conventional semiconductor package structure 1 is formed by first mounting a semiconductor wafer 11 on a package substrate 10 by a flip chip bonding method (ie, through the conductive bumps 110 and the underfill 111). And a gold layer (not shown) is formed on the non-active surface 11b of the semiconductor wafer 11, and a heat sink 13 is returned to the top sheet 130 by the TIM layer 12 (which includes the solder layer and the flux). The soldering is bonded to the gold layer, and the supporting leg 131 of the heat dissipating member 13 is mounted on the package substrate 10 by the adhesive layer 14. Next, a package stamping operation is performed to encapsulate the semiconductor wafer 11 and the heat sink 13 with a package colloid (not shown), and the top sheet 130 of the heat sink 13 is exposed to the encapsulant and directly in contact with the atmosphere.
於運作時，該半導體晶片11所產生之熱能係經由該非作用面11b、金層、TIM層12而傳導至該散熱件13以散熱至該半導體封裝結構1之外部。 During operation, the thermal energy generated by the semiconductor wafer 11 is conducted to the heat sink 13 via the non-active surface 11b, the gold layer, and the TIM layer 12 to dissipate heat to the outside of the semiconductor package structure 1.
惟，當習知半導體封裝結構1之厚度薄化，且其面積越來越大時，使該散熱件13與TIM層12之間的熱膨脹係數差異(CTE Mismatch)而導致變形的情況(即翹曲程度)更明顯，故當變形量過大時，該散熱件13之頂片130與 TIM層12’之間容易發生脫層(如第1B圖所示之間隙d)，不僅造成導熱效果下降，且會造成半導體封裝結構1外觀上的不良，因而嚴重影響產品之信賴性。 However, when the thickness of the conventional semiconductor package structure 1 is thinned and its area is larger and larger, the coefficient of thermal expansion between the heat sink 13 and the TIM layer 12 is changed (CTE Mismatch) to cause deformation (ie, warping). The degree of curvature is more obvious, so when the amount of deformation is too large, the top sheet 130 of the heat sink 13 is The delamination (e.g., the gap d shown in Fig. 1B) is liable to occur between the TIM layers 12', which not only causes a decrease in the heat conduction effect, but also causes a defect in the appearance of the semiconductor package structure 1, thereby seriously affecting the reliability of the product.
因此，如何克服上述習知技術之問題，實已成為目前業界亟待克服之難題。 Therefore, how to overcome the above problems of the prior art has become a difficult problem to be overcome in the industry.
鑑於上述習知技術之種種缺失，本發明提供一種散熱型封裝結構，係包括：承載件；電子元件，係設於該承載件上；結合層，係設於該電子元件上；以及散熱件，係設於該結合層上，且該散熱件具有散熱體、設於該散熱體上之支撐腳與設於該散熱體上之至少一支架，該散熱體係接觸該結合層，且該支撐腳與該支架係結合於該承載件上，又該支架係位於該電子元件與該支撐腳之間。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides a heat-dissipating package structure, comprising: a carrier; an electronic component is disposed on the carrier; a bonding layer is disposed on the electronic component; and a heat sink, The heat dissipating member is disposed on the bonding layer, and the heat dissipating member has a heat dissipating body, a supporting leg disposed on the heat dissipating body, and at least one bracket disposed on the heat dissipating body, the heat dissipating system contacting the bonding layer, and the supporting leg is The bracket is coupled to the carrier, and the bracket is located between the electronic component and the support leg.
前述之散熱型封裝結構中，該承載件係為封裝基板或導線架。 In the above heat dissipation type package structure, the carrier is a package substrate or a lead frame.
前述之散熱型封裝結構中，該電子元件係為主動元件、被動元件、封裝元件或其三者之組合。 In the above heat dissipation type package structure, the electronic component is an active component, a passive component, a package component, or a combination of the three.
前述之散熱型封裝結構中，該結合層係為導熱介面材或導熱膠。 In the above heat dissipation type package structure, the bonding layer is a heat conducting interface material or a thermal conductive adhesive.
前述之散熱型封裝結構中，該支架係鄰近於該電子元件之角落處。 In the aforementioned heat dissipation type package structure, the bracket is adjacent to a corner of the electronic component.
本發明亦提供一種散熱件，係包括：一種散熱件，係包括：散熱體；支撐腳，係設於該散熱體上；以及至少一支架，係設於該散熱體上，且該支架較該支撐腳鄰近該散 熱體中央處。 The present invention also provides a heat dissipating member, comprising: a heat dissipating member, comprising: a heat dissipating body; a supporting leg disposed on the heat dissipating body; and at least one bracket disposed on the heat dissipating body, wherein the bracket is The support foot is adjacent to the dispersion At the center of the hot body.
前述之散熱型封裝結構及其散熱件中，該散熱體係為散熱片。 In the above heat dissipation type package structure and the heat dissipation member thereof, the heat dissipation system is a heat sink.
前述之散熱型封裝結構及其散熱件中，該支架之高度與該支撐腳之高度相同或不相同。 In the above heat dissipation type package structure and the heat dissipation member thereof, the height of the bracket is the same as or different from the height of the support leg.
前述之散熱型封裝結構及其散熱件中，該支架係一體成型於該散熱體上。 In the heat dissipation package structure and the heat dissipation member thereof, the bracket is integrally formed on the heat sink.
前述之散熱型封裝結構及其散熱件中，該支架係黏貼於該散熱體上。 In the heat dissipation package structure and the heat dissipation member thereof, the bracket is adhered to the heat sink.
前述之散熱型封裝結構及其散熱件中，該支架之材質不同於該散熱體之材質。 In the heat dissipation package structure and the heat dissipation member thereof, the material of the bracket is different from the material of the heat sink.
前述之散熱型封裝結構及其散熱件中，該支架之材質係為不導熱材料。 In the heat dissipation package structure and the heat dissipation member thereof, the material of the bracket is a non-thermal material.
前述之散熱型封裝結構及其散熱件中，該支架係為L形柱體。 In the above heat dissipation type package structure and the heat dissipation member thereof, the bracket is an L-shaped cylinder.
由上可知，本發明之散熱型封裝結構，主要藉由增設支架，使該支架相較於該支撐腳更靠近該電子元件周圍，故相較於習知技術，當薄化該散熱型封裝結構之厚度，且該散熱型封裝結構之面積越來越大時，該支架能提供支撐力以維持該散熱體與該承載件之間的距離，因而能避免發生過大之翹曲程度，以避免該散熱體與結合層之間發生脫層，進而提升導熱效果，且能提升產品之信賴性。 As can be seen from the above, the heat-dissipating package structure of the present invention mainly uses a bracket to make the bracket closer to the periphery of the electronic component than the support leg, so that the heat-dissipating package structure is thinned compared with the prior art. The thickness of the heat-dissipating package structure is increased, the support can provide a supporting force to maintain the distance between the heat sink and the carrier, thereby avoiding an excessive warpage to avoid the The delamination occurs between the heat sink and the bonding layer, thereby improving the heat conduction effect and improving the reliability of the product.
1,2‧‧‧封裝結構 1,2‧‧‧Package structure
10‧‧‧封裝基板 10‧‧‧Package substrate
11‧‧‧半導體晶片 11‧‧‧Semiconductor wafer
11a,21a‧‧‧作用面 11a, 21a‧‧‧ action surface
11b,21b‧‧‧非作用面 11b, 21b‧‧‧ non-active surface
110,210‧‧‧導電凸塊 110,210‧‧‧Electrical bumps
111,211‧‧‧底膠 111,211‧‧‧ 底胶
12‧‧‧TIM層 12‧‧‧TIM layer
12’‧‧‧TIM層 12’‧‧‧TIM layer
13,23‧‧‧散熱件 13,23‧‧‧Solder parts
130‧‧‧頂片 130‧‧‧Top film
131,231‧‧‧支撐腳 131,231‧‧‧Support feet
14,24‧‧‧黏著層 14,24‧‧‧Adhesive layer
20‧‧‧承載件 20‧‧‧Carrier
21‧‧‧電子元件 21‧‧‧Electronic components
22‧‧‧結合層 22‧‧‧Combination layer
230‧‧‧散熱體 230‧‧‧ Heat sink
232,232’‧‧‧支架 232,232’‧‧‧ bracket
d‧‧‧間隙 D‧‧‧ gap
h1,h1’,h2‧‧‧高度 H1, h1’, h2‧‧‧ height
第1A圖係為習知半導體封裝結構之剖視示意圖； 第1B圖係為第1A圖之脫層情況之示意圖；第2及2’圖係為本發明散熱型封裝結構之不同實施例之剖視示意圖；以及第3A至3D圖係為第2圖之支架之各種態樣的上視圖。 1A is a schematic cross-sectional view of a conventional semiconductor package structure; 1B is a schematic view of the delamination of FIG. 1A; FIGS. 2 and 2' are schematic cross-sectional views showing different embodiments of the heat dissipation package structure of the present invention; and FIGS. 3A to 3D are diagrams of FIG. A top view of the various aspects of the stent.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower" and "one" are used in the description for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship may be changed or Adjustments, where there is no material change, are considered to be within the scope of the invention.
第2圖係為本發明之散熱型封裝結構2，其包括：一承載件20、一電子元件21、一結合層22以及一散熱件23。 2 is a heat dissipation package structure 2 of the present invention, comprising: a carrier member 20, an electronic component 21, a bonding layer 22, and a heat sink 23.
所述之承載件20係為封裝基板，且有關封裝基板之種類繁多，並無特別限制；於其它實施例中，該承載件20亦可為導線架。 The carrier 20 is a package substrate, and the type of the package substrate is not particularly limited. In other embodiments, the carrier 20 can also be a lead frame.
所述之電子元件21係設於該承載件20上，且該電子元件21係為主動元件、被動元件、封裝元件或其三者之組合。 The electronic component 21 is disposed on the carrier 20, and the electronic component 21 is an active component, a passive component, a package component, or a combination of the three.
於本實施例中，該主動元件係例如半導體晶片，該被動元件係例如電阻、電容及電感，且該封裝元件係包含基板、設於該基板上之晶片及包覆該晶片之封裝層。 In this embodiment, the active component is, for example, a semiconductor chip, such as a resistor, a capacitor, and an inductor, and the package component includes a substrate, a wafer disposed on the substrate, and an encapsulation layer covering the wafer.
再者，該電子元件21具有相對之作用面21a及非作用面21b，且該電子元件21之作用面21a具有複數導電凸塊210，而該電子元件21係藉由該些導電凸塊210結合並電性連接該承載件20，並以底膠211包覆該些導電凸塊210。 Furthermore, the electronic component 21 has an opposite active surface 21a and an inactive surface 21b, and the active surface 21a of the electronic component 21 has a plurality of conductive bumps 210, and the electronic component 21 is bonded by the conductive bumps 210. The carrier 20 is electrically connected, and the conductive bumps 210 are covered with a primer 211.
又，於其它實施例中，該電子元件21亦可以打線封裝方式電性連接該承載件20。 Moreover, in other embodiments, the electronic component 21 can also be electrically connected to the carrier 20 by wire bonding.
所述之結合層22係為導熱介面材或導熱膠，其設於該電子元件21之非作用面21b上。 The bonding layer 22 is a heat conducting interface material or a thermal conductive adhesive disposed on the non-active surface 21b of the electronic component 21.
所述之散熱件23係設於該結合層22上，且該散熱件23具有一散熱體230、設於該散熱體230下側之複數支撐腳231與設於該散熱體230下側之複數支架232，該散熱體230下側係接觸該結合層22，且該支撐腳231與該支架232係以黏著層24結合於該承載件20上，又於該承載件20上，該支架232係位於該電子元件21與該支撐腳231之間。 The heat dissipating member 23 is disposed on the bonding layer 22, and the heat dissipating member 23 has a heat dissipating body 230, a plurality of supporting legs 231 disposed on the lower side of the heat dissipating body 230, and a plurality of supporting legs disposed on the lower side of the heat dissipating body 230. a bracket 232, the lower side of the heat sink 230 contacts the bonding layer 22, and the supporting leg 231 and the bracket 232 are bonded to the carrier 20 by an adhesive layer 24, and the carrier 232 is attached to the carrier 20 Located between the electronic component 21 and the support leg 231.
於本實施例中，該散熱體230係為散熱片，且該支架232較該支撐腳231鄰近該散熱體230中央處，使該支架232係鄰近於該電子元件21之角落處(如第3A至3D圖)。 In this embodiment, the heat sink 230 is a heat sink, and the bracket 232 is adjacent to the center of the heat sink 230 than the support leg 231, so that the bracket 232 is adjacent to a corner of the electronic component 21 (such as the 3A). To 3D map).
再者，該支架232之高度h1與該支撐腳231之高度h2相同。 Furthermore, the height h1 of the bracket 232 is the same as the height h2 of the support leg 231.
於其它實施例中，該支架232之高度h1’與該支撐腳231之高度h2可不相同，即該支架232與該支撐腳231可利用不同厚度之黏著層24結合於該承載件20上。如第2’圖所示，該支架232’之高度h1’小於該支撐腳231之高度h2。該支架232’之高度亦可大於該支撐腳231之高度h2。 In other embodiments, the height h1' of the bracket 232 and the height h2 of the support leg 231 may be different, that is, the bracket 232 and the support leg 231 may be coupled to the carrier 20 by using an adhesive layer 24 of different thickness. As shown in Fig. 2', the height h1' of the bracket 232' is smaller than the height h2 of the support leg 231. The height of the bracket 232' may also be greater than the height h2 of the support leg 231.
又，該支架232與該支撐腳231係以機械加工同時形成，亦即該支架232與該散熱體230係一體成型。或者，可先以導熱或不導熱材料形成該支架232，再將該支架232黏貼於該散熱體230下側。因此，該支架232之材質可不同於該散熱體230之材質。 Moreover, the bracket 232 and the supporting leg 231 are simultaneously formed by machining, that is, the bracket 232 is integrally formed with the heat sink 230. Alternatively, the bracket 232 may be formed of a heat conductive or non-thermal conductive material, and the bracket 232 may be adhered to the lower side of the heat sink 230. Therefore, the material of the bracket 232 can be different from the material of the heat sink 230.
另外，該支架232係為各式形狀之柱體，如第3A至3D圖所示，較佳者為L形。 In addition, the bracket 232 is a column of various shapes, as shown in Figs. 3A to 3D, preferably L-shaped.
本發明之散熱型封裝結構2係藉由該散熱件23增設支架232，使該支架232相較於該支撐腳231更靠近該電子元件21周圍，故當薄化該散熱型封裝結構2之厚度，且該散熱型封裝結構2之面積越來越大時，該散熱型封裝結構2之翹曲(warpage)程度相較於習知封裝結構減少37%，且該電子元件21之表面分離應力(surface peeling stress)減少23%。 The heat dissipation package structure 2 of the present invention is provided with a bracket 232 by the heat sink 23, so that the bracket 232 is closer to the periphery of the electronic component 21 than the support leg 231, so that the thickness of the heat dissipation package structure 2 is thinned. When the area of the heat dissipation package structure 2 is larger and larger, the warpage degree of the heat dissipation package structure 2 is reduced by 37% compared with the conventional package structure, and the surface separation stress of the electronic component 21 is Surface peeling stress) is reduced by 23%.
因此，該支架232能提供結合力以維持該散熱體230中央與該承載件20之間的距離，故能避免該散熱體230與結合層22之間發生脫層，因而不僅能提升導熱效果，且 能提升產品之信賴性。 Therefore, the bracket 232 can provide a bonding force to maintain the distance between the center of the heat sink 230 and the carrier 20, so that delamination between the heat sink 230 and the bonding layer 22 can be avoided, thereby not only improving the heat conduction effect. And Can enhance the reliability of the product.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
2‧‧‧封裝結構 2‧‧‧Package structure
20‧‧‧承載件 20‧‧‧Carrier
21‧‧‧電子元件 21‧‧‧Electronic components
21a‧‧‧作用面 21a‧‧‧Action surface
21b‧‧‧非作用面 21b‧‧‧Non-active surface
210‧‧‧導電凸塊 210‧‧‧Electrical bumps
211‧‧‧底膠 211‧‧‧Bottom glue
22‧‧‧結合層 22‧‧‧Combination layer
23‧‧‧散熱件 23‧‧‧ Heat sink
230‧‧‧散熱體 230‧‧‧ Heat sink
231‧‧‧支撐腳 231‧‧‧Support feet
232‧‧‧支架 232‧‧‧ bracket
24‧‧‧黏著層 24‧‧‧Adhesive layer
h1,h2‧‧‧高度 H1, h2‧‧‧ height
Claims (20)
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| TW104108923A TWI555147B (en) | 2015-03-20 | 2015-03-20 | Heat-dissipation package structure and its heat sink |
| CN201510156193.4A CN106158785B (en) | 2015-03-20 | 2015-04-03 | Heat dissipation type packaging structure and heat dissipation piece thereof |
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| TW104108923A TWI555147B (en) | 2015-03-20 | 2015-03-20 | Heat-dissipation package structure and its heat sink |
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| CN106960828A (en) * | 2017-05-11 | 2017-07-18 | 西安电子科技大学 | Flip-chip type semiconductor packaging structure |
| CN111211059B (en) * | 2018-11-22 | 2023-07-04 | 矽品精密工业股份有限公司 | Electronic package, manufacturing method thereof and heat dissipation part |
| TWI706523B (en) * | 2019-09-02 | 2020-10-01 | 矽品精密工業股份有限公司 | Electronic package |
| TWI730703B (en) * | 2020-03-31 | 2021-06-11 | 大陸商上海兆芯集成電路有限公司 | Chip package |
| CN111739855B (en) * | 2020-08-25 | 2020-11-20 | 苏州通富超威半导体有限公司 | Packaging structure and forming method thereof |
| CN113990809B (en) * | 2021-12-17 | 2022-04-29 | 中兴通讯股份有限公司 | Packaging structure, circuit board assembly and electronic equipment |
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| TW200503198A (en) * | 2003-07-15 | 2005-01-16 | Siliconware Precision Industries Co Ltd | Semiconductor package and method for fabricating the same |
| TW200634943A (en) * | 2005-03-29 | 2006-10-01 | Advanced Semiconductor Eng | Thermally enhanced chip package with high performance |
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| JP2001044310A (en) * | 1999-07-28 | 2001-02-16 | Mitsubishi Electric Corp | Semiconductor device and mounting method therefor |
| US7268428B2 (en) * | 2005-07-19 | 2007-09-11 | International Business Machines Corporation | Thermal paste containment for semiconductor modules |
| CN101221944A (en) * | 2007-01-09 | 2008-07-16 | 矽品精密工业股份有限公司 | Cooling type semiconductor packaging member |
| KR20120053332A (en) * | 2010-11-17 | 2012-05-25 | 삼성전자주식회사 | Semiconductor package and method of forming the same |
| JP6421050B2 (en) * | 2015-02-09 | 2018-11-07 | 株式会社ジェイデバイス | Semiconductor device |
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| TW200503198A (en) * | 2003-07-15 | 2005-01-16 | Siliconware Precision Industries Co Ltd | Semiconductor package and method for fabricating the same |
| TW200634943A (en) * | 2005-03-29 | 2006-10-01 | Advanced Semiconductor Eng | Thermally enhanced chip package with high performance |
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| CN106158785B (en) | 2019-09-13 |
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