CN101221944A - Cooling type semiconductor packaging member - Google Patents
Cooling type semiconductor packaging member Download PDFInfo
- Publication number
- CN101221944A CN101221944A CNA2007100013270A CN200710001327A CN101221944A CN 101221944 A CN101221944 A CN 101221944A CN A2007100013270 A CNA2007100013270 A CN A2007100013270A CN 200710001327 A CN200710001327 A CN 200710001327A CN 101221944 A CN101221944 A CN 101221944A
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- Prior art keywords
- substrate
- fin
- passive device
- electrically connected
- radiating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a radiation semiconductor package, comprising a substrate which is provided with a plurality of welding pads and grounding pads on the surface, semiconductor chips which are arranged on the substrate and electrically connected with the welding pads, passive components which are arranged on the welding pads of the substrate, zero resistance passive components or metal blocks which are arranged on the grounding pads of the substrate, and radiation fins which can be arranged on the zero resistance passive components or metal blocks, wherein, the radiation fins are electrically connected with the zero resistance passive components or metal blocks, and are electrically coupled with the grounding pads of the substrate to form a ground, thereby providing an EMI blackout effect, preventing the problems of increased cost of structure process and material consumption generated when the prior heat conductive structure provided with a supporting part is arranged on the substrate through the supporting part, and preventing the problem of arrangement of electronic components on the substrate restricted by the arrangement of the supporting part.
Description
Technical field
The present invention relates to a kind of semiconductor package part, refer to a kind of semiconductor package part that is integrated with radiator structure especially.
Background technology
Along with requirement to compactization of electronic product, ball grid array (BGA) semiconductor package part (Ball Grid Array Semiconductor Package) now becomes the main flow of encapsulating products gradually because of I/O connecting end (I/O Connection) that quantity sufficient can the be provided demand with the semiconductor chip that meets tool high density electronic component and electronic circuit.Yet, because this kind semiconductor package part provides the electronic circuit (Electronic Circuits) and electronic component (Electronic Components) of higher density, so the heat that is produced when operation is also higher, if in real time the heat of chip surface is not allayed fast, the heat that accumulates can have a strong impact on the electrical functionality and the product stability of semiconductor chip.
For solving the existing deficiency of ball grid array (BGA) semiconductor package on thermal diffusivity, there is the kenel of installing radiator structure in this BGA semiconductor package part to arise at the historic moment then.Relevant technology is case such as United States Patent (USP) 5,877,552,5,736,785,5,977,626,5,851,337,6,552,428,6,246,115,6,429,512,6,400,014,6,462,405 for example.
As shown in Figure 1, be United States Patent (USP) the 5th, 977, a kind of radiating semiconductor packer that is disclosed for No. 626, the radiator structure 13 of this radiating semiconductor packer 1 includes the par 130 that an end face exposes outside packing colloid 14; Frame supports a plurality of support portions 131 that this par 130 makes it to be positioned at semiconductor chip 11 tops; And extend for a plurality of a plurality of contact sites 132 that are used for gluing in the protuberance 137 of substrate 10 these 131 bottoms, support portion certainly; Wherein, this support portion 131 rings place that this par 130 is peripheral and outer gradually to extend this contact site 132 to constitute the channel 18 of holding a plurality of master/passive devices (as chip, bonding wire, capacitor etc.) downwards, and the heat energy that chip 11 operations are produced can be released by this radiator structure 13 and be dissipated in the atmosphere.
But, along with chip aggregationization and chip size packages (Chip ScalePackage, CSP) high development of kenel, size of substrate is required gradually near chip size (Near chip size), if double and substrate size reduces and bonding wire laying closeness increases dual consideration, certainly will must in limited substrate area, vacate more spaces the element integration is provided.Right in cooperating the formation of aforementioned radiator structure 13 the above protuberance 137, this contact site 132 often must keep certain area in order to these protuberance 137 punching out, and these radiator structure 13 contact sites 132 occupy substrate than large space, not only influence the base plate line configuration, the layout of passive device also enjoys restriction simultaneously.
In addition, because the substrate peripheral region is occupied by this contact site 132, be only can be placed in the channel 18 of this support portion 131 and par 130 formations with all active elements in the packaging part, therefore this contact site 132 is if can not reduce the substrate area that it takies, it will be more inadequate relatively providing the space of component positioning on the substrate, satisfy this kind radiator structure 13 real encapsulation kenels that can't be suitable for high aggregationization.
See also shown in Fig. 2 A and Fig. 2 B, in view of foregoing problems, TaiWan, China letters patent number 255047 a kind of radiating semiconductor packer of exposure and method for makings thereof, be semiconductor chip 21 and passive device 29 to be connect put and be electrically connected on the substrate 200, and the radiator structure 22 that will have fin 221 and support portion 222, connect with its support portion 222 and to place on this substrate 200, use that this semiconductor chip 21 is placed in this fin 221 belows, wherein this support portion 222 connects and places the default planar dimension P outer (shown in Fig. 2 A) that is positioned at this semiconductor package part on this substrate 200; Then connect the packing colloid 23 that forms this semiconductor chip 21 of coating and radiator structure 22 on the substrate 200 that is equipped with semiconductor chip 21 and radiator structure 22 in this, and the projection plane size M of this packing colloid 23 is greater than the default planar dimension P of this semiconductor package part, carry out cutting operation along the predetermined plane size P position of this semiconductor package part afterwards, use the part (shown in Fig. 2 B) that surpasses the default planar dimension of this packaging part in the support portion that removes this packing colloid, radiator structure and the substrate.
Thereby connect with its support portion by this radiator structure and to place outside the default planar dimension that is positioned at semiconductor package part on this substrate, can be for meeting the configuration district of electronic components such as putting and electrically connect semiconductor chip and passive device to avoid taking substrate, and then can provide the enough substrates of those electronic components to connect to put the space.
But in the aforesaid radiating semiconductor packer, because of the support zone of its radiator structure outside the default planar dimension of this semiconductor package part, that is in this support portion behind the cutting operation not in semiconductor package part, therefore this radiator structure is connect to put and be electrically connected to the substrate access area and form a grounded circuit (ground), hide effect and can't provide at electromagnetic interference (EMI).
In addition, though U.S. Pat 5,877,552 announcements can utilize the support portion of radiator structure to connect and put and be electrically connected to the substrate access area, but, will produce the waste of aforesaid base plate space and the configuration of restriction passive device because of this support portion directly places in the halfbody encapsulation packaging part.That is this radiator structure still must be dependent on this support portion and can connect and place on this substrate, so will cause the waste of substrate expensive real estate.
Moreover, disclosed radiator structure must prepare in aforementioned each prior art the support portion, connects for radiator structure to place on the substrate, yet promptly has the support portion because of this radiator structure, to cause the feed consumption expense of its mould expense and radiator structure to improve, and then increase the processing procedure cost.
Therefore, how effectively to solve the heat dissipation problem of semiconductor package part, can provide semiconductor package part electromagnetic interference screening effect simultaneously, and avoid radiator structure to take substrate area and high cost of manufacture and feed consumption problem, the big problem that it need be faced for industry.
Summary of the invention
Prior art problems in view of the above, a purpose of the present invention provides a kind of radiating semiconductor packer, is avoided being integrated in the radiator structure restriction electronic component arrangements space in the semiconductor package part.
Another object of the present invention provides a kind of radiating semiconductor packer, thereby the electromagnetic interference screening effect can be provided.
Another purpose of the present invention provides a kind of radiating semiconductor packer, is avoided making expensive and many feed consumptions problem that radiator structure caused of apparatus support portion.
For reaching above-mentioned and other purpose, the present invention discloses a kind of radiating semiconductor packer, comprising: substrate, and this substrate surface is provided with a plurality of weld pads and ground mat; Semiconductor chip connects and places on this substrate and be electrically connected to this weld pad; Passive device connects and puts and be electrically connected to this substrate weld pad; The passive device of zero resistance connects and puts and be electrically connected to this substrate ground mat; And fin, connect and place on this passive device, and be electrically connected to the passive device of this zero resistance.
This radiating semiconductor packer includes the packing colloid of the passive device that coats this fin, semiconductor chip, passive device and zero resistance again, and makes this heat sink top surface expose outside this packing colloid; This fin core is formed with protuberance, and this protuberance end face exposes outside packing colloid, and all the other peripheral part then are coated in this packing colloid, follow to strengthen this fin and packing colloid.In addition this fin connects the passive device of putting and be electrically connected to this zero resistance with the conductivity adhesion layer, and connects with non-conductive adhesion layer and to place on this passive device.
The present invention discloses another radiating semiconductor packer preferred embodiment again, comprising: substrate, and this substrate surface is provided with a plurality of weld pads and ground mat; Semiconductor chip connects and places on this substrate and be electrically connected to this weld pad; Passive device connects and puts and be electrically connected to this substrate weld pad; Metal derby connects and puts and be electrically connected to this substrate ground mat; And fin, at interval conductivity adhesion layer and connect and put and be electrically connected on this metal derby.
In addition, among the present invention this fin again at interval heat-conducting glue and connecing place on the semiconductor chip, use the heat that is produced when strengthening the operation of loss semiconductor chip; Also or make this fin and semiconductor chip keep a segment distance, use and reduce semiconductor chip by the problem of crushing.
Therefore, radiating semiconductor packer of the present invention is mainly put and is electrically connected with semiconductor chip and the passive device except that connecing on substrate, on this substrate, ground mat is set in addition, and on this ground mat, connect passive device or the metal derby of putting and be electrically connected with zero resistance, be able to be electrically connected to the passive device or the metal derby of this zero resistance by a conductivity adhesion layer for fin, and then form a grounded circuit (ground) with this substrate ground mat electrical couplings, using provides electromagnetic interference (EMI) to hide effect; Moreover, fin of the present invention can connect the passive device that places this passive device, zero resistance or metal derby and frame supports on substrate, avoid the existing conductive structure that makes the apparatus support portion to connect when placing on the substrate by its support portion, radiator structure cost that is produced and feed consumption increase problem, and because of electronic component allocation problem on the setting restricting substrate of this support portion.
Description of drawings
Fig. 1 is a United States Patent (USP) the 5th, 977, the generalized section of the radiating semiconductor packer that is disclosed for No. 626;
Fig. 2 A and Fig. 2 B are the schematic diagram of TaiWan, China letters patent number 255047 disclosed a kind of radiating semiconductor packers and method for making thereof;
Fig. 3 A and Fig. 3 B are plane and the generalized section of radiating semiconductor packer first embodiment of the present invention;
Fig. 4 A to Fig. 4 C is the schematic diagram of radiating semiconductor packer second embodiment of the present invention;
Fig. 5 is the schematic diagram of radiating semiconductor packer the 3rd embodiment of the present invention; And
Fig. 6 is the schematic diagram of radiating semiconductor packer the 4th embodiment of the present invention.
Symbol description
1 semiconductor package part
10,20 substrates
11,21 semiconductor chips
13,23 radiator structures
130 pars
131 support portions
132,232 contact sites
137 protuberances
14 packing colloids
18 channel
200 substrates
21 semiconductor chips
22 radiator structures
221 fin
222 support portions
23 packing colloids
29 passive devices
The default planar dimension of P semiconductor package part
The projection plane size of M packing colloid
30 substrates
301 weld pads
302 ground mats
31 semiconductor chips
32 fin
320 protuberances
33 packing colloids
34 conductive projections
351 non-conductive adhesion layers
352 conductivity adhesion layers
37 heat-conducting glues
38 metal derbies
391 passive devices
The passive device of 392 zero resistances
Embodiment
Below be that those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed by particular specific embodiment explanation embodiments of the present invention.
First embodiment
See also Fig. 3 A and Fig. 3 B, be plane and the generalized section of radiating semiconductor packer first embodiment of the present invention.
As shown in the figure, this radiating semiconductor packer includes a substrate 30, and these substrate 30 surfaces are provided with a plurality of weld pads 301 and at least one ground mat 302; At least one semiconductor chip 31 connects and places on this substrate 30 and be electrically connected to this weld pad 301; A plurality of passive devices 391 connect and put and be electrically connected to this substrate weld pad 301; The passive device 392 of at least one zero resistance connects and puts and be electrically connected to substrate ground mat 302; And fin 32, connect and place on this passive device 391, and be electrically connected to the passive device 392 of zero resistance.
This substrate 30 for example is the spherical grid array type substrate, and is provided with a plurality of weld pads 301 and at least one ground mat 302 in these substrate 30 surfaces.
This semiconductor chip 31 can connect by a plurality of conductive projections 34 and put and be electrically connected to this substrate weld pad 301.This semiconductor chip also can be electrically connected to this substrate by the routing mode in addition.
Multiple connection is equipped with a plurality of passive devices 391 on this substrate 30 simultaneously, and this passive device 391 is resistance, electric capacity or inductance etc. for example, connects and puts and be electrically connected to substrate weld pad 301, uses lifting or improves the electrical quality of packaging part.
The passive device 392 of this zero resistance connects and puts and be electrically connected to substrate ground mat 302, so that the fin 32 ground connection effects of follow-up electric connection on it to be provided.
This passive device 391 can be disposed at substrate 30 nearly angle end or edges earlier, with supporting construction as follow-up fin 32, moreover on this substrate 30 the zone for this general passive device 391 of configuration do not form at least one ground mat 302, connect for the passive device 392 of at least one zero resistance and put and be electrically connected on this ground mat 302.
Among the present invention, behind abundant configuring semiconductor chip 31 and passive device 391 on this substrate 30, this fin 32 connects by a non-conductive adhesion layer 351 and places on this passive device 391, and cover this semiconductor chip 31, and unlikely restriction semiconductor chip 31 and passive device 391 configuring conditions; And these fin 32 multiple passive devices 392 that are electrically connected to this zero resistance by a conductivity adhesion layer 352, and then make this fin 32 and substrate ground mat 302 electrical couplings, to provide the semiconductor chip that is covered in these fin 32 belows 31 electrical interference shielding effects; In addition, this fin 32 also can effectively connect by the passive device 392 of this zero resistance and place on this substrate 30.
Described before combining, because this fin 32 only is positioned at the passive device 391 at this fin angle end or edge and frame supports on substrate 30 relatively by a plurality of, avoid the existing conductive structure that makes the apparatus support portion to connect when placing on the substrate by its support portion, the radiator structure cost that is produced and feed consumption increase problem, and limit the passive device allocation problem because of the setting of this support portion.
This radiating semiconductor packer includes the packing colloid 33 of the passive device that coats this fin 32, semiconductor chip 31, passive device 391 and zero resistance again in addition, and makes these fin 32 end faces expose outside this packing colloid 33; Wherein these fin 32 cores are formed with protuberance 320, and these protuberance 320 end faces expose outside packing colloid 33, and all the other peripheral part then are coated in this packing colloid 33, to strengthen this fin 32 and packing colloid 33 then.
Moreover, radiating semiconductor packer of the present invention can connect on the ground mat 302 of substrate 30 again and put and electrically connect metal derby (not shown), use with the passive device 392 that replaces zero resistance, be electrically connected to this metal derby for fin by the conductivity adhesion layer, so with this substrate ground mat electrical couplings.
Second embodiment
See also Fig. 4 A to Fig. 4 C, be the schematic diagram of radiating semiconductor packer second embodiment of the present invention, wherein this Fig. 4 B generalized section that is the radiating semiconductor packer of corresponding diagram 4A.
Radiating semiconductor packer second embodiment of the present invention is disclosed, be corresponding to general passive device can't be as the situation of fin supporting construction the time, or for avoiding it undermined, can be in end place, substrate 30 nearly angle (shown in Fig. 4 A and Fig. 4 B) or proximal edge place (shown in Fig. 4 C) form a plurality of ground mats 302, and on this ground mat 302, connect passive device or the metal derby 38 of putting and electrically connect at least three zero resistances, all the other zones are provided with weld pad 301 and put and electrically connect semiconductor chip 31 and general passive device 391 for connecing on substrate 30 simultaneously, so can connect on the passive device or metal derby 38 of putting and be electrically connected to this zero resistance by conductivity adhesion layer 352 for fin 32, except that the support that fin 32 is provided, and must form grounded circuit, and then provide semiconductor chip electromagnetic interference screening effect with substrate ground mat 302 electrical couplings.
The 3rd embodiment
See also Fig. 5, schematic diagram for radiating semiconductor packer the 3rd embodiment of the present invention, the radiating semiconductor packer and the previous embodiment of present embodiment are roughly the same, main difference is that fin 32 can connect by heat-conducting glue 37 again simultaneously and places on the semiconductor chip 31, uses to strengthen the heat that loss semiconductor chip 31 is produced when operation.
The 4th embodiment
See also Fig. 6, schematic diagram for radiating semiconductor packer the 4th embodiment of the present invention, the radiating semiconductor packer and the previous embodiment of present embodiment are roughly the same, main difference is that fin 32 and this connect the semiconductor chip 31 that places on the substrate 30 and keep a segment distance, uses and reduces semiconductor chip 31 by the problem of crushing.
Therefore, radiating semiconductor packer of the present invention is mainly put and is electrically connected with semiconductor chip and the passive device except that connecing on substrate, on this substrate, ground mat is set in addition, and on this ground mat, connect passive device or the metal derby of putting and be electrically connected with zero resistance, be able to be electrically connected to the passive device or the metal derby of this zero resistance by a conductivity adhesion layer for fin, and then form a grounded circuit (ground) with this substrate ground mat electrical couplings, using provides electromagnetic interference (EMI) to hide effect; Moreover, fin of the present invention can connect the passive device that places this passive device, zero resistance or metal derby and frame supports on substrate, avoid the existing conductive structure that makes the apparatus support portion to connect when placing on the substrate by its support portion, radiator structure cost that is produced and feed consumption increase problem, and because of electronic component allocation problem on the setting restricting substrate of this support portion.
The above embodiments only are illustrative principle of the present invention and effect thereof, but not are used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, the scope of the present invention should be foundation with the scope of claims of the present invention.
Claims (22)
1. radiating semiconductor packer comprises:
Substrate, this substrate surface is provided with weld pad and ground mat;
Semiconductor chip connects and places on this substrate and be electrically connected to this weld pad;
Passive device connects and puts and be electrically connected to this substrate weld pad;
The passive device of zero resistance connects and puts and be electrically connected to this substrate ground mat; And
Fin connects the passive device of putting and be electrically connected to this zero resistance.
2. radiating semiconductor packer according to claim 1, wherein, this fin connects the passive device that places this zero resistance by the conductivity adhesion layer, and covers this semiconductor chip.
3. radiating semiconductor packer according to claim 1, wherein, the passive device of this zero resistance selects to be disposed at this fin angle end and edge.
4. radiating semiconductor packer according to claim 3, wherein, the passive device of this zero resistance has at least three.
5. radiating semiconductor packer according to claim 1, wherein, this fin connects by non-conductive adhesion layer and places on this passive device, and covers this semiconductor chip.
6. radiating semiconductor packer according to claim 1, wherein, this passive device is selected to be disposed at substrate nearly angle end and edge, and on this substrate the zone for this passive device of configuration form ground mat, connect for the passive device of zero resistance and put and be electrically connected on this ground mat.
7. radiating semiconductor packer according to claim 1, wherein, this semiconductor chip is electrically connected to this substrate in a wherein mode of covering crystalline substance and routing.
8. radiating semiconductor packer according to claim 1, include the packing colloid that is formed on this substrate again, in order to coating the passive device of this fin, semiconductor chip, passive device and zero resistance, and make this heat sink top surface expose outside this packing colloid.
9. radiating semiconductor packer according to claim 8, wherein, this fin core is formed with protuberance, and this protuberance end face exposes outside packing colloid, all the other peripheral part then are coated in this packing colloid, follow to strengthen this fin and packing colloid.
10. radiating semiconductor packer according to claim 1, wherein, this fin connects by heat-conducting glue and places on the semiconductor chip.
11. radiating semiconductor packer according to claim 1, wherein, this fin and semiconductor chip keep a segment distance.
12. a radiating semiconductor packer comprises:
Substrate, this substrate surface is provided with a plurality of weld pads and ground mat;
Semiconductor chip connects and places on this substrate and be electrically connected to this weld pad;
Passive device connects and puts and be electrically connected to this substrate weld pad;
Metal derby connects and puts and be electrically connected to this substrate ground mat; And
Fin connects and puts and be electrically connected on this metal derby.
13. radiating semiconductor packer according to claim 12, wherein, this fin connects by the conductivity adhesion layer and puts and be electrically connected to this metal derby, and covers this semiconductor chip.
14. radiating semiconductor packer according to claim 12, wherein, this metal derby selects to be disposed at the edge and the angle end place of this fin.
15. radiating semiconductor packer according to claim 14, wherein, this metal derby has at least three.
16. radiating semiconductor packer according to claim 12, wherein, this fin connects by non-conductive adhesion layer and places on this passive device, and covers this semiconductor chip.
17. radiating semiconductor packer according to claim 12, wherein, this passive device selects to be disposed at the edge and the angle end place of this fin.
18. radiating semiconductor packer according to claim 12, wherein, this semiconductor chip is electrically connected to this substrate in a wherein mode of covering crystalline substance and routing.
19. radiating semiconductor packer according to claim 12 includes the packing colloid that is formed on this substrate again, in order to coating this fin, semiconductor chip, passive device and metal derby, and makes this heat sink top surface expose outside this packing colloid.
20. radiating semiconductor packer according to claim 19, wherein, this fin core is formed with protuberance, and this protuberance end face exposes outside packing colloid, all the other peripheral part then are coated in this packing colloid, follow to strengthen this fin and packing colloid.
21. radiating semiconductor packer according to claim 12, wherein, this fin connects by heat-conducting glue and places on the semiconductor chip.
22. radiating semiconductor packer according to claim 12, wherein, this fin and semiconductor chip keep a segment distance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100013270A CN101221944A (en) | 2007-01-09 | 2007-01-09 | Cooling type semiconductor packaging member |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100013270A CN101221944A (en) | 2007-01-09 | 2007-01-09 | Cooling type semiconductor packaging member |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101221944A true CN101221944A (en) | 2008-07-16 |
Family
ID=39631667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100013270A Pending CN101221944A (en) | 2007-01-09 | 2007-01-09 | Cooling type semiconductor packaging member |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101221944A (en) |
Cited By (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044504A (en) * | 2010-01-28 | 2011-05-04 | 江苏长电科技股份有限公司 | Radiating block packaging structure with inside pin embedded in chip upside-down mounting band |
| CN102044507A (en) * | 2010-01-30 | 2011-05-04 | 江苏长电科技股份有限公司 | Printed circuit board chip flip external radiator packaging structure |
| CN102044509A (en) * | 2010-01-30 | 2011-05-04 | 江苏长电科技股份有限公司 | Package structure with embedded inner pins, chip, inverted locking hole, radiating block, convex column and external radiator |
| CN102044505A (en) * | 2010-01-28 | 2011-05-04 | 江苏长电科技股份有限公司 | Packaging structure with exposed inner pin, inverted chip and cooling block |
| CN102044506A (en) * | 2010-01-30 | 2011-05-04 | 江苏长电科技股份有限公司 | Package structure with embedded inner pins, chip, inverted radiating block and external radiator |
| CN102054801A (en) * | 2010-01-30 | 2011-05-11 | 江苏长电科技股份有限公司 | Capsulation structure with inner pin embedded in flip-chip locking hole and radiator externally connected on radiating block |
| CN102054799A (en) * | 2010-01-30 | 2011-05-11 | 江苏长电科技股份有限公司 | Encapsulating structure with exposed inner pin, inverted chip and radiating block provided with lock hole and externally connected with radiator through projecting post |
| CN102054805A (en) * | 2010-01-30 | 2011-05-11 | 江苏长电科技股份有限公司 | Packaging structure of flip resin circuit board chip with circumscribed radiator |
| CN102054800A (en) * | 2010-01-30 | 2011-05-11 | 江苏长电科技股份有限公司 | Encapsulating structure with inner pin exposed, chip fipped and heat radiating block externally connected for heat radiator |
| CN102054797A (en) * | 2010-01-30 | 2011-05-11 | 江苏长电科技股份有限公司 | Packaging structure of printed circuit board, chip, flip lock hole radiating block and external radiator |
| CN102074522A (en) * | 2010-01-30 | 2011-05-25 | 江苏长电科技股份有限公司 | Package structure with printed circuit boards (PCBs), chip, inverted locking hole, radiating block, convex column and external radiator |
| CN102074519A (en) * | 2010-01-27 | 2011-05-25 | 江苏长电科技股份有限公司 | Flip chip package structure with radiating block on printed circuit board (PCB) |
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2007
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| CN106158785A (en) * | 2015-03-20 | 2016-11-23 | 矽品精密工业股份有限公司 | Heat dissipation type packaging structure and heat dissipation piece thereof |
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| CN106531701A (en) * | 2016-12-07 | 2017-03-22 | 江苏长电科技股份有限公司 | Grounding packaging structure of heat dissipation cover and technological method for grounding packaging structure |
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