TW200503198A - Semiconductor package and method for fabricating the same - Google Patents

Semiconductor package and method for fabricating the same

Info

Publication number
TW200503198A
TW200503198A TW092119216A TW92119216A TW200503198A TW 200503198 A TW200503198 A TW 200503198A TW 092119216 A TW092119216 A TW 092119216A TW 92119216 A TW92119216 A TW 92119216A TW 200503198 A TW200503198 A TW 200503198A
Authority
TW
Taiwan
Prior art keywords
chip
stiffeners
fabricating
semiconductor package
same
Prior art date
Application number
TW092119216A
Other languages
Chinese (zh)
Other versions
TWI236106B (en
Inventor
Ying-Ren Lin
Ho-Yi Tsai
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW092119216A priority Critical patent/TWI236106B/en
Publication of TW200503198A publication Critical patent/TW200503198A/en
Application granted granted Critical
Publication of TWI236106B publication Critical patent/TWI236106B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor package and a method for fabricating the same are proposed, in which at feast a chip is mounted on and electrically connected to a chip carrier, and a plurality of elastic stiffeners are respectively formed on a surface of the chip. In addition, an adhesive surrounding the stiffeners is coated on the surface of the chip, and the height of the stiffeners is higher than the diameter of fillers in the adhesive. Then, a thermal conductive member is attached to the surface of the chip by means of the adhesive and stiffeners and an encapsulant is formed to encapsulate the chip, the thermal conductive member, and a part of the chip carrier. As a result, the stiffeners can prevent the surface of the chip from being damaged by thermal stresses from the thermal conductive member.
TW092119216A 2003-07-15 2003-07-15 Semiconductor package and method for fabricating the same TWI236106B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW092119216A TWI236106B (en) 2003-07-15 2003-07-15 Semiconductor package and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092119216A TWI236106B (en) 2003-07-15 2003-07-15 Semiconductor package and method for fabricating the same

Publications (2)

Publication Number Publication Date
TW200503198A true TW200503198A (en) 2005-01-16
TWI236106B TWI236106B (en) 2005-07-11

Family

ID=36648959

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092119216A TWI236106B (en) 2003-07-15 2003-07-15 Semiconductor package and method for fabricating the same

Country Status (1)

Country Link
TW (1) TWI236106B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI555147B (en) * 2015-03-20 2016-10-21 矽品精密工業股份有限公司 Heat-dissipation package structure and its heat sink

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI555147B (en) * 2015-03-20 2016-10-21 矽品精密工業股份有限公司 Heat-dissipation package structure and its heat sink

Also Published As

Publication number Publication date
TWI236106B (en) 2005-07-11

Similar Documents

Publication Publication Date Title
TW200705519A (en) Semiconductor package without chip carrier and fabrication method thereof
TW200620496A (en) Semiconductor package free of carrier and fabrication method thereof
TW200721424A (en) Semiconductor device
TW200620511A (en) Semiconductor device and method of assembling semiconductor device
MY159521A (en) Resin-sealed light emitting device and its manufacturing method
TW200504995A (en) Stacked chip semiconductor device and method for manufacturing the same
TWI268628B (en) Package structure having a stacking platform
TW200711081A (en) A method of manufacturing a semiconductor packages and packages made
WO2005124858A3 (en) Package and method for packaging an integrated circuit die
TW200731476A (en) Plastic packaged device with die interface layer
TW200725859A (en) Structure and method for packaging a chip
TW200707676A (en) Thin IC package for improving heat dissipation from chip backside
TW200737437A (en) Chip package and package process thereof
WO2011049959A3 (en) Methods and devices for manufacturing cantilever leads in a semiconductor package
TW200725852A (en) Build-up package and method of an optoelectronic chip
TWI256091B (en) A semiconductor package having stacked chip package and a method
TW200729429A (en) Semiconductor package structure and fabrication method thereof
TW200514216A (en) Quad flat no-lead package structure and manufacturing method thereof
TW200504963A (en) Multi-chip semiconductor package and manufacturing method thereof
TW200711151A (en) Multi-chip package structure
TW200625562A (en) Semiconductor package and fabrication method thereof
TWI265617B (en) Lead-frame-based semiconductor package with lead frame and lead frame thereof
TW200618222A (en) Heat dissipating package structure and fabrication method thereof
TWI263286B (en) Wire bonding method and semiconductor package using the method
TW200504900A (en) A semiconductor device and the manufacturing method thereof

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent