TW201839936A - Packaging substrate and method for fabricating the same - Google Patents

Abstract

A packaging substrate includes an electronic component and a conductive pillar disposed on a circuit structure, and an insulation layer encapsulating the electronic component and the conductive pillar, with an end surface of the conductive pillar exposed from the insulation layer, allowing an electronic device to be stacked on the end surface of the conductive pillar of the packaging substrate. Therefore, the stacking height of the overall structure is reduced, and the fabrication process is simplified. A method for fabricating the packaging substrate is also provided.

Description

 Package substrate and its preparation method  

The invention relates to a package structure, in particular to a package substrate and a preparation method thereof.

With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, and in order to improve electrical functions and save packaging space, different stereo packaging technologies have been developed, for example, package stacking (Package on Technology, such as package (PoP), to meet the large increase in the number of inputs/outputs on various wafers, and to integrate the integrated circuits of different functions into a single package structure. This package can achieve the heterogeneous integration of system package (SiP). The electronic components of different functions, such as memory, central processing unit, graphics processor, image application processor, etc., can be integrated into the system by stacking design, and are suitable for various thin and light electronic products.

1 is a schematic cross-sectional view of a conventional semiconductor package 1 for PoP. As shown in FIG. 1, the semiconductor package 1 is provided with a plurality of semiconductor elements 11, 12 on a package substrate 10 having a wiring layer (not shown), and the electronic device 15 is stacked on the package by a plurality of conductive pillars 13. On the substrate 10, an encapsulant 14 is formed between the package substrate 10 and the electronic device 15 to cover the semiconductor elements 11, 12 and the conductive pillars 13.

However, in the conventional semiconductor package 1 , the semiconductor elements 11 , 12 are disposed above the package substrate 10 , so when stacking the electronic device 15 , the semiconductor elements 11 , 12 and the conductive pillars 13 are considered. The height of the semiconductor package 1 increases the overall package height of the semiconductor package 1 , which makes it difficult to reduce the size of the semiconductor package 1 and the process is complicated. Moreover, if the heights of the conductive pillars 13 are inconsistent, the installation of the electronic device 15 will be difficult. Degree, or even affect the yield of the product.

Therefore, how to overcome the shortcomings of the prior art is a technical problem that is currently being solved by all walks of life.

In view of the above-mentioned shortcomings of the prior art, the present invention provides a package substrate comprising: a line structure; an electronic component disposed on the circuit structure; a plurality of conductive pillars disposed on the circuit structure; and formed on the circuit structure The electronic component and the insulating layer of the conductive pillar are covered, and the end surface of each of the conductive pillars is exposed to the upper surface of the insulating layer.

The invention provides a method for manufacturing a package substrate, comprising: disposing an electronic component and a plurality of conductive pillars on a line structure; and forming an insulating layer on the circuit structure to cover the electronic component and the conductive pillar, and The end face of the conductive post is exposed on the upper surface of the insulating layer.

In the above package substrate and method of manufacturing the same, the end surface of the conductive pillar protrudes from the upper surface of the insulating layer for attaching the electronic device to the end surface of the conductive pillar.

In the above package substrate and the method of manufacturing the same, the end surface of the conductive pillar may be flush or lower than the upper surface of the insulating layer for forming a conductive component on the end surface of the conductive pillar for receiving the electronic device.

In the above package substrate and its manufacturing method, the circuit structure is a large layout type, so that the wiring structure is molded by using a large layout pattern to form the insulating layer.

It can be seen that the package substrate of the present invention and the manufacturing method thereof are mainly designed by embedding the electronic component and the conductive pillar in the package substrate, so as to greatly reduce the height of the exposed component above the package substrate, so In the prior art, when the electronic device is stacked, the overall package height of the electronic package can be reduced to reduce the size of the electronic package.

Furthermore, since the electronic component is embedded in the package substrate, the conductive path between the electronic component and the wiring structure can be shortened, thereby achieving the purpose of electrical improvement.

Moreover, embedding the electronic component and the conductive pillar in the package substrate can simplify the subsequent packaging process (such as omitting the fabrication of the conventional package colloid) to reduce the manufacturing cost.

1‧‧‧Semiconductor package

10,2a‧‧‧Package substrate

11,12‧‧‧Semiconductor components

13,23,43,53‧‧‧conductive pillar

14‧‧‧Package colloid

15,25‧‧‧Electronic devices

2,4,5‧‧‧Electronic package

20‧‧‧Line structure

21,22‧‧‧Electronic components

21a‧‧‧Action surface

21b‧‧‧Non-active surface

210‧‧‧Electrical bumps

22a, 22b‧‧‧electrode pads

220‧‧‧Electrical conductor

23a, 43a, 53a‧‧‧ end face

24,24’‧‧‧Insulation

24a‧‧‧ first surface

24b, 24b’‧‧‧ second surface

240‧‧‧ openings

30,40‧‧‧Conductive components

31‧‧‧ boards

32‧‧‧ glass plate

1 is a schematic cross-sectional view of a conventional semiconductor package; and 2A to 2C are schematic cross-sectional views showing a method of fabricating an embodiment of the package substrate of the present invention; and FIG. 2D is one of the package substrates to which the present invention is applied. 3A and 3B are cross-sectional views showing still another embodiment of a package substrate to which the present invention is applied; and FIGS. 4A and 4B are cross-sectional views showing still another embodiment of a package substrate to which the present invention is applied; And Fig. 5 is a schematic cross-sectional view showing another embodiment of a package substrate to which the present invention is applied.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2A to 2C are schematic cross-sectional views showing the manufacturing method of the first embodiment of the package substrate of the present invention.

As shown in FIG. 2A, a plurality of electronic components 21, 22 and a plurality of conductive pillars 23 are formed on a line structure 20.

In this embodiment, the circuit structure 20 is a large layout (PNL) type having a dielectric layer (not shown) and a circuit layer (not shown) combined with the dielectric layer. The circuit layer is electrically connected to the electronic components 21, 22 and the conductive pillars 23, and the conductive pillars 23 are made of a metal material such as copper or a solder material.

Furthermore, the electronic components 21, 22 are active components, passive components or a combination thereof, and the active components are, for example, semiconductor wafers, and the passive components are, for example, resistors, capacitors, and inductors. In one embodiment, the electronic component 21 is a semiconductor chip, such as a microcontroller (Microcontroller Unit, MCU for short), an application specific integrated circuit (ASIC), and a dynamic random access memory (Dynamic). a random access memory (DRAM) or a power management IC (PMIC) having a working surface 21a and a non-active surface 21b. The active surface 21a has a plurality of electrode pads, and the electronic component 21 is covered. The crystal mode (forming the conductive bumps 210 on the electrode pads) is electrically connected to the circuit layer of the circuit structure 20; in addition, the electronic component 22 is a passive component having electrode pads 22a, 22b on the left and right sides thereof. The electrical conductor 220 is formed to electrically connect the wiring layer of the wiring structure 20.

As shown in FIG. 2B, a large layout (PNL) pattern is used for molding to form an insulating layer 24' on the wiring structure 20, so that the insulating layer 24' covers the electrons. The components 21, 22 and the conductive pillars 23.

In the present embodiment, the material forming the insulating layer 24' is a dielectric material, for example, epoxy is a base.

Furthermore, the insulating layer 24' has opposing first and second surfaces 24a, 24b' and is bonded to the wiring structure 20 by the first surface 24a.

As shown in FIG. 2C, part of the material of the second surface 24b' of the insulating layer 24' is removed, so that the end surface 23a of the conductive pillar 23 protrudes from the second surface 24b of the insulating layer 24 as an external contact. The package substrate 2a of the present invention is obtained.

In addition, as shown in FIG. 2D, an electronic device 25 can be disposed in the package substrate 2a to expose the end surface 23a of the conductive pillar 23 of the insulating layer 24 to form an electronic package 2, wherein the electronic component Device 25 is such as a package structure or other electronic structure such as a wafer.

Furthermore, as shown in FIG. 3A, on the other side of the line structure 20 opposite to the insulating layer 24 (ie, the lower side of the line structure 20), a plurality of conductive elements 30 such as solder balls can be combined as a circuit board. 31 external device. Alternatively, as shown in FIG. 3B, an external device such as a glass plate 32 may be bonded to the other side of the wiring structure 20 with respect to the insulating layer 24.

The package substrate 2a of the present invention is embedded in the package substrate 2a by the electronic components 21, 22 and the conductive pillars 23, so as to greatly reduce and effectively control the exposed components above the package substrate 2a (only the conductive pillars are exposed) The height of the end face 23a) of the 23 is such that when the electronic device 25 is stacked, the overall package height of the electronic package 2 can be reduced to facilitate the reduction of the size of the electronic package 2 while simplifying the process.

Furthermore, since the electronic components 21, 22 are embedded in the package substrate 2a, the conductive path between the electronic components 21, 22 and the line structure 20 can be shortened, thereby achieving the purpose of electrical improvement.

Moreover, the electronic components 21, 22 and the conductive pillars 23 are embedded in the package substrate 2a, which simplifies the subsequent packaging process (such as omitting the fabrication of the conventional encapsulant 14) to reduce the manufacturing cost.

In addition, the conductive pillar 23 is embedded in the insulating layer 24, so that the periphery of each of the conductive pillars 23 is separated by an insulating material, and the exposed size of the end portion of the conductive pillar 23 can be effectively controlled, so the number of the conductive pillars 23 is When the spacing between the conductive pillars 23 is increased, bridging between the conductive pillars 23 can be avoided.

4A to 4B are cross-sectional views showing another embodiment of the package substrate and the electronic package of the same according to the present invention. The difference between this embodiment and the first embodiment lies in the height of the end face of the conductive post, and the other structures are substantially the same. Therefore, only the differences will be described in detail below, and the same points will not be described again, and thus will be described.

As shown in FIGS. 4A and 4B, after the process shown in FIG. 2B, part of the material of the second surface 24b' of the insulating layer 24' and the conductive pillar 23 are removed by a leveling process such as a grinding method. Part of the material is such that the end surface 43a of the conductive post 43 is flush with the second surface 24b of the insulating layer 24.

In this embodiment, the package substrate 2a can be separated from the end surface 43a of the conductive post 43 by a conductive element 40 such as a solder ball to connect the electronic device 25 to form an electronic package 4.

Furthermore, the manner in which the end surface of the conductive post is flush with the second surface of the insulating layer is not limited to the above, and the second surface 24b may be directly formed by mold forming after the process shown in FIG. 2A. The insulating layer 24 of the end face 23a of the conductive post 23 is flattened.

Figure 5 is a cross-sectional view showing another embodiment of the package substrate of the present invention and an electronic package for use thereof. The difference between this embodiment and the foregoing embodiment lies in the height of the end face of the conductive post, and the other structures are substantially the same. Therefore, only the differences will be described in detail below, and the same points will not be described again, and thus will be described.

As shown in FIG. 5, in the process shown in FIG. 2C, part of the material of the second surface 24b' of the insulating layer 24' is removed in an open manner to the second surface 24b of the insulating layer 24. An opening 240 is formed on the end surface 53a of the conductive post 53 so that the end surface 53a of the conductive post 53 is lower than the second surface 24b of the insulating layer 24.

In this embodiment, the package substrate 2a is formed in the openings 240 to form a plurality of conductive elements 40 on the end faces 53a of the conductive posts 53 to connect the electronic device 25 to form an electronic package 5. .

Furthermore, the manner in which the end surface of the conductive post is lower than the second surface of the insulating layer is not limited to the above, and the material of the conductive pillar 43 may be etched and removed in a flush state as shown in FIG. 4A. The end face 53a of the conductive post 53 is lower than the second surface 24b of the insulating layer 24.

The present invention also provides a package substrate 2a, comprising: a line structure 20, a plurality of electronic components 21, 22 and a plurality of conductive pillars 23, 43, 53 disposed on the circuit structure 20, and covering the electronic components 21, 22 An insulating layer 24 with conductive pillars 23, 43, 53.

The electronic components 21, 22 are disposed on the circuit structure 20 and embedded in the insulating layer 24 and electrically connected to the circuit structure 20.

The conductive pillars 23, 43, 53 are disposed on the circuit structure 20 and embedded in the insulating layer 24 and electrically connected to the circuit structure 20, and the end faces 23a of the conductive pillars 23, 43, , 43a, 53a are exposed to the insulating layer 24.

In an embodiment, the end surface 23a of the conductive post 23 protrudes from the insulating layer 24 to connect the electronic device 25 to the end surface 23a of the conductive post 23.

In one embodiment, the end faces 43a, 53a of the conductive posts 43, 53 are flush or lower than the second surface 24b of the insulating layer 24 to space the conductive elements 40 on the end faces 43a, 53a of the conductive posts 43, 53. The electronic device 25 is connected.

In one embodiment, the line structure 20 is of a large layout type.

In one embodiment, the package substrate 2a can be combined with an external device (such as the circuit board 31 or the glass plate 32) on the other side of the circuit structure 20 opposite the insulating layer 24.

In summary, the package substrate of the present invention and the manufacturing method thereof are designed by embedding electronic components and conductive pillars in the package substrate, thereby reducing the size and electrical conductivity of the electronic package, and simplifying the package. The process reduces the manufacturing cost, and when the number of conductive pillars is increased and applied to fine pitch products, bridging between the conductive pillars can be avoided.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

Claims (10)

 A package substrate includes: a line structure; an electronic component disposed on the circuit structure; a plurality of conductive pillars disposed on the circuit structure; and an insulation formed on the circuit structure and covering the electronic component and the conductive pillar And exposing the upper surface of the insulating layer to the outer surface of each of the conductive pillars.    The package substrate of claim 1, wherein an end surface of the conductive pillar protrudes from an upper surface of the insulating layer.    The package substrate of claim 1, wherein the end surface of the conductive post is flush or lower than the upper surface of the insulating layer.    The package substrate according to claim 1, wherein the circuit structure is a large layout type.    The package substrate according to claim 1, further comprising a conductive component disposed on an end surface of the conductive pillar for receiving the electronic device.    A method for manufacturing a package substrate, comprising: disposing an electronic component and a plurality of conductive pillars on a line structure; and forming an insulating layer on the circuit structure to cover the electronic component and the conductive pillar, and having an end face of each of the conductive pillars Exposed to the upper surface of the insulating layer.    The method of manufacturing a package substrate according to claim 6, wherein an end surface of the conductive pillar protrudes from an upper surface of the insulating layer.    The method for manufacturing a package substrate according to claim 6, wherein the end surface of the conductive pillar is flush or lower than the upper surface of the insulating layer.    The method of manufacturing a package substrate according to claim 6, wherein the circuit structure is molded by using a large layout pattern to form the insulation layer.    The method for manufacturing a package substrate according to claim 6, further comprising forming a conductive member on the conductive post to connect the electronic device.