CN106298699A - Encapsulating structure and method for packing - Google Patents
Encapsulating structure and method for packing Download PDFInfo
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- CN106298699A CN106298699A CN201610850385.XA CN201610850385A CN106298699A CN 106298699 A CN106298699 A CN 106298699A CN 201610850385 A CN201610850385 A CN 201610850385A CN 106298699 A CN106298699 A CN 106298699A
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- functional
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- chip
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- encapsulating structure
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- 238000012856 packing Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 205
- 239000010410 layer Substances 0.000 claims description 152
- 238000004806 packaging method and process Methods 0.000 claims description 52
- 239000004033 plastic Substances 0.000 claims description 48
- 229910052751 metal Inorganic materials 0.000 claims description 34
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- 238000001259 photo etching Methods 0.000 claims description 3
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- 230000007423 decrease Effects 0.000 abstract 1
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- 239000000463 material Substances 0.000 description 22
- 230000000694 effects Effects 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
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- 230000015572 biosynthetic process Effects 0.000 description 4
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- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- -1 Sillim Chemical compound 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
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- 230000010354 integration Effects 0.000 description 2
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 2
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
A kind of encapsulating structure and method for packing, encapsulating structure includes: substrate, and described substrate has line layer in having relative first and second, and described substrate；It is positioned at the first functional chip on described substrate first, described first functional chip has the first relative functional surfaces and first back side, there is on described first functional surfaces pad, described first back side and described first fixed engagement, and described pad is electrically connected with described line layer by wire；Upside-down mounting is arranged on the second functional chip on described substrate second, described second functional chip has the second relative functional surfaces and second back side, described second functional surfaces with described second relative, and the line layer that described second functional surfaces exposes with described substrate the second face electrically connects；Being positioned at the solder-bump on described substrate second, the line layer that described solder-bump exposes with described substrate the second face electrically connects.Present invention decreases the size of encapsulating structure, improve the integrated level of encapsulating structure.
Description
Technical field
The present invention relates to encapsulation technology field, particularly to a kind of encapsulating structure and method for packing.
Background technology
Along with the continuous enhancing of electronic product function, chip is sent out towards high integration, high pixelation and miniaturization trend
Exhibition.In order to tackle this challenge, it is proposed that fan-out-type (fan out) Wafer level packaging.
Fan-out-type Wafer level packaging mainly comprises the steps that and is first cut by full wafer bare silicon wafer, forms single
Discrete chip；Substrate is provided, by the individual chips rearrangement on substrate after cutting, forms inter-chip pitch the newest
Wafer；Then use Wafer level packaging (WLP, Wafer Level Package), the wafer of rearrangement is sealed
After dress test, cut into the welded ball array chip bigger than original chip area.Fan-out-type Wafer level packaging is conducive to encapsulation
The chip that volume is little, multi-electrode, electrode spacing are narrow；Additionally, fan-out-type Wafer level packaging can also encapsulate in principle simultaneously
The chip that dissimilar nitrogen equivalently-sized even soldered ball quantity is closer to.
Compared with crystal wafer chip dimension encapsulation, fan-out-type Wafer level packaging preferably solves the low problem of reliability
And the problem mated with successive process PCB, wherein, the problem that described reliability is low is likely due to that electrode closeness is excessive to be made
Become.
But, the size of the encapsulating structure of prior art is relatively big, and integrated level has much room for improvement.
Summary of the invention
The problem that the present invention solves is to provide a kind of encapsulating structure and method for packing, reduces the size of encapsulating structure, carries
High integration.
For solving the problems referred to above, the present invention provides a kind of encapsulating structure, and including substrate, described substrate has relative the
In one side and second, and described substrate, there is line layer；It is positioned at the first functional chip on described substrate first, described
One functional chip has the first relative functional surfaces and first back side, and described first functional surfaces has pad, described first back of the body
Face and described first fixed engagement, and described pad electrically connected with described line layer by wire；Upside-down mounting is arranged on described base
The second functional chip on plate second, described second functional chip has the second relative functional surfaces and second back side, described
Second functional surfaces with described second relative, and the line layer that described second functional surfaces and described substrate the second face expose is electrically connected
Connect；It is positioned at the solder-bump on described substrate second, the line layer that described solder-bump exposes with described substrate the second face
Electrical connection.
Optionally, described first functional chip is image sensing chip；On described first functional surfaces, also there is video sensing
District, and described pad ring is around described video sensing district.
Optionally, described encapsulating structure also includes: be positioned at the hollow and annular post on described substrate first, described hollow ring
Shape post surrounds described first functional chip；It is arranged on the light-passing board of described hollow and annular column top, and described light-passing board, hollow ring
Shape post and described substrate surround cavity, and described first functional chip is positioned at described cavity.
Optionally, described hollow and annular column top is higher than first of described first functional chip.
Optionally, between described hollow and annular column top and described light-passing board, also there is adhesive-layer.
Optionally, described second functional chip is signal processing chip；The quantity of described second functional chip more than or etc.
In 1.
Optionally, described encapsulating structure also includes: be positioned at the metal coupling on described second functional surfaces, by described metal
Projection electrically connects the line layer that described second functional surfaces exposes with described substrate the second face.
Optionally, described solder-bump is distributed in around described second functional chip.
Optionally, the distance between described second solder-bump top and described substrate second is more than described second function
Distance between chip second back side and described substrate second.
Optionally, described encapsulating structure also includes: the adhesion layer between described first back side and described first.
Optionally, described encapsulating structure also includes: be positioned at the insulating barrier in described substrate portion second, and described welding
Projection runs through described insulating barrier；It is positioned at the welding resisting layer on described substrate first, and described wire runs through described welding resisting layer.
Optionally, described encapsulating structure also includes: is positioned at described substrate second and covers the second functional chip sidewall
Plastic packaging layer.
The present invention also provides for a kind of method for packing, including: several first functional chips and the second functional chip are provided,
Described first functional chip has the first relative functional surfaces and first back side, and described first functional surfaces has pad, described
Second functional chip has the second relative functional surfaces and second back side；There is provided substrate, described substrate have some functional areas and
Cutting Road region between adjacent functional district, described substrate has in relative first and second, and described substrate
There is line layer；Being arranged in first, described functional substrate district by described first functional chip, described first back side is with described
First fixed engagement；Formed and electrically connect described pad and the wire of line layer；Described second functional chip upside-down mounting is arranged
In second, described functional substrate district, described second functional surfaces with described second relative, and described second functional surfaces and institute
State the line layer electrical connection that the second face, functional substrate district exposes；Second, described functional substrate district is formed solder-bump,
The line layer that described solder-bump exposes with the second face, described functional substrate district electrically connects；Institute is cut along described Cutting Road region
State substrate, form some single encapsulating structures.
Optionally, described first functional chip is image sensing chip；On described first functional surfaces, also there is video sensing
District, and described pad ring is around described video sensing district；Described method for packing also includes: shape in first, described functional substrate district
Become hollow and annular post, and after described first functional chip is arranged in first, described functional substrate district, described hollow and annular
Post surrounds described first functional chip；Light-passing board, and described light-passing board, hollow and annular post are set in described hollow and annular column top
And substrate surrounds cavity, and described first functional chip is positioned at described cavity.
Optionally, before described first functional chip is arranged in first, described functional substrate district, formed described
Hollow and annular post.
Optionally, use coating process and photoetching process, form described hollow and annular post；Or, use resin printing
Technique, forms described hollow and annular post.
Optionally, use routing technique, form described wire.
Optionally, before described second functional chip upside-down mounting is arranged in second, described functional substrate district, also wrap
Include step: on described second functional chip the second functional surfaces or in second, described functional substrate district, form metal coupling；
Use solder bonds technique, realize described second functional surfaces and the exposure of second, described functional substrate district by described metal coupling
The line layer electrical connection gone out.
Optionally, before cutting described substrate, further comprise the steps of: and formed in described functional substrate district part second
Plastic packaging layer, and the described plastic packaging layer described second functional chip sidewall of covering.
Optionally, before forming described solder-bump, described plastic packaging layer is formed；Or, forming described solder-bump
Afterwards, described plastic packaging layer is formed.
Compared with prior art, technical scheme has the advantage that
In the technical scheme of the encapsulating structure that the present invention provides, the first functional chip and the second functional chip setting respectively
Put on two faces that substrate is relative, be arranged on parallel on same of substrate with the first functional chip and the second functional chip
Scheme compare, the size that (is parallel on substrate surface direction) in the horizontal direction of encapsulating structure that the present invention provides is the most more
It is little, so that the integrated level of encapsulating structure is higher.Further, it is arranged on described second functional chip due to described solder-bump
On the same face of described substrate, thus reduce described encapsulating structure as far as possible at the gauge being perpendicular on horizontal plane,
Reduce the gross thickness of product.
In alternative, the first functional chip is image sensing chip, and described encapsulating structure also includes: be positioned at described substrate
Hollow and annular post on first, described hollow and annular post surrounds described first functional chip；It is arranged on described hollow and annular post
The light-passing board at top, and described light-passing board, hollow and annular post and described substrate surround cavity, described first functional chip is positioned at
In described cavity.The present invention has protective effect to the video sensing district of the first functional chip, prevents described video sensing district to be subject to
To damage.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of encapsulating structure；
The structural representation of the encapsulating structure that Fig. 2 provides for the embodiment of the present invention；
The method for packing that Fig. 3 to Figure 10 provides for using the embodiment of the present invention is packaged the structural representation of process.
Detailed description of the invention
From background technology, the size of the encapsulating structure that prior art provides is big, integrated level has much room for improvement.
Being analyzed in conjunction with a kind of encapsulating structure, Fig. 1 is the structural representation of a kind of encapsulating structure, with reference to Fig. 1, described
Encapsulating structure includes: has the substrate 10 of relative upper surface and lower surface, circuit interconnection layer is distributed in described substrate 10
Having the hollow out 11 running through described substrate 10 in (sign), and described substrate 10, described light-passing board 20 is pasted on described substrate
The upper surface of 10 hollow outs 11；Upside-down mounting is electrically connected to the first functional chip 30 of described substrate 10 lower surface, and described first function
The functional areas of chip 30 are positioned at immediately below described hollow out 11, and the pad (sign) of described first functional chip 30 is mutual with circuit
Even layer electrical connection；It is positioned at described substrate 10 upper surface and the second functional chip electrically connected by wire 40 with described substrate 10
50, described second functional chip 50 is positioned at described hollow out 11 side；It is positioned at the BGA stannum ball 60 of described substrate 30 lower surface；It is positioned at
Described substrate 10 surface and the plastic packaging layer 70 of covering the second functional chip 50 sidewall.
Above-mentioned encapsulating structure size in the horizontal direction is big, and the integrated level causing encapsulating structure is low, is unfavorable for meeting device
The development trend of part miniaturization miniaturization.
For solving the problems referred to above, the present invention provides a kind of encapsulating structure, significantly reduces the size of encapsulating structure.For making this
The above-mentioned purpose of invention, feature and advantage can become apparent from understandable, do the specific embodiment of the present invention below in conjunction with the accompanying drawings
Detailed description.
The structural representation of the encapsulating structure that Fig. 2 provides for the embodiment of the present invention.
With reference to Fig. 2, described encapsulating structure includes:
Substrate 101, described substrate 101 has relative first (sign) and second (sign), and described base
There is in plate 101 line layer 102；
Being positioned at the first functional chip 201 on described substrate 102 first, described first functional chip 201 has relatively
The first functional surfaces (sign) and first back side (sign), described first functional surfaces has pad 202, described first back of the body
Face and described first fixed engagement, and described pad 202 electrically connected with described line layer 102 by wire 203；
Upside-down mounting is arranged on the second functional chip 301 on described substrate 101 second, and described second functional chip 301 has
There are relative the second functional surfaces (sign) and second back side (sign), and described second functional surfaces and described substrate 101 the
The line layer 102 come out in two faces electrically connects；
It is positioned at the solder-bump 401 on described substrate 101 second, described solder-bump 401 and described substrate 101 second
The line layer 102 that face exposes electrically connects.
The encapsulating structure provided the present embodiment below with reference to accompanying drawing is described in detail.
Described substrate 101 plays described first functional chip 201 and the effect of the second functional chip 301 of support；Additionally,
Described substrate 101 also acts as described first functional chip 201 and the effect of the second functional chip 301 of electrical connection, and is additionally operable to
It is electrically connected with external circuits or miscellaneous part.
Described substrate 101 is glass substrate, metal basal board, semiconductor substrate or polymeric substrates.In the present embodiment, institute
State substrate 101 for PCB substrate.
In described substrate 101, also there is line layer 102.In the present embodiment, according to wiring and electrical connection demand, described line
Road floor 102 is the multilayer wiring interconnection architecture being positioned at described substrate 101.Wherein, the line layer 102 that described first face exposes
For electrically connecting with the first functional chip 201；The line layer 102 that described second face exposes for the second functional chip 301
Electrical connection.
In the present embodiment, described substrate 101 first can also have welding resisting layer (Solder Mask Layer) 103, institute
State welding resisting layer 103 be positioned at described substrate 101 first and cover described line layer 102, and, described welding resisting layer 103 exposes
The part surface of described line layer 102 so that one end of described wire 203 be positioned at described in line layer 102 surface that exposes, protect
Demonstrate,prove described wire 203 to electrically connect with described line layer 102.
The material of described welding resisting layer 103 is green oil.Described welding resisting layer 103 is made for described line layer 102 plays protection
With, it is to avoid line layer 102 is oxidized, and prevents from, between described line layer 102 and miscellaneous part, unnecessary electrical connection occurs.
In the present embodiment, described first functional chip 201 is image sensing chip, and described first functional surfaces also has shadow
As induction zone 204, and described pad 202 is around described video sensing district 204.Described first functional surfaces for have pad 202 with
And the face in video sensing district 204, described first back side is the face of second fixed engagement with substrate 201.
Can have, in described first functional chip 201, the metal electrically connected in described video sensing district 204 and pad 202
Interconnection structure (not shown), be formed in described video sensing district 204 image sensor unit and with and with image sensor list
The associated circuit that unit is connected, ambient is received and converted into electrical signal, and described electricity is believed by video sensing district 204
Number by the line layer 102 on metal interconnection structure and pad 204 and substrate 101, in order to be sent to the second functional chip
In 301.
For the ease of wiring, described video sensing district 204 is positioned at the centre position of described first functional surfaces, described pad
202 marginal positions being positioned at described first functional surfaces, and described pad 202 is positioned at four sides in described video sensing district 204, in square
Shape is distributed, and each side in described video sensing district 204 has several pads 202, and each pad 202 passes through wire
203 electrically connect with the line layer 102 on described substrate 101 first.
Described wire 203 summit is higher than described first functional chip 201 first.One end of described wire 203 is with described
Pad 202 electrically connects, and the other end of described wire 203 electrically connects with described line layer 102, so that described first function core
Sheet 201 circuit electrically connects with the line layer 102 on described substrate 101 first.Described wire 203 is connected to described pad 202
And between described line layer 102, the most described wire 203 bends.
The material of described wire 203 is metal, and described metal includes copper, aluminum, tungsten, golden or silver-colored.
In the present embodiment, in order to improve first back side of described first functional chip 201 and described substrate 101 first it
Between binding ability, between described first back side and described first, also there is adhesion layer, improve described by described adhesion layer
Binding ability between first back side and described first.
In order to protective effect is improved in the video sensing district 204 on described first functional chip 201 first, prevent image
Induction zone 204 sustains damage, and in the present embodiment, in described encapsulating structure, described video sensing district 204 is protected.Specifically,
Described encapsulating structure also includes: be positioned at the hollow and annular post 104 on described substrate 101 first, and described hollow and annular post 104 wraps
Enclose described first functional chip 201；It is arranged on the light-passing board 105 at described hollow and annular post 104 top, and described light-passing board 105,
Hollow and annular post 104 and described substrate 101 surround cavity, and described first functional chip 201 is positioned at described cavity.
Described hollow and annular post 104 top is higher than first of described first functional chip 201, specifically, the present embodiment
In, described hollow and annular post 104 top, higher than the video sensing district 204 on described first functional chip 201 first, prevents institute
State light-passing board 105 and touch described video sensing district 204.
The material of described hollow and annular post 104 is Other substrate materials or resin material.
In the present embodiment, the summit of described wire 203 is higher than top, described video sensing district 204, wherein, described wire
The summit of 203 is distance the first functional chip 201 first functional surfaces point furthest in described wire 203, in order to avoid institute
Stating light-passing board 105 and touch described wire 203, described hollow and annular post 104 top is higher than the summit of described wire 203.Due to
Having welding resisting layer 103 on described substrate 101 first, the most described wire 203 runs through described welding resisting layer 103 so that described in lead
Line 203 electrically connects with the line layer 102 of described substrate 101 first.
Owing to described first functional chip 201 is positioned at described cavity, the cavity wall of described cavity is to described video sensing district
204 provide protective effect, it is to avoid described video sensing district 204 sustains damage；Further, it is light-passing board due to described cavity top
105 so that ambient can be irradiated in described video sensing district 204 via described light-passing board 105, described video sensing district
204 receive external optical signals to be converted into the signal of telecommunication.
Described second functional chip 301 upside-down mounting is arranged on described substrate 101 second, described second functional chip 301
Having the second relative functional surfaces and second back side, wherein, described second functional surfaces is the surface with circuit-wiring layer.
In the present embodiment, described second functional chip 301 is signal processing chip, and described second functional chip 301 is used for
Process the signal of telecommunication that described first functional chip 201 utilizes optical signal to convert, for example, it is possible to Electric signal processing is converted into display
Format signal required by terminal.The quantity of described second functional chip 301 is more than or equal to 1；In the present embodiment, with described
The quantity of two functional chips 301 is 1 as example.
The line layer 102 that described second functional surfaces exposes with described substrate 101 second face electrically connects.Described encapsulating structure
Also include: be positioned at the metal coupling 302 on described second functional surfaces, electrically connect described second merit by described metal coupling 302
The line layer 102 that energy face exposes with described substrate 101 second face.
Described metal coupling 302 is connected with the circuit-wiring layer on described second functional chip 301 second functional surfaces, from
And the line layer 102 making described second functional surfaces and described substrate 101 second face expose by metal coupling 302 is electrically connected
Connect.
According to the electrical connection demand of the circuit-wiring layer on described second functional chip 301 second functional surfaces, determine described
The position of metal coupling 302 and quantity.The material of described metal coupling 302 is copper, aluminum, tungsten, gold or stannum.In the present embodiment,
The material of described metal coupling 302 is gold.
In the present embodiment, described encapsulating structure also includes: is positioned at described substrate 101 part second and covers described second
The plastic packaging layer 303 of functional chip 301 sidewall.
Described plastic packaging layer 303 plays the effect protecting described second functional chip 301, prevent dampness by outside invade and
External electrical insulate, and prevents the second functional chip 301 performance failure caused under the influence of external environment；Described plastic packaging layer
303 also act as the most firm effect of associativity between described second functional chip 301 and described substrate 101 so that described
Second functional chip 301 is difficult to come off from substrate 101.
In the present embodiment, described plastic packaging layer 303 covers the second functional chip 301 partial sidewall.In other embodiments, institute
State plastic packaging layer and can also cover the second whole sidewall of functional chip, or, described plastic packaging layer is whole except covering the second functional chip
Second functional chip second back side is also covered outside sidewall.
The material of described plastic packaging layer 303 is resin or anti-solder ink material, described resin can be epoxy resin or
Acrylic resin.
Described solder-bump 401, for electrically connecting with external circuit or other devices, is made by described solder-bump 401
Described second functional chip 301 electrically connects with external circuit or other devices.In the present embodiment, described solder-bump 401 is distributed
Around described second functional chip 301.
In the present embodiment, described solder-bump 401 crest surface shape is arc, and the material of described solder-bump 401 is
Stannum.In other embodiments, the material of described solder-bump can also be gold or ashbury metal, and described ashbury metal can be stannum
Silver, tin-lead, SAC, stannum silver zinc, stannum zinc, stannum bismuth indium, stannum indium, Sillim, stannum copper, stannum zinc indium or stannum silver antimony etc..
In order to avoid when described solder-bump 401 electrically connects with external circuit or other devices to the second functional chip
301 cause damage, and described solder-bump 401 top is higher than second back side of described second functional chip 301.
In the present embodiment, described encapsulating structure also includes: be positioned at the insulating barrier 402 in described substrate 101 part second,
And described solder-bump 401 runs through described insulating barrier 402.The line layer 102 exposed can be played guarantor by described insulating barrier 402
Protect effect, it is to avoid line layer 102 is exposed in external environment oxidation or the problem of unnecessary electrical connection that may cause.
The material of described insulating barrier 402 is silicon oxide or resin.In the present embodiment, described plastic packaging layer 303 is also located at portion
Divide on insulating barrier 402, it is ensured that the line layer 102 exposed is covered by described plastic packaging layer 303 or covered by insulating barrier 402.
It should be noted that in other embodiments, it is also possible to only with plastic packaging layer, the line layer exposed is covered
Lid.
The present invention provide encapsulating structure in, described first functional chip and the second functional chip respectively be arranged on institute
State on two faces that substrate is relative, be arranged on parallel on same of substrate with the first functional chip and the second functional chip
Scheme is compared, and the size that the encapsulating structure that the present invention provides (is parallel on substrate surface direction) in the horizontal direction is the most more
It is little, so that the integrated level of encapsulating structure is higher.
Further, owing to described solder-bump and described second functional chip are arranged on the same face of described substrate, thus
Reduce described encapsulating structure as far as possible in the gauge being perpendicular on horizontal plane, the gross thickness of reduction product.
Accordingly, the present invention also provides for a kind of method for packing, including: several first functional chips and the second merit are provided
Energy chip, described first functional chip has the first relative functional surfaces and first back side, described first functional surfaces has weldering
Dish, described second functional chip has the second relative functional surfaces and second back side；Thering is provided substrate, described substrate has some merits
Can district and the Cutting Road region between adjacent functional district, described substrate has relative first and second, and described
There is in substrate line layer；Described first functional chip is arranged in first, described functional substrate district, described first back side
With described first fixed engagement；Formed and electrically connect described pad and the wire of line layer；Described second functional chip is fallen
Dress is arranged in second, described functional substrate district, described second functional surfaces with described second relative, and described second function
The line layer that face exposes with the second face, described functional substrate district electrically connects；Second, described functional substrate district is formed welding
Projection, the line layer that described solder-bump exposes with the second face, described functional substrate district electrically connects；Along described Cutting Road region
Cut described substrate, form some single encapsulating structures.
Use the method for packing that the present invention provides, owing to the first functional chip and the second functional chip are arranged on described base
On two faces that plate is relative, so that the size that the encapsulating structure formed is in the horizontal direction is substantially reduced, thus improve
The integrated level of encapsulating structure.
The method for packing that Fig. 3 to Figure 10 provides for using the embodiment of the present invention is packaged the structural representation of process.
With reference to Fig. 3, it is provided that several first functional chips 201, described first functional chip 201 has the first relative merit
Energy face and first back side, described first functional surfaces has pad 202.
Specifically, it is provided that the first function wafer；Cut described first function wafer and form many first functional chips 201.
In the present embodiment, described first functional chip 201 is image sensing chip, and described first functional surfaces also has shadow
As induction zone 204.Description about described pad 202 and video sensing district 204 refers to the corresponding description of previous embodiment,
Do not repeat them here.
With reference to Fig. 4, it is provided that several second functional chips 301, described second functional chip 301 has the first relative merit
Can face and second back side.
Specifically, it is provided that the second function wafer；Cut described second function wafer and form multiple second functional chip 301.
In the present embodiment, described second functional chip 301 is signal processing chip, and described second functional surfaces is to have circuit-wiring layer
Face.
In the present embodiment, further comprise the steps of: on described second functional chip 301 second functional surfaces, form at least one gold
Belong to projection 302, and described metal coupling 302 electrically connects with the circuit-wiring layer of described second functional surfaces.
Described metal coupling 302 is utilized to make the second functional surfaces of described second functional chip 301 and the substrate of follow-up offer
The line layer that second face exposes is electrically connected.Circuit-wiring layer according to described second functional chip 301 second functional surfaces
The demand being electrically connected, is arranged on described second functional chip 301 second functional surfaces the position of the metal coupling 302 formed
And quantity.
The material of described metal coupling 302 is copper, aluminum, tungsten, gold or stannum；Use screen printing technique or plant ball technique,
Form described metal coupling 302.
It should be noted that in other embodiments, it is also possible to not shape on described second functional chip the second functional surfaces
Become metal coupling, the line layer that substrate second face of follow-up offer exposes forms described metal coupling.
With reference to Fig. 5, it is provided that substrate 101, described substrate 101 has some functional areas I and between adjacent functional district I
Cutting Road region II, described substrate 101 has line layer in having relative first and second, and institute's upper substrate 101
102。
Described substrate 101 is glass substrate, metal basal board, semiconductor substrate or polymeric substrates.In the present embodiment, institute
State substrate 101 for PCB substrate.
Follow-up first functional chip 201 (with reference to Fig. 3) and the second functional chip 301 (with reference to Fig. 4) are being arranged on institute
After stating substrate 101 functional areas I, can along described Cutting Road region II cut described substrate 101, be positioned at functional areas I substrate 101,
First functional chip 201 and the second functional chip 301 will become the encapsulating structure of some single.
In the present embodiment, according to wiring and electrical connection demand, described line layer 102 is for have in described substrate 101
Multilayer wiring interconnection architecture, wherein, the line layer 102 that described first face exposes is for follow-up electric with the first functional chip 201
Connecting, the line layer 102 that described second face exposes electrically connects with the second functional chip 301 for follow-up.
In the present embodiment, described substrate 101 first face is also formed with welding resisting layer 103, and described welding resisting layer 103 is positioned at described base
Plate 101 first and also cover described line layer 102, prevents described line layer 102 oxidized or is corroded.Described substrate
102 second faces are also formed with insulating barrier 402, and described insulating barrier 402 is positioned at described substrate 101 second and covers described line layer
102, prevent described line layer 102 oxidized or be corroded.
With reference to Fig. 6, described substrate 101 functional areas I first forms hollow and annular post 104.
Described hollow and annular post 104 is subsequently used for providing described first functional chip 201 (with reference to Fig. 3) protecting, and
After described hollow and annular post 104 top arranges light-passing board so that described hollow and annular post 104, light-passing board and described substrate 101
Surround cavity, and described first functional chip 201 is positioned at described cavity, it is to avoid the video sensing in the first functional chip 201
District 204 is contaminated or damages.
In the present embodiment, the material of described hollow and annular post 104 is photoresist, uses coating process and photoetching process,
Form described hollow and annular post 104.In other embodiments, when the material of described hollow and annular post is resin material, it is also possible to
Use resin typography, form described hollow and annular post.
It should be noted that the thickness of described hollow and annular post 104 should not be the thinnest, follow-up when described first functional chip
After 201 are arranged on described substrate 101 first, described hollow and annular post 104 top should be higher than that video sensing district 204, prevents
The light-passing board of follow-up setting touches described video sensing district 204.
Also, it should be noted in the present embodiment, the hollow and annular post 104 between adjacent functional district I is separate,
In other embodiments, the hollow and annular post of formation is also located at Cutting Road region, the therefore hollow and annular between adjacent functional district
Post is integrated, and follow-up also cutting when cutting described substrate along Cutting Road is positioned at the hollow and annular post in Cutting Road region.
In the present embodiment, before described substrate 101 first arranges the first functional chip 201, at described substrate 101
First, functional areas are upper forms described hollow and annular post 104, it is to avoid form the technique of described hollow and annular post 104 to the first function
Chip 201 brings damage.
With reference to Fig. 7, described first functional chip 201 is arranged on first, described substrate 101 functional areas, described first
The back side and described first fixed engagement；Formed and electrically connect described pad 202 and the wire 203 of line layer 102.
In the present embodiment, described first back side or described first arrange adhesion layer (not shown), by described
Adhesion layer realizes the fixed engagement at described first back side and described first.Be conducive to improving described substrate at described adhesion layer
Adhesion between 101 and described first functional chip 201.
Described pad 202 electrically connects with the line layer 102 of described substrate 101 first, specifically, real by wire 203
The electrical connection of existing the most described pad 202 and described line layer 102, described wire 203 one end is connected with described pad 202, described in lead
Line 203 other end is connected with described line layer 102.In the present embodiment, owing to being formed with welding resisting layer on described substrate 101 first
103, the most described wire 203 runs through described welding resisting layer 103, so that described wire 203 one end and described substrate 101 function
The line layer 102 that district is first electrically connects.
The technique forming described wire 203 is routing technique, and the material of described wire 203 is metal, described metal be copper,
Aluminum, tungsten, silver-colored or golden.
Described wire 203 bends.In the present embodiment, described wire 203 summit is less than described hollow and annular post 104 top,
Thus prevent the light-passing board of follow-up setting from touching described wire 203.
With reference to Fig. 8, light-passing board 105, and described light-passing board 105, hollow and annular are set at described hollow and annular post 104 top
Post 104 and described substrate 101 surround cavity, and described first functional chip 201 is positioned at described cavity.
Single described light-passing board 105 can be across at least one functional areas I.In the present embodiment, above each functional areas I
Form single light-passing board 105.
In other embodiments, described light-passing board can also be across at least two functional areas, such as, on all functional areas
Side arranges one piece of light-passing board.
It should be noted that when described light-passing board 105 is across at least two functional areas I, described light-passing board 105 is also located at
Above the II of Cutting Road region, follow-up when cutting described substrate 101 along Cutting Road region II, also cut described light-passing board 105.
In the present embodiment, before described light-passing board 105 is set, also form viscose glue at described hollow and annular post 104 top
Layer (not shown), the material of described adhesive-layer can be UV adhesive tape or pyrolysis glue adhesive tape.In other embodiments, it is also possible to logical
Cross the mode of Direct Bonding, make described light-passing board and described hollow and annular column top fixed engagement.
In other embodiments, it is also possible to by the way of Direct Bonding, described light-passing board 105 and described hollow and annular are made
Post 104 top fixed engagement.
With reference to Fig. 9, described second functional chip 301 upside-down mounting is arranged on described substrate 101 functional areas I second, institute
State the second functional surfaces with described second relative, and described second functional surfaces exposes with described substrate 101 functional areas I the second face
Line layer 102 electrically connect.
In the present embodiment, it is being inverted in being arranged on described substrate 101 functional areas I second by described second functional chip 301
Before face, first etching removes the partial insulative layer 402 on described substrate 101 functional areas I second, exposes described substrate 101
Functional areas I part second, and expose the line layer 102 electrically connected with described second functional surfaces；By described second function core
Sheet 301 upside-down mounting be arranged on described on the substrate 101 functional areas I second that exposes.
The quantity of the second functional chip 301 being inverted on substrate 101 same functional areas I second is more than or equal to 1.This
In embodiment, it is 1 as showing to be inverted in the quantity of the second functional chip 301 on substrate 101 same functional areas I second
Example.
In the present embodiment, realize described second functional surfaces and described substrate 101 functional areas I by described metal coupling 302
Electrical connection between the line layer 102 that second face exposes.Specifically, use solder bonds technique, make described metal coupling 302
Line layer 102 fixed engagement exposed with described substrate 101 functional areas I the second face, wherein, described solder bonds technique is common
Brilliant bonding, ultrasonic thermocompression, thermal compression welding or ultrasonic wire bonding etc..
With reference to Figure 10, described substrate 101 functional areas I second forms solder-bump 401, described solder-bump 401
The line layer 102 exposed with described substrate 101 functional areas I the second face electrically connects.
Electrically connected with described second functional chip 301 by described solder-bump 401, and described solder-bump 401 is also used
Electrically connect in external circuit or other devices, so that described second functional chip 301 and external circuit or other devices
Electrical connection.
In the present embodiment, owing to being also formed with insulating barrier 402 on described substrate 101 functional areas I second, described being formed
Before solder-bump 402, first etching removes partial insulative layer 402, exposes the portion on described substrate 101 functional areas I second
Divide line layer 102；The line layer 102 that described substrate 101 functional areas I the second face exposes forms described solder-bump 401.
Described solder-bump 401 top to the distance of described substrate 101 second more than described second functional chip 301 the
The distance of two back sides extremely described substrate 101 second, it is ensured that when described solder-bump 401 electrically connects with external circuit or device
Second functional chip 301 will not be caused extruding.In other embodiments, described solder-bump top is to described substrate second
Distance can also be equal to or less than described second functional chip second back side to the distance of described substrate second.
Described solder-bump 401 crest surface shape is arc, and the material of described solder-bump 401 is gold, stannum or stannum
Alloy, described ashbury metal can be stannum silver, tin-lead, SAC, stannum silver zinc, stannum zinc, stannum bismuth indium, stannum indium, Sillim, stannum copper, stannum zinc
Indium or stannum silver antimony etc..
In the present embodiment, use and plant ball technique, form described solder-bump 401.In other embodiments, it is also possible to use
Screen printing technique and reflux technique, form described solder-bump.
With continued reference to Figure 10, described substrate 101 functional areas I second forms plastic packaging layer 303, described plastic packaging layer 303
Cover described second functional chip 301 sidewall.
In the present embodiment, described plastic packaging layer 303 is except covering the line layer that described substrate 101 functional areas I the second face exposes
Outside 102, it is also located at partial insulative layer 402 surface.
Described plastic packaging layer 303 plays the effect of protection the second functional chip 301, prevents dampness from being invaded by outside so that institute
State the second functional chip 301 to insulate with external electrical.Additionally, described plastic packaging layer 303 also acts as supports the second functional chip 301
Effect, improves the associativity between the second functional chip 301 and described substrate 101.
Using plastic package process (molding) to form described plastic packaging layer 303, described plastic package process uses branch mode or pressing
Mode；Gluing process can also be used to form described plastic packaging layer 303.
In the present embodiment, described plastic packaging layer 303 covers the second functional chip 301 partial sidewall.In other embodiments, institute
State plastic packaging layer and can also cover the second whole sidewall of functional chip, or, described plastic packaging layer is whole except covering the second functional chip
Outside sidewall, also cover second functional chip second back side.
The mode using whole module or some separate modules forms described plastic packaging layer 211.In the present embodiment, use some
It is the most solely that the mode of individual discrete module forms the plastic packaging floor 303 on described plastic packaging layer 303, i.e. adjacent functional district I second
Stand.In other embodiments, it is also possible to use the mode of whole module to form described plastic packaging layer, i.e. to monoblock substrate second
The plastic packaging layer of upper formation monoblock.
Specifically, use the mode of separate module to form the method for described plastic packaging layer 303 to be: use multiple mould, and often
Individual mould is filled plastic packaging layer 303 material；By mold compresses on described substrate 101 functional areas I second, carry out drying and processing
Recession, except mould, forms the plastic packaging layer 303 with some separate modules.
The material of described plastic packaging layer 303 is resin or anti-solder ink material, such as, epoxy resin or acrylic resin.
In the present embodiment, described plastic packaging layer 303 exposes described solder-bump 401 sidewall.In other embodiments, described
Plastic packaging layer can also cover described solder-bump sidewall, thus plays a protective role the sidewall of solder-bump, and further
Improve the associativity between solder-bump and described substrate.
It should be noted that in the present embodiment, as a example by forming described plastic packaging layer after being initially formed described solder-bump 401；
In other embodiments, it is also possible to being initially formed described plastic packaging layer, the described solder-bump of rear formation, and described plastic packaging layer can expose
Go out solder-bump sidewall, it is also possible to cover described solder-bump sidewall.
After forming described solder-bump 401 and plastic packaging layer 303, cut described substrate along described Cutting Road region II
101, form some single encapsulating structures as shown in Figure 2.
In the present embodiment, use microtome knife cutting or laser cutting parameter to cut described substrate 101, form some single envelopes
Assembling structure.
Due to described first functional chip 201 and described second functional chip 301, to lay respectively at described substrate 101 relative
Two faces on, specifically, described first functional chip 201 is positioned on described substrate 101 first, described second functional chip
301 are positioned on described substrate 101 second, and the encapsulating structure that therefore the present embodiment is formed size in the horizontal direction substantially subtracts
Little, thus improve the integrated level of the encapsulating structure of formation.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from this
In the spirit and scope of invention, all can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Limit in the range of standard.
Claims (20)
1. an encapsulating structure, it is characterised in that including:
Substrate, described substrate has line layer in having relative first and second, and described substrate；
Be positioned at the first functional chip on described substrate first, described first functional chip have the first relative functional surfaces and
First back side, described first functional surfaces has pad, described first back side and described first fixed engagement, and described pad
Electrically connected with described line layer by wire；
Upside-down mounting is arranged on the second functional chip on described substrate second, and described second functional chip has the second relative merit
Can face and second back side, described second functional surfaces with described second relative, and described second functional surfaces and described substrate second
The line layer electrical connection that face exposes；
It is positioned at the solder-bump on described substrate second, the line layer that described solder-bump exposes with described substrate the second face
Electrical connection.
2. encapsulating structure as claimed in claim 1, it is characterised in that described first functional chip is image sensing chip；Institute
State and also there is on the first functional surfaces video sensing district, and described pad ring is around described video sensing district.
3. encapsulating structure as claimed in claim 2, it is characterised in that described encapsulating structure also includes:
Being positioned at the hollow and annular post on described substrate first, described hollow and annular post surrounds described first functional chip；
It is arranged on the light-passing board of described hollow and annular column top, and described light-passing board, hollow and annular post and described substrate surround
Cavity, described first functional chip is positioned at described cavity.
4. encapsulating structure as claimed in claim 3, it is characterised in that described hollow and annular column top is higher than described first function
First of chip.
5. encapsulating structure as claimed in claim 2, it is characterised in that between described hollow and annular column top and described light-passing board
Also there is adhesive-layer.
6. encapsulating structure as claimed in claim 1, it is characterised in that described second functional chip is signal processing chip；Institute
State the quantity of the second functional chip more than or equal to 1.
7. encapsulating structure as claimed in claim 6, it is characterised in that described encapsulating structure also includes: be positioned at described second merit
Metal coupling on energy face, is exposed by described metal coupling described second functional surfaces of electrical connection and described substrate the second face
Line layer.
8. encapsulating structure as claimed in claim 1, it is characterised in that described solder-bump is distributed in described second functional chip
Around.
9. encapsulating structure as claimed in claim 1, it is characterised in that described second solder-bump top and described substrate second
Distance between face is more than the distance between described second functional chip second back side and described substrate second.
10. encapsulating structure as claimed in claim 1, it is characterised in that described encapsulating structure also includes: be positioned at described first back of the body
Adhesion layer between face and described first.
11. encapsulating structures as claimed in claim 1, it is characterised in that described encapsulating structure also includes: be positioned at described baseplate part
Insulating barrier on point second, and described solder-bump runs through described insulating barrier；It is positioned at the welding resisting layer on described substrate first,
And described wire runs through described welding resisting layer.
12. encapsulating structures as claimed in claim 1, it is characterised in that described encapsulating structure also includes: be positioned at described substrate
Two and the plastic packaging layer of covering the second functional chip sidewall.
13. 1 kinds of method for packing, it is characterised in that including:
Several first functional chips and the second functional chip, described first functional chip is provided to have the first relative function
Face and first back side, described first functional surfaces has pad, described second functional chip have the second relative functional surfaces and
Second back side；
Thering is provided substrate, described substrate has some functional areas and the Cutting Road region between adjacent functional district, described substrate
In there is relative first and second, and described substrate, there is line layer；
Being arranged in first, described functional substrate district by described first functional chip, described first back side is consolidated with described first
Fixed joint；
Formed and electrically connect described pad and the wire of line layer；
Described second functional chip upside-down mounting is arranged in second, described functional substrate district, described second functional surfaces and described the
Two relatively, and the line layer that described second functional surfaces exposes with the second face, described functional substrate district electrically connects；
Forming solder-bump in second, described functional substrate district, described solder-bump is sudden and violent with second, described functional substrate district
The line layer electrical connection exposed；
Cut described substrate along described Cutting Road region, form some single encapsulating structures.
14. method for packing as claimed in claim 13, it is characterised in that described first functional chip is image sensing chip；
Also there is on described first functional surfaces video sensing district, and described pad ring is around described video sensing district；Described method for packing is also
Including:
First, described functional substrate district is formed hollow and annular post, and when described first functional chip is arranged on described substrate
After first, functional areas are upper, described hollow and annular post surrounds described first functional chip；
Light-passing board is set in described hollow and annular column top, and described light-passing board, hollow and annular post and substrate surround cavity, and
Described first functional chip is positioned at described cavity.
15. method for packing as claimed in claim 14, it is characterised in that described first functional chip is being arranged on described base
Before first, plate functional areas are upper, form described hollow and annular post.
16. method for packing as claimed in claim 15, it is characterised in that use coating process and photoetching process, form institute
State hollow and annular post；Or, use resin typography, form described hollow and annular post.
17. method for packing as claimed in claim 13, it is characterised in that use routing technique, form described wire.
18. method for packing as claimed in claim 13, it is characterised in that described second functional chip upside-down mounting is being arranged on institute
Before stating in second, functional substrate district, further comprise the steps of: on described second functional chip the second functional surfaces or described base
Metal coupling is formed on second, plate functional areas；Use solder bonds technique, realize described second merit by described metal coupling
The line layer that energy face exposes with the second face, described functional substrate district electrically connects.
19. method for packing as claimed in claim 13, it is characterised in that before cutting described substrate, further comprise the steps of:
The upper plastic packaging floor that formed of described functional substrate district part second, and the described plastic packaging layer described second functional chip sidewall of covering.
20. method for packing as claimed in claim 19, it is characterised in that before forming described solder-bump, are formed described
Plastic packaging layer；Or, after forming described solder-bump, form described plastic packaging layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610850385.XA CN106298699A (en) | 2016-09-26 | 2016-09-26 | Encapsulating structure and method for packing |
| PCT/CN2017/102607 WO2018054315A1 (en) | 2016-09-26 | 2017-09-21 | Packaging structure and packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610850385.XA CN106298699A (en) | 2016-09-26 | 2016-09-26 | Encapsulating structure and method for packing |
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| CN106298699A true CN106298699A (en) | 2017-01-04 |
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| WO2018054315A1 (en) * | 2016-09-26 | 2018-03-29 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method |
| CN108428690A (en) * | 2018-03-27 | 2018-08-21 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating structure and packaging method of chip |
| CN109417081A (en) * | 2018-09-29 | 2019-03-01 | 深圳市汇顶科技股份有限公司 | Chip-packaging structure, method and electronic equipment |
| CN109437088A (en) * | 2018-10-30 | 2019-03-08 | 苏州晶方半导体科技股份有限公司 | The encapsulating structure and packaging method of chip |
| CN109935577A (en) * | 2017-12-18 | 2019-06-25 | 无锡华润安盛科技有限公司 | A kind of packaging body |
| CN111261647A (en) * | 2020-01-20 | 2020-06-09 | 甬矽电子(宁波)股份有限公司 | Light-transmitting cover plate, optical sensor and manufacturing method thereof |
| CN117238781A (en) * | 2023-11-16 | 2023-12-15 | 江苏芯德半导体科技有限公司 | Wafer-level ultrathin four-side pin-free chip packaging method and chip packaging structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6011294A (en) * | 1996-04-08 | 2000-01-04 | Eastman Kodak Company | Low cost CCD packaging |
| US7078791B1 (en) * | 2001-05-09 | 2006-07-18 | Ess Technology, Inc. | Chip on board package for imager |
| CN102110699A (en) * | 2009-12-16 | 2011-06-29 | 三星电子株式会社 | Image sensor module, method of manufacturing same, and image processing system including image sensor module |
| CN105448944A (en) * | 2015-12-29 | 2016-03-30 | 苏州晶方半导体科技股份有限公司 | Image sensing chip packaging structure and packaging method |
| CN206259337U (en) * | 2016-09-26 | 2017-06-16 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure |
-
2016
- 2016-09-26 CN CN201610850385.XA patent/CN106298699A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6011294A (en) * | 1996-04-08 | 2000-01-04 | Eastman Kodak Company | Low cost CCD packaging |
| US7078791B1 (en) * | 2001-05-09 | 2006-07-18 | Ess Technology, Inc. | Chip on board package for imager |
| CN102110699A (en) * | 2009-12-16 | 2011-06-29 | 三星电子株式会社 | Image sensor module, method of manufacturing same, and image processing system including image sensor module |
| CN105448944A (en) * | 2015-12-29 | 2016-03-30 | 苏州晶方半导体科技股份有限公司 | Image sensing chip packaging structure and packaging method |
| CN206259337U (en) * | 2016-09-26 | 2017-06-16 | 苏州晶方半导体科技股份有限公司 | Encapsulating structure |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018054315A1 (en) * | 2016-09-26 | 2018-03-29 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method |
| CN109935577A (en) * | 2017-12-18 | 2019-06-25 | 无锡华润安盛科技有限公司 | A kind of packaging body |
| CN108428690A (en) * | 2018-03-27 | 2018-08-21 | 苏州晶方半导体科技股份有限公司 | A kind of encapsulating structure and packaging method of chip |
| CN109417081A (en) * | 2018-09-29 | 2019-03-01 | 深圳市汇顶科技股份有限公司 | Chip-packaging structure, method and electronic equipment |
| CN109417081B (en) * | 2018-09-29 | 2021-01-22 | 深圳市汇顶科技股份有限公司 | Chip packaging structure, method and electronic equipment |
| CN112820749A (en) * | 2018-09-29 | 2021-05-18 | 深圳市汇顶科技股份有限公司 | Chip packaging structure, method and electronic equipment |
| CN109437088A (en) * | 2018-10-30 | 2019-03-08 | 苏州晶方半导体科技股份有限公司 | The encapsulating structure and packaging method of chip |
| CN111261647A (en) * | 2020-01-20 | 2020-06-09 | 甬矽电子(宁波)股份有限公司 | Light-transmitting cover plate, optical sensor and manufacturing method thereof |
| CN117238781A (en) * | 2023-11-16 | 2023-12-15 | 江苏芯德半导体科技有限公司 | Wafer-level ultrathin four-side pin-free chip packaging method and chip packaging structure |
| CN117238781B (en) * | 2023-11-16 | 2024-02-23 | 江苏芯德半导体科技有限公司 | Wafer-level ultrathin four-side pin-free chip packaging method and chip packaging structure |
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