CN108428690A - A kind of encapsulating structure and packaging method of chip - Google Patents
A kind of encapsulating structure and packaging method of chip Download PDFInfo
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- CN108428690A CN108428690A CN201810259146.6A CN201810259146A CN108428690A CN 108428690 A CN108428690 A CN 108428690A CN 201810259146 A CN201810259146 A CN 201810259146A CN 108428690 A CN108428690 A CN 108428690A
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- sensing chip
- package substrate
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 239000000463 material Substances 0.000 claims description 12
- 238000012856 packing Methods 0.000 claims description 10
- 238000005520 cutting process Methods 0.000 claims description 9
- 230000003667 anti-reflective effect Effects 0.000 claims description 6
- 239000003292 glue Substances 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000010410 layer Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 230000000750 progressive effect Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000005439 thermosphere Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
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Abstract
Technical solution of the present invention discloses a kind of encapsulating structure and packaging method of chip, the technical solution is packaged processing chip and image sensing chip by package substrate, processing chip is bundled in the second surface of package substrate, image sensing chip is arranged in the receiving hole of package substrate, the processing chip and the image sensing chip are connected by the interconnection circuit on the package substrate with external circuit, on the one hand, the processing chip and the image sensing chip are oppositely arranged, reduce the area of encapsulating structure, on the other hand, the connection of chip and external circuit is realized by the interconnection circuit in package substrate, it is interconnected convenient for circuit, convenient for further increasing the integrated level of chip.
Description
Technical field
The present invention relates to chip encapsulation technology fields, more specifically, being related to encapsulating structure and the encapsulation of a kind of chip
Method.
Background technology
With science and technology be constantly progressive, more and more electronic equipments be widely used in daily life with
And in work, huge facility is brought for daily life and work, becomes the indispensable weight of current people
Want tool.Electronic equipment realizes that the critical piece of various functions is chip, in order to ensure the reliability of chip, service life and
External factor is avoided to damage, chip needs are packaged protection.
In the prior art, usually directly chip is packaged using packaging plastic, forms encapsulating structure.In this way, inconvenient
It is connected with external circuit in the encapsulating structure of chip.
Invention content
To solve the above-mentioned problems, technical solution of the present invention provides a kind of encapsulating structure and packaging method of chip,
It is connected with external circuit convenient for encapsulating structure.
To achieve the goals above, the present invention provides the following technical solutions：
A kind of encapsulating structure of chip, the encapsulating structure include：
Package substrate, the package substrate opposite first surface and second surface；Through the first surface and
The receiving hole of the second surface；The package substrate also has interconnection circuit；
It is bundled in the processing chip of the second surface, the processing chip is covered in the receiving hole and is located at described second
The opening on surface；
The image sensing chip being arranged in the receiving hole；
It is fixed on the cover board of the first surface, the cover board to the image sensing chip for being sealed protection；
Wherein, the processing chip is connect by the interconnection circuit with external circuit with the image sensing chip.
Preferably, in above-mentioned encapsulating structure, the interconnection circuit includes：The first contact in the first surface is set
End, is arranged the second contact jaw and third contact jaw in the second surface, and the wiring being arranged in the package substrate
Circuit, for the third contact jaw for connecting external circuit, first contact jaw and second contact jaw pass through institute respectively
Wired circuit is stated to connect with the different third contact jaws；
The image sensing chip is connect with first contact jaw；
The processing chip is connect with second contact jaw.
Preferably, in above-mentioned encapsulating structure, the image sensing chip have opposite front and back, the back side and
The processing chip is oppositely arranged, the first weld pad that front has the first functional unit and connected with the first functional unit,
First weld pad is connect with first contact jaw.
Preferably, in above-mentioned encapsulating structure, first weld pad is connect with first contact jaw by conducting wire.
Preferably, in above-mentioned encapsulating structure, the processing chip has opposite front and back, positive and described
Image sensing chip is oppositely arranged, the second weldering that front has the second functional unit and connected with second functional unit
Pad, second weld pad are connect with second contact jaw.
Preferably, in above-mentioned encapsulating structure, second weld pad and second contact jaw welding or described second
Weld pad passes through conductive glue connection with second contact jaw.
Preferably, in above-mentioned encapsulating structure, the image sensing chip and the processing chip are fixed by glue-line.
Preferably, in above-mentioned encapsulating structure, there is support member, the branch between the cover board and the package substrate
Support part part is for so that have default spacing between the cover board and the package substrate.
Preferably, have in above-mentioned encapsulating structure, between the image sensing chip and the gap of the receiving hole and fill out
Fill material.
Preferably, in above-mentioned encapsulating structure, the package substrate, which has, is located at the first surface and second table
Heat-conducting layer between face, the heat-conducting layer are used to heat being transmitted to the outside of the package substrate from the side wall of the receiving hole
Face.
Preferably, in above-mentioned encapsulating structure, the surface of the cover board is provided with optical filter and/or antireflective film.
The present invention also provides a kind of packaging method of chip, the packaging method includes：
There is provided a package substrate, the package substrate includes opposite first surface and second surface；The encapsulation base
Plate is divided into multiple chip bonding regions, has cutting raceway groove between two neighboring chip bonding region；The chip bonding area
Domain includes：Through the receiving hole of the first surface and the second surface；The package substrate also has interconnection circuit；
Processing chip and image sensing chip are bound in the chip bonding region；The processing chip is bundled in described
Second surface, and cover the opening that the receiving hole is located at the second surface；The image sensing chip is arranged in the appearance
It receives in hole；
Cover board is fixed in the first surface, it is described for being sealed protection to the image sensing chip；
Divide the package substrate based on the cutting raceway groove, forms multiple encapsulating structures.
Preferably, in above-mentioned packaging method, the interconnection circuit includes：The first contact in the first surface is set
End, is arranged the second contact jaw and third contact jaw in the second surface, and the wiring being arranged in the package substrate
Circuit, for the third contact jaw for connecting external circuit, first contact jaw and second contact jaw pass through institute respectively
Wired circuit is stated to connect with the different third contact jaws；
It is described to include in chip bonding region binding processing chip and image sensing chip：By the processing chip
It is connect with second contact jaw, the image sensing chip is connect with first contact jaw.
Preferably, described to bind processing chip and image biography in the chip bonding region in above-mentioned packaging method
Sense chip includes：
The processing chip and the image sensing chip are relatively fixed；
The processing chip is bound in the second surface, so that the processing chip connects with second contact jaw
It connects；
The image sensing chip is connect with first contact jaw.
Preferably, described to bind processing chip and image biography in the chip bonding region in above-mentioned packaging method
Sense chip includes：
The processing chip is bound in the second surface, so that the processing chip connects with second contact jaw
It connects；
The image sensing chip is set in the receiving hole, and the image sensing chip is arranged in the processing chip
Surface；
The image sensing chip is connect with first contact jaw.
Preferably, in above-mentioned packaging method, the image sensing chip have opposite front and back, the back side and
The processing chip is oppositely arranged, the first weld pad that front has the first functional unit and connected with the first functional unit；
It is described the image sensing chip is connect with first contact jaw including：By first weld pad and described the
One contact jaw is connected by conducting wire.
Preferably, in above-mentioned packaging method, the processing chip has opposite front and back, positive and described
Image sensing chip is oppositely arranged, the second weldering that front has the second functional unit and connected with second functional unit
Pad；
It is described the processing chip is connect with second contact jaw including：Second weld pad and described second are connect
Contravention welds, or second weld pad and second contact jaw are passed through conductive glue connection.
Preferably, in above-mentioned packaging method, the image sensing chip and the processing chip are fixed by glue-line.
Preferably, in above-mentioned packaging method, the surface of the cover board is provided with optical filter and/or antireflective film.
Preferably, in above-mentioned packaging method, further include：
Before the fixation cover board, in the gap setting packing material of the image sensing chip and the receiving hole.
By foregoing description it is found that in the encapsulating structure and packaging method of chip described in technical solution of the present invention, pass through envelope
Dress substrate is packaged processing chip and image sensing chip, and processing chip is bundled in the second surface of package substrate, will
Image sensing chip is arranged in the receiving hole of package substrate, and the processing chip and the image sensing chip pass through institute
The interconnection circuit stated on package substrate is connected with external circuit, on the one hand, by the processing chip and the image sensing chip
It is oppositely arranged, reduces the area of encapsulating structure, on the other hand, chip and outside are realized by the interconnection circuit in package substrate
The connection of circuit interconnects convenient for circuit, convenient for further increasing the integrated level of chip.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of schematic diagram of the encapsulating structure of chip provided in an embodiment of the present invention；
Fig. 2 is the schematic diagram of the encapsulating structure of another chip provided in an embodiment of the present invention；
Fig. 3-Fig. 7 is a kind of flow diagram of packaging method provided in an embodiment of the present invention；
Fig. 8-Figure 11 is the flow diagram of another packaging method provided in an embodiment of the present invention；
Figure 12-Figure 15 is a kind of production method flow chart of chip provided in an embodiment of the present invention.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As stated in the background art, usually directly chip is packaged using packaging plastic, forms encapsulating structure.In this way,
The encapsulating structure for being not easy to chip is connected with external circuit.And for multichip packaging structure, encapsulation two ought be such as needed simultaneously
When a chip, different zones usually directly on circuit boards bind two chips respectively, cause the area of circuit board larger.
Specially, with the continuous improvement of chip integration, the size of chip is smaller and smaller, the quantity of the weld pad on chip
And density is increasing, the technology difficulty directly connected with external circuit by chip surface weld pad is larger.
To solve the above problems, in the encapsulating structure and packaging method of chip described in technical solution of the present invention, pass through encapsulation
Substrate is packaged processing chip and image sensing chip, and processing chip is bundled in the second surface of package substrate, by shadow
As sensing chip is arranged in the receiving hole of package substrate, the processing chip and the image sensing chip pass through described
Interconnection circuit on package substrate is connected with external circuit, on the one hand, by the processing chip and the image sensing chip phase
To setting, the area of encapsulating structure is reduced, on the other hand, chip and external electrical are realized by the interconnection circuit in package substrate
The connection on road interconnects convenient for circuit, convenient for further increasing the integrated level of chip.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is described in further detail.
With reference to figure 1, Fig. 1 is a kind of schematic diagram of the encapsulating structure of chip provided in an embodiment of the present invention, the encapsulating structure
Including：Package substrate 11, the package substrate 11 opposite first surface and second surface；Through the first surface and
The receiving hole 111 of the second surface；The package substrate 11 also has interconnection circuit；It is bundled in the processing of the second surface
Chip 12, the processing chip 12 are covered in the opening that the receiving hole 111 is located at the second surface；It is arranged in the receiving
Image sensing chip 13 in hole 111；It is fixed on the cover board 14 of the first surface, the cover board 14 is used to pass the image
Sense chip 13 is sealed protection；Wherein, the processing chip 12 passes through interconnection electricity with the image sensing chip 13
Road is connect with external circuit.
The processing chip 12 and the image sensing chip 13 are stacked by the encapsulating structure, reduce encapsulating face
Product.The encapsulating structure is packaged protection by two chip of package substrate pair and realizes the interconnection of chip and external circuit,
The weld pad of chip is connected by the interconnection circuit on package substrate with external circuit, client is easily facilitated and realizes encapsulating structure
With the connection of external circuit.This is because with the raising of chip integration, chip front side size is smaller and smaller, and front is reserved
The space of weld pad is also more next to be lacked, and weld pad quantity is more and more, in this way if two direct laminate packagings of chip pass through, is directly passed through
Chip pad is connected with external circuit, and technology difficulty is larger, is not easy to client and is carried out circuit interconnection.And technical scheme
In, two chips are connected with the interconnection circuit in package substrate, are connected by interconnection circuit in package substrate and external circuit
It connects, and package substrate relative to chip size there is enough areas contact jaw is arranged, consequently facilitating client is packaged knot
The connection of structure and external circuit.
As shown in Figure 1, the interconnection circuit includes：The first contact jaw 112 in the first surface is set, is arranged in institute
The second contact jaw 113 and third contact jaw 115 of second surface are stated, and the wired circuit being arranged in the package substrate 11
114, for connecting external circuit, first contact jaw 112 and second contact jaw 113 divide the third contact jaw 115
It is not connected by the wired circuit 114 and the different third contact jaws 115；The image sensing chip 13 and described the
One contact jaw 112 connects；The processing chip 12 is connect with second contact jaw 113.
In the embodiment of the present invention, the image sensing chip 13 has opposite front and back, the back side and the place
Reason chip 12 is oppositely arranged, and front has the first functional unit 131 and the first weld pad with the connection of the first functional unit 131
132, first weld pad 132 is connect with first contact jaw 112.In mode shown in Fig. 1, first weld pad 131 and institute
The first contact jaw 112 is stated to connect by conducting wire 15.
In the embodiment of the present invention, there is the processing chip 12 opposite front and back, front and the image to pass
Sense chip 13 is oppositely arranged, positive second for having the second functional unit 121 and being connected with second functional unit 121
Weld pad 122, second weld pad 121 are connect with second contact jaw 113.Second weld pad 122 is contacted with described second
113 welding of end or second weld pad 122 pass through conductive glue connection with second contact jaw 113.Optionally, the shadow
As sensing chip 13 and the processing chip 12 are fixed by glue-line, the glue-line is not shown in Fig. 1.
The cover board 14 can penetrate the light wave of default wave band.The image sensing chip 13 is used to sense the light wave,
Image information is formed based on the light wave.When the image sensing chip 13 is for when sensing visible light, the cover board to be transparent
Cover board, for penetrating visible light.When the image sensing chip 13 is for when sensing infrared light, the cover board 14 to be used for through red
Outer light.The cover board 14 is fixed by glue-line and package substrate 11.There is branch between the cover board 14 and the package substrate 11
Support part part 17, so that having default spacing between cover board 14 and package substrate 11.The support member 17 can be to bond admittedly
The glue-line of the fixed cover board 14 and the package substrate 11, the support member 17 can also be individual structural member, both sides point
Not She Zhi glue-line and cover board 14 and package substrate 11 be adhesively fixed.The cover board 14 can be lens, by the way that support portion is arranged
The thickness of part 17 can adjust the spacing, and then adjust distance of the cover board 14 relative to the image sensing chip 13, adjust
The focal length of image sensing chip 13.In order to improve default wave band light wave transmitance, reduction can be on the surface of the cover board
Antireflective film is set, and/or, in order to reduce the interference of other wave band light waves, can optical filter be set on the surface of the cover board, use
In the light wave for filtering out its all band, to improve image quality.The spacing is additionally operable to be adapted to the conducting wire 15.
As having default spacing between above-mentioned cover board 14 and package substrate 11, the space that the spacing generates can be utilized in institute
It states and integrates plug-in element in encapsulating structure.The plug-in element includes resistance, capacitance and inductance etc..When in the encapsulating structure
When being integrated with plug-in element, the first surface is additionally provided with the pad for binding the plug-in element, and the pad passes through
Wired circuit 114 and the connection of corresponding third contact jaw 115, in order to be connected with external circuit.
In order to increase the heat dissipation performance of encapsulating structure, the package substrate 11 has positioned at the first surface and described the
The heat-conducting layer is not shown in Fig. 1 in heat-conducting layer between two surfaces.That is, the package substrate 11 is stepped construction, lead
Thermosphere is between first surface and second surface.Heat-conducting layer can be ceramic material or the gold that insulate with the interconnection circuit
Belong to layer.The heat-conducting layer is used to heat being transmitted to the lateral surface of the package substrate 11 from the side wall of the receiving hole 111.This
Sample, on the one hand, the heat distributed when two chip operations can transmit in the longitudinal direction, be arrived by the backside radiator of processing chip 12
On the other hand the outside of encapsulating structure can in the horizontal be transmitted by the heat-conducting layer, pass through the lateral surface of package substrate 11
The outside of encapsulating structure is rejected heat to, therefore the encapsulating structure has preferable heat dissipation performance.
With reference to figure 2, Fig. 2 is the schematic diagram of the encapsulating structure of another chip provided in an embodiment of the present invention, the encapsulation knot
Structure is with Fig. 1 illustrated embodiment differences, further includes being arranged between the image sensing chip 13 and the receiving hole 11
Packing material 16 between gap.The packing material 16 can be colloid, be used for image sensing chip 13 and the receiving hole
111 side wall is fixed.The packing material 16 is additionally operable to fix the processing chip and the package substrate 11.The filling
Material 16 does not cover the front of the image sensing chip 13, in order to which the first weld pad 132 and the first contact jaw 112 connect, with
And in order to which the first functional unit 131 is photosensitive.Optionally, the packing material 16 replaces for thermal conductivity, laterally and vertical to increase
To heat dissipation.
In encapsulating structure described in the embodiment of the present invention, the size for being suitable for image sensing chip 13 is less than processing chip 12
The packaged type of size.Receiving hole 111 is completely covered in processing chip 12.
By foregoing description it is found that in encapsulating structure provided in an embodiment of the present invention, by package substrate 11 to handling core
Piece 12 and image sensing chip 13 are packaged, and processing chip 12 is bundled in the second surface of package substrate 11, image is passed
Sense chip 13 is arranged in the receiving hole 111 of package substrate, and the processing chip 12 and the image sensing chip 13 are logical
The interconnection circuit crossed on the package substrate 11 is connected with external circuit, on the one hand, by the processing chip 12 and the image
Sensing chip 13 is oppositely arranged, and reduces the area of encapsulating structure, on the other hand, real by the interconnection circuit in package substrate 11
The connection of existing chip and external circuit, interconnects convenient for circuit, convenient for further increasing the integrated level of chip.
Based on above-described embodiment, another embodiment of the present invention additionally provides a kind of packaging method, for making above-mentioned implementation
The example encapsulating structure, for the packaging method as shown in Fig. 3-Fig. 7, Fig. 3-Fig. 7 is a kind of encapsulation provided in an embodiment of the present invention
The flow diagram of method, the packaging method include：
Step S11：As shown in figure 3, providing a package substrate 11.
The package substrate includes opposite first surface and second surface；The package substrate is divided into multiple chips
Binding region has cutting raceway groove 100 between two neighboring chip bonding region；The chip bonding region 100 includes：Run through
The receiving hole 111 of the first surface and the second surface；The package substrate 11 also has interconnection circuit.One chip
Binding region is used to form an encapsulating structure.
The interconnection circuit includes：The first contact jaw 112 in the first surface is set, is arranged in the second surface
The second contact jaw 113 and third contact jaw 115, and the wired circuit 114 that is arranged in the package substrate 11, described
Three contact jaws 115 pass through described respectively for connecting external circuit, first contact jaw 112 and second contact jaw 113
Wired circuit 114 and the connection of the different third contact jaws 115.
Step S12：As shown in Figure 4 and Figure 5, processing chip 12 and image sensing core are bound in the chip bonding region
Piece 13.
In the step, binds processing chip 12 in the chip bonding region and image sensing chip 13 includes：By institute
It states processing chip 12 to connect with second contact jaw 113, the image sensing chip 13 and first contact jaw 112 is connected
It connects.
The processing chip 12 is bundled in the second surface, and covers the receiving hole 111 and be located at the second surface
Opening；The image sensing chip 13 is arranged in the receiving hole 111.
In the step, first, processing chip 12 and image sensing chip 13 are relatively fixed, processing chip 12 front and
13 back side of image sensing chip is relatively fixed.The image sensing chip 13 and the processing chip 12 are fixed by glue-line.
Then, as shown in figure 4, binding processing chip 12 in second surface, so that the processing chip 12 and described the
Two contact jaws 113 connect, and image sensing chip 13 is located in receiving hole 111.The processing chip 12 have opposite front and
The back side, front and the image sensing chip 13 are oppositely arranged, and front has the second functional unit 121 and with described the
Second weld pad 122 of two functional units 121 connection；It is described that the processing chip 12 is connect packet with second contact jaw 113
It includes：Second weld pad 122 and second contact jaw 113 are welded, or second weld pad 122 and described second are connect
Contravention 113 passes through conductive glue connection.
Finally, as shown in figure 5, image sensing chip 13 and the first contact jaw 112 are connected.In the embodiment of the present invention, institute
Stating image sensing chip 13, there is opposite front and back, the back side and the processing chip 12 to be oppositely arranged, positive mask
The first weld pad 132 for having the first functional unit 131 and being connected with the first functional unit 131.It is described by the image sensing core
Piece 13 connect with first contact jaw 112 including：First weld pad 132 and first contact jaw 112 are passed through into conducting wire
15 connections.
Alternatively, in the step, first can also bind processing chip 12 in second surface so that the processing chip 12 with
Second contact jaw 113 connects, then setting image sensing chip 13, the image sensing chip 13 in receiving hole 111
It is arranged on the surface of the processing chip 12, then image sensing chip 13 and the first contact jaw 112 is connected.
Alternatively, in the step, can also the first stabilized image sensing chip 13 in receiving hole 111, then tied up in second surface
Determine processing chip 12, then sensing chip 13 will be influenced and connected with interconnection circuit.
Step S13：As shown in fig. 6, cover board 14 is fixed in the first surface, it is described for the image sensing chip
13 are sealed protection.
Optionally, the surface of the cover board 14 is provided with optical filter and/or antireflective film.
Step S14：As shown in fig. 7, dividing the package substrate 11 based on the cutting raceway groove 100, multiple encapsulation are formed
Structure.
In the embodiment of the present invention, the front of the image sensing chip 13 is located in the receiving hole 111, and lower surface can
To be located in the receiving hole 111 or outside the receiving hole 111, that is to say, that the image sensing chip 13 can be with
It is fully located in the receiving hole 111, or part is located in the receiving hole 111.
By production method shown in Fig. 3-Fig. 7, encapsulating structure as shown in Figure 1 is ultimately formed.
It is the flow diagram of another packaging method provided in an embodiment of the present invention with reference to figure 8- Figure 11, Fig. 8-Figure 11,
The packaging method is with above-mentioned production method difference, further includes before the fixation cover board 14：In the image sensing core
The gap setting packing material 16 of piece 13 and the receiving hole 111.
First image sensing chip 13 and processing chip 12 can be relatively fixed, then two chips after fixation is default
Packing material is arranged in region, then as shown in figure 8, being fixed two chips and package substrate 11 by packing material 16, and makes
Second weld pad 122 and the connection of the second contact jaw 113.It is connect again as shown in figure 9, connecting the first weld pad 132 and first by conducting wire 15
Contravention 112, it is last as shown in figure 11 in as shown in Figure 10, fixed cover board 14, cover board 14 and envelope are divided based on cutting raceway groove 100
Substrate 11 is filled, multiple encapsulating structures as shown in Figure 2 are formed.
In the embodiment of the present invention, production method such as Figure 12-of the processing chip 12 and the image sensing chip 13
Shown in Figure 15, Figure 12-Figure 15 is a kind of production method flow chart of chip provided in an embodiment of the present invention, and this method includes：
First, as shown in Figure 12 and Figure 13, a wafer 43 is provided, Figure 13 is sectional drawings of the Figure 12 in the directions PP '.Wafer 43
With multiple chip units 42, there is cutting raceway groove 41, a chip unit to be used to form one between adjacent chips unit 42
Chip.There is chip unit opposite front and back, front to have functional unit 421 and weld pad 422.Optionally, described
The surface of wafer 43 also has protective layer 400, and 400 covering function unit 421 of protective layer, the region of corresponding weld pad 422, which has, opens
Mouthful in order to being bound with package substrate.
Then, as shown in figure 14, the wafer is divided based on the cutting raceway groove 41, forms chip as shown in figure 15.
By foregoing description it is found that in packaging method described in the embodiment of the present invention, by package substrate 11 to two chips
It is carried out at the same time encapsulation, it is simple for process.And chip is not necessarily to form back side interconnection architecture by TSV techniques, cost of manufacture is relatively low.And
The mechanical strength of encapsulating structure can be enhanced by the package substrate 11, chip can be carried out place is largely thinned
Reason, reduces the thickness of encapsulating structure.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.For being encapsulated disclosed in embodiment
For method, since it is corresponding with encapsulating structure disclosed in embodiment, so description is fairly simple, related place is referring to envelope
Assembling structure corresponding part illustrates.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest range caused.
Claims (20)
1. a kind of encapsulating structure of chip, which is characterized in that the encapsulating structure includes：
Package substrate, the package substrate opposite first surface and second surface；Through the first surface and described
The receiving hole of second surface；The package substrate also has interconnection circuit；
It is bundled in the processing chip of the second surface, the processing chip is covered in the receiving hole and is located at the second surface
Opening；
The image sensing chip being arranged in the receiving hole；
It is fixed on the cover board of the first surface, the cover board to the image sensing chip for being sealed protection；
Wherein, the processing chip is connect by the interconnection circuit with external circuit with the image sensing chip.
2. encapsulating structure according to claim 1, which is characterized in that the interconnection circuit includes：It is arranged described first
First contact jaw on surface is arranged the second contact jaw and third contact jaw in the second surface, and is arranged in the envelope
The wired circuit in substrate is filled, for connecting external circuit, first contact jaw and described second connect the third contact jaw
Contravention is connected by the wired circuit with the different third contact jaws respectively；
The image sensing chip is connect with first contact jaw；
The processing chip is connect with second contact jaw.
3. encapsulating structure according to claim 2, which is characterized in that the image sensing chip have opposite front and
The back side, the back side and the processing chip are oppositely arranged, and front has the first functional unit and connects with the first functional unit
The first weld pad connect, first weld pad are connect with first contact jaw.
4. encapsulating structure according to claim 3, which is characterized in that first weld pad passes through with first contact jaw
Conducting wire connects.
5. encapsulating structure according to claim 2, which is characterized in that the processing chip has opposite front and the back of the body
Face, front and the image sensing chip are oppositely arranged, and front has the function of the second functional unit and with described second
Second weld pad of unit connection, second weld pad are connect with second contact jaw.
6. encapsulating structure according to claim 5, which is characterized in that second weld pad is welded with second contact jaw
It connects or second weld pad passes through conductive glue connection with second contact jaw.
7. encapsulating structure according to claim 1, which is characterized in that the image sensing chip and the processing chip are logical
Glue-line is crossed to fix.
8. encapsulating structure according to claim 1, which is characterized in that have branch between the cover board and the package substrate
Support part part, the support member is for so that have default spacing between the cover board and the package substrate.
9. encapsulating structure according to claim 1, which is characterized in that between the image sensing chip and the receiving hole
There is packing material between gap.
10. encapsulating structure according to claim 1, which is characterized in that the package substrate, which has, is located at first table
Heat-conducting layer between face and the second surface, the heat-conducting layer are used to heat being transmitted to from the side wall of the receiving hole described
The lateral surface of package substrate.
11. encapsulating structure according to claim 1, which is characterized in that the surface of the cover board be provided with optical filter and/or
Antireflective film.
12. a kind of packaging method of chip, which is characterized in that the packaging method includes：
There is provided a package substrate, the package substrate includes opposite first surface and second surface；The package substrate is drawn
It is divided into multiple chip bonding regions, there is cutting raceway groove between two neighboring chip bonding region；The chip bonding region packet
It includes：Through the receiving hole of the first surface and the second surface；The package substrate also has interconnection circuit；
Processing chip and image sensing chip are bound in the chip bonding region；The processing chip is bundled in described second
Surface, and cover the opening that the receiving hole is located at the second surface；The image sensing chip is arranged in the receiving hole
It is interior；
Cover board is fixed in the first surface, it is described for being sealed protection to the image sensing chip；
Divide the package substrate based on the cutting raceway groove, forms multiple encapsulating structures.
13. packaging method according to claim 12, which is characterized in that the interconnection circuit includes：Setting is described the
First contact jaw on one surface is arranged the second contact jaw and third contact jaw in the second surface, and is arranged described
Wired circuit in package substrate, the third contact jaw is for connecting external circuit, first contact jaw and described second
Contact jaw is connected by the wired circuit with the different third contact jaws respectively；
It is described to include in chip bonding region binding processing chip and image sensing chip：By the processing chip and institute
The connection of the second contact jaw is stated, the image sensing chip is connect with first contact jaw.
14. packaging method according to claim 13, which is characterized in that described to be handled in chip bonding region binding
Chip and image sensing chip include：
The processing chip and the image sensing chip are relatively fixed；
The processing chip is bound in the second surface, so that the processing chip is connect with second contact jaw；
The image sensing chip is connect with first contact jaw.
15. packaging method according to claim 13, which is characterized in that described to be handled in chip bonding region binding
Chip and image sensing chip include：
The processing chip is bound in the second surface, so that the processing chip is connect with second contact jaw；
The image sensing chip is set in the receiving hole, and the table in the processing chip is arranged in the image sensing chip
Face；
The image sensing chip is connect with first contact jaw.
16. packaging method according to claim 13, which is characterized in that the image sensing chip has opposite front
And the back side, the back side and the processing chip are oppositely arranged, front have the first functional unit and with the first functional unit
First weld pad of connection；
It is described the image sensing chip is connect with first contact jaw including：First weld pad and described first are connect
Contravention is connected by conducting wire.
17. packaging method according to claim 13, which is characterized in that the processing chip has opposite front and the back of the body
Face, front and the image sensing chip are oppositely arranged, and front has the function of the second functional unit and with described second
Second weld pad of unit connection；
It is described the processing chip is connect with second contact jaw including：By second weld pad and second contact jaw
Welding, or second weld pad and second contact jaw are passed through into conductive glue connection.
18. packaging method according to claim 12, which is characterized in that the image sensing chip and the processing chip
It is fixed by glue-line.
19. packaging method according to claim 12, which is characterized in that the surface of the cover board be provided with optical filter and/
Or antireflective film.
20. packaging method according to claim 12, which is characterized in that further include：
Before the fixation cover board, in the gap setting packing material of the image sensing chip and the receiving hole.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810259146.6A CN108428690A (en) | 2018-03-27 | 2018-03-27 | A kind of encapsulating structure and packaging method of chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810259146.6A CN108428690A (en) | 2018-03-27 | 2018-03-27 | A kind of encapsulating structure and packaging method of chip |
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| CN108428690A true CN108428690A (en) | 2018-08-21 |
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| CN201810259146.6A Pending CN108428690A (en) | 2018-03-27 | 2018-03-27 | A kind of encapsulating structure and packaging method of chip |
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