CN108063126A - The encapsulating structure and method for packing of a kind of chip - Google Patents
The encapsulating structure and method for packing of a kind of chip Download PDFInfo
- Publication number
- CN108063126A CN108063126A CN201711469223.2A CN201711469223A CN108063126A CN 108063126 A CN108063126 A CN 108063126A CN 201711469223 A CN201711469223 A CN 201711469223A CN 108063126 A CN108063126 A CN 108063126A
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 238000012856 packing Methods 0.000 title claims abstract description 40
- 238000005520 cutting process Methods 0.000 claims description 23
- 229910000679 solder Inorganic materials 0.000 claims description 14
- 238000005538 encapsulation Methods 0.000 claims description 11
- 230000005611 electricity Effects 0.000 claims description 7
- 238000003466 welding Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 38
- 238000010586 diagram Methods 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 238000010411 cooking Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000011089 mechanical engineering Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Micromachines (AREA)
Abstract
The invention discloses the encapsulating structures and method for packing of a kind of chip, MEMS chip and asic chip are packaged using a dimensional packaged circuit board in technical solution of the present invention, the dimensional packaged circuit board has receiving hole, MEMS chip is bundled in the both sides of the receiving hole with asic chip respectively, MEMS chip is connected with asic chip by dimensional packaged circuit board, and pass through dimensional packaged circuit board and be connected with external circuit, realize circuit interconnection convenient for encapsulating structure and other electronic components.
Description
Technical field
The present invention relates to chip encapsulation technology field, more specifically, being related to encapsulating structure and the encapsulation of a kind of chip
Method.
Background technology
MEMS (Micro-Electro-Mechanical Systems, abbreviation MEMS) be by microelectric technique with
A kind of industrial technology that mechanical engineering is fused together, its opereating specification is in micron range.MEMS be it is a kind of it is brand-new must
The research and development field of a variety of physical field immixtures must be considered simultaneously, and compared with traditional machinery, they smaller is maximum
As soon as no more than centimetre in addition only several microns, thickness it is more small.Application-specific integrated circuit (Application
Specific Integrated Circuit, abbreviation ASIC), it is considered as that one kind sets for special purpose in integrated circuit circle
The integrated circuit of meter.The characteristics of ASIC is the demand towards specific user, ASIC in batch production with universal integrated circuit phase
Than having many advantages, such as that volume smaller, power consumption are lower, reliability improves, performance improves, confidentiality enhances, cost reduction.
The generation technique similar with integrated circuit may be employed in MEMS and ASIC, can largely using integrated circuit into
Cooking technique and technique carry out the production of high-volume, low cost, generate high performance MEMS chip and asic chip.MEMS cores
The encapsulating structure of the integral packaging of piece and asic chip opens a brand-new technical field and industry, based on the encapsulation knot
It is configured the microsensor made, microactrator, micro parts, Micromechanical Optics device, vacuum microelectronic device, power electronic devices
Have Deng in Aeronautics and Astronautics, automobile, biomedicine, environmental monitoring, military affairs and all spectra that almost people are touched
Very wide application prospect.
In the prior art, general MEMS chip and the encapsulating structure of asic chip are directly to pass through glue-line by the two is opposite
Fitting is fixed or is welded and fixed, and is not easy to it and other electronic components realize circuit interconnection.
The content of the invention
To solve the above-mentioned problems, the present invention provides the encapsulating structure and method for packing of a kind of chip, by MEMS cores
Piece is bundled in the both sides of the dimensional packaged circuit board with receiving hole with asic chip, and the two is connected by dimensional packaged circuit board, and is passed through
Dimensional packaged circuit board is connected with external circuit, and circuit interconnection is realized convenient for encapsulating structure and other electronic components.
To achieve these goals, the present invention provides following technical solution：
A kind of encapsulating structure of chip, the encapsulating structure include：
Dimensional packaged circuit board, the dimensional packaged circuit board have receiving hole；
Asic chip, the asic chip is bundled in the one side of the dimensional packaged circuit board, and covers the receiving hole；
MEMS chip, the MEMS chip is bundled in the opposite side of the dimensional packaged circuit board, and covers the receiving hole；Institute
MEMS chip is stated with opposite front and the back side, front has the first functional unit；The MEMS chip just faces
It is set to the receiving hole, first functional unit is oppositely arranged with the receiving hole；
Wherein, the dimensional packaged circuit board has wired circuit and the first connecting pin being connected with the wired circuit, institute
The first connecting pin is stated for being connected with external circuit；The asic chip and the MEMS chip connect with the wired circuit
It connects.
Preferably, in above-mentioned encapsulating structure, the MEMS chip further includes：Cover the envelope of first functional unit
Lid；
Wherein, the capping has chamber, and the opening of the chamber is oppositely arranged with first functional unit；The envelope
Lid is located in the receiving hole.
Preferably, in above-mentioned encapsulating structure, there is gap between the top surface of the capping and the asic chip.
Preferably, in above-mentioned encapsulating structure, the top surface of the capping is used to bind institute without departing from the dimensional packaged circuit board
The surface of asic chip is stated, the surface that the dimensional packaged circuit board is used to bind the MEMS chip is exposed in the bottom surface of the capping
Outside.
Preferably, in above-mentioned encapsulating structure, the dimensional packaged circuit board has opposite first surface with second surface；Institute
First surface is stated for binding the asic chip, the second surface is used to bind the MEMS chip.
Preferably, in above-mentioned encapsulating structure, there is gap between the asic chip and the MEMS chip.
Preferably, in above-mentioned encapsulating structure, the first surface has the first weld pad, and the second surface has second
Weld pad, first weld pad and second weld pad are connected with the wired circuit, and first connecting pin is located at described
Second surface；
The asic chip has second connection end, the second connection end and institute towards the surface of the dimensional packaged circuit board
State the connection of the first weld pad；
The front of the MEMS chip has the 3rd weld pad that be connected with first functional unit, the 3rd weld pad and
The second weld pad connection.
Preferably, in above-mentioned encapsulating structure, the asic chip has multiple second connection ends, the encapsulation electricity
Road plate has multiple the first weld pads to connect one to one with the second connection end；
The MEMS chip has multiple 3rd weld pads, and the dimensional packaged circuit board has multiple and the 3rd weld pad
Second weld pad to connect one to one.
Preferably, in above-mentioned encapsulating structure, the wired circuit includes：
First wired circuit, first wired circuit are used to connect first weld pad and second weld pad；
Second wired circuit, second wired circuit are used to connect first weld pad and second weld pad, and
It is connected with corresponding first connecting pin；
3rd wired circuit, the 3rd wired circuit for connecting the first weld pad or the second weld pad, and with it is corresponding
The first connecting pin connection.
Preferably, in above-mentioned encapsulating structure, the asic chip has opposite front and the back side, the ASIC cores
The back side of piece is set towards the first surface；
The 4th weldering that the front of the asic chip has the second functional unit and is connected with second functional unit
Pad；
The back side of the asic chip has the second connection end, and the second connection end connects with the 4th weld pad
It connects.
Preferably, in above-mentioned encapsulating structure, the back side of the asic chip has a through hole, and the through hole exposes described the
Four weld pads；
The back side of the asic chip is provided with insulating layer, and the insulating layer covers the side wall of the through hole, and extends to
The outside of the through hole；
The surface of insulating layer connects covered with wiring layer again, the wiring layer again and the 4th weld pad of the via bottoms
It connects, and extends to the outside of the through hole；
The surface covering solder mask of the wiring layer again, the region that the solder mask is located at outside the through hole, which has, opens
Mouthful, wiring layer, the second connection end are arranged on the opening again described in the opening exposing, and the second connection end passes through institute
Wiring layer is stated again to be connected with the 4th weld pad.
Preferably, in above-mentioned encapsulating structure, the second connection end is solder-bump.
Preferably, in above-mentioned encapsulating structure, first connecting pin is solder-bump.
The present invention also provides a kind of method for packing of chip, the method for packing includes：
A cutting board to be cut is provided, the cutting board to be cut has multiple chip bonding regions, the adjacent chip bonding
There is cutting raceway groove between region；Each chip bonding region has the receiving hole through the cutting board to be cut；It is described
Chip bonding region has wired circuit；
Asic chip is bound in the one side in the chip bonding region, the opposite side in the chip bonding region is bound
MEMS chip, the asic chip cover the receiving hole, and the MEMS chip covers the receiving hole；The MEMS chip tool
There are opposite front and the back side, front has the first functional unit；The MEMS chip just facing towards the receiving hole
It sets, first functional unit is oppositely arranged with the receiving hole；The asic chip and the MEMS chip are and institute
State wired circuit connection；
In the chip bonding region, towards setting, a side surface of the MEMS chip is formed and the wired circuit connects
The first connecting pin connect, first connecting pin are used to connect with external circuit；
The cutting board to be cut is split based on the cutting raceway groove, forms multiple dimensional packaged circuit boards, each encapsulation electricity
Road plate includes a binding region, is bound on each dimensional packaged circuit board described in an asic chip and one
MEMS chip.
Preferably, in above-mentioned method for packing, the MEMS chip further includes：Cover the envelope of first functional unit
Lid；
Wherein, the capping has chamber, and the opening of the chamber is oppositely arranged with first functional unit；The envelope
Lid is located in the receiving hole.
Preferably, in above-mentioned method for packing, there is gap between the top surface of the capping and the asic chip.
Preferably, in above-mentioned method for packing, the top surface of the capping is used to bind institute without departing from the dimensional packaged circuit board
The surface of asic chip is stated, the surface that the dimensional packaged circuit board is used to bind the MEMS chip is exposed in the bottom surface of the capping
Outside.
Preferably, in above-mentioned method for packing, the dimensional packaged circuit board has opposite first surface with second surface；Institute
First surface is stated for binding the asic chip, the second surface is used to bind the MEMS chip.
Preferably, in above-mentioned method for packing, there is gap between the asic chip and the MEMS chip.
Preferably, in above-mentioned method for packing, the first surface has the first weld pad, and the second surface has second
Weld pad, first weld pad and second weld pad are connected with the wired circuit, and first connecting pin is located at described
Second surface；The asic chip has second connection end towards the surface of the dimensional packaged circuit board；The MEMS chip is just
Face has the 3rd weld pad being connected with first functional unit；
Described to bind asic chip in the one side in the chip bonding region, the opposite side in the chip bonding region is tied up
Determining MEMS chip includes：The second connection end is connected with first weld pad, by the 3rd weld pad and the described second weldering
Pad connection.
Preferably, in above-mentioned method for packing, the asic chip has multiple second connection ends, the encapsulation electricity
Road plate has multiple the first weld pads to connect one to one with the second connection end；
The MEMS chip has multiple 3rd weld pads, and the dimensional packaged circuit board has multiple and the 3rd weld pad
Second weld pad to connect one to one.
Preferably, in above-mentioned method for packing, the wired circuit includes：
First wired circuit, first wired circuit are used to connect first weld pad and second weld pad；
Second wired circuit, second wired circuit are used to connect first weld pad and second weld pad, and
It is connected with corresponding first connecting pin；
3rd wired circuit, the 3rd wired circuit for connecting the first weld pad or the second weld pad, and with it is corresponding
The first connecting pin connection.
Preferably, in above-mentioned method for packing, the asic chip has opposite front and the back side, the ASIC cores
The back side of piece is set towards the first surface；The front of the asic chip has the second functional unit and with described second
4th weld pad of functional unit connection；The back side of the asic chip have the second connection end, the second connection end with
The 4th weld pad connection；
It is described the second connection end is connected with first weld pad including：By welding procedure, described second is connected
End is connect to weld with first weld pad.
Preferably, in above-mentioned method for packing, the back side of the asic chip has a through hole, and the through hole exposes described the
Four weld pads；
The back side of the asic chip is provided with insulating layer, and the insulating layer covers the side wall of the through hole, and extends to
The outside of the through hole；
Wiring layer, the wiring layer again and the 4th weld pad of the via bottoms connect again for the covering of the surface of insulating layer
It connects, and extends to the outside of the through hole；
The covering solder mask for connecting up layer surface again, the region that the solder mask is located at outside the through hole, which has, opens
Mouthful, wiring layer, the second connection end are arranged on the opening again described in the opening exposing, and the second connection end passes through institute
Wiring layer is stated again to be connected with the 4th weld pad.
Preferably, in above-mentioned method for packing, the second connection end is solder-bump.
Preferably, in above-mentioned method for packing, first connecting pin is solder-bump.
In the encapsulating structure and method for packing that are provided by foregoing description, technical solution of the present invention, using an envelope
Device, circuit board is packaged MEMS chip and asic chip, and the dimensional packaged circuit board has receiving hole, MEMS chip and ASIC
Chip is bundled in the both sides of the receiving hole respectively, and MEMS chip is connected with asic chip by dimensional packaged circuit board, and passes through envelope
Device, circuit board is connected with external circuit, and circuit interconnection is realized convenient for encapsulating structure and other electronic components.
Description of the drawings
It in order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention, for those of ordinary skill in the art, without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the structure diagram of a kind of MEMS chip and asic chip routine encapsulating structure；
Fig. 2 is the structure diagram of another MEMS chip and asic chip routine encapsulating structure；
Fig. 3 is a kind of structure diagram of the encapsulating structure of chip provided in an embodiment of the present invention；
Fig. 4 is the structure diagram of MEMS chip in encapsulating structure shown in Fig. 3；
Fig. 5 is the structure diagram of asic chip in encapsulating structure shown in Fig. 3；
Fig. 6-Fig. 9 is a kind of flow diagram of method for packing provided in an embodiment of the present invention；
Figure 10-Figure 13 is a kind of production method flow diagram of MEMS chip provided in an embodiment of the present invention；
Figure 14-Figure 21 is a kind of production method flow diagram of asic chip provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment belongs to the scope of protection of the invention.
With reference to figure 1, Fig. 1 is the structure diagram of a kind of MEMS chip and asic chip routine encapsulating structure, MEMS chip
10 and asic chip 20 by glue-line 11 be bonded fix, MEMS chip 10 front covered with capping 104,10 He of MEMS chip
Asic chip 20 is connected by conducting wire, which needs to be packaged MEMS chip 10 and conducting wire by injection structure 12 solid
It is fixed, it is necessary to thicker injection structure 12, and injection structure 12 needs to expose that 20 surface of asic chip reserves is used for and outside
The weld pad of circuit connection, the weld pad are used to be connected with external circuit by conducting wire.Which needs to connect two cores by conducting wire
Piece and by chip and external connection, while Shooting Technique is packaged, volume is larger, and routing connective stability is poor, makes
Cost is higher.
With reference to figure 2, Fig. 2 is the structure diagram of another MEMS chip and asic chip routine encapsulating structure, MEMS cores
The back side of piece 10 and the front of asic chip 20 are directly welded by welding ends, and the front of similary MEMS chip 10 is provided with capping
104.20 back side of asic chip has connecting pin 13, for being connected with external circuit.Connecting pin 13 passes through through hole and asic chip
20 positive welding ends connections.Which needs MEMS chip 10 consistent with the size of asic chip 20, MEMS chip 10
Size increase, integrated level is lower, and the high stage development trend that cost becomes higher and existing MEMS chip 10 is less and less is not
Meet.And which needs MEMS chip 10 and 20 upside-down mounting of asic chip to be electrically coupled, it is also necessary to which 20 back side of asic chip passes through
TSV techniques form connecting pin 13, and in order to be connected with external circuit, process complexity is larger, and cost is higher.
To solve the above-mentioned problems, an embodiment of the present invention provides a kind of MEMS chip and the encapsulating structure of asic chip,
MEMS chip and asic chip are packaged using a dimensional packaged circuit board, the dimensional packaged circuit board has receiving hole, MEMS cores
Piece is bundled in the both sides of the receiving hole with asic chip respectively, and MEMS chip is connected with asic chip by dimensional packaged circuit board,
And pass through dimensional packaged circuit board and be connected with external circuit, realize circuit interconnection convenient for encapsulating structure and other electronic components.The present invention
Encapsulating structure described in embodiment, manufacture craft is simple, low manufacture cost, and integrated level is high.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is described in further detail.
With reference to figure 3- Fig. 5, Fig. 3 be a kind of structure diagram of the encapsulating structure of chip provided in an embodiment of the present invention, Fig. 4
For the structure diagram of MEMS chip in encapsulating structure shown in Fig. 3, Fig. 5 is the structure of asic chip in encapsulating structure shown in Fig. 3
Schematic diagram, the encapsulating structure include：Dimensional packaged circuit board 30, the dimensional packaged circuit board 30 have receiving hole 301；Asic chip 20,
The asic chip 20 is bundled in the one side of the dimensional packaged circuit board 30, and covers the receiving hole 301；MEMS chip 10, institute
The opposite side that MEMS chip 10 is bundled in the dimensional packaged circuit board 30 is stated, and covers the receiving hole 301.
The MEMS chip 10 has opposite front 101 and the back side 102, and front 101 has the first functional unit
103；The front 101 of the MEMS chip 10 is set towards the receiving hole 301, first functional unit 103 and the appearance
Receiving hole 301 is oppositely arranged.
Wherein, the first company that the dimensional packaged circuit board 30 has wired circuit 307 and is connected with the wired circuit 307
End 21 is connect, first connecting pin 21 is used to connect with external circuit；The asic chip 20 and the MEMS chip 10 are equal
It is connected with the wired circuit 307.
Optionally, the MEMS chip 10 further includes：Cover the capping 104 of first functional unit 103；Wherein, institute
Stating capping 104 has chamber Q, and the opening of the chamber Q is oppositely arranged with first functional unit 103；The capping 104
In in the receiving hole 301.It is multiplexed the receiving hole 301 and the capping 104 is set, first functional unit 103 is carried out
Protection will not additionally increase the thickness of encapsulating structure.The front 101 of the MEMS chip 10 covers matcoveredn 400, protective layer
400 the first functional units 103 of covering, on the one hand protect first functional unit 103, on the other hand ensure its front
101 planarization is bonded fixation convenient for the front of the MEMS chip 10 with dimensional packaged circuit board 20.
There is gap between the top surface of the capping 104 and the asic chip 20, in order in dimensional packaged circuit board 30
The asic chip 20 and the MEMS chip 10 are bound respectively in both sides.The top surface of the capping 104 is without departing from the encapsulation electricity
Road plate 30 is used to bind the surface of the asic chip 20, can be generated to avoid top surface and asic chip 20 contact of capping 104
The dimensional packaged circuit board 30 is exposed for binding outside the surface of the MEMS chip 10 in stress, the bottom surface of the capping 104, so as to
It is bound in MEMS chip 10 and dimensional packaged circuit board 30.
The dimensional packaged circuit board 30 has opposite first surface 303 with second surface 304；The first surface 303 is used
In binding the asic chip 20, the second surface 304 is used to bind the MEMS chip 10.The two of dimensional packaged circuit board 30
After asic chip 20 and MEMS chip 10 are bound in a surface respectively, have between the asic chip 20 and the MEMS chip 10
Gap.
The first surface 303 has the first weld pad 305, and the second surface 304 has the second weld pad 306, and described the
One weld pad 305 and second weld pad 306 are connected with the wired circuit 307, and first connecting pin 21 is located at described
Second surface 304.The asic chip 20 has a second connection end 201 towards the surface of the dimensional packaged circuit board 30, and described the
Two connecting pins 201 are connected with first weld pad 305；The front 101 of the MEMS chip 10 has the function of and first list
3rd weld pad 105 of 103 connection of member, the 3rd weld pad 105 are connected with second weld pad 306.
The asic chip 20 has multiple second connection ends 201, and the dimensional packaged circuit board 30 has multiple with described the
The first weld pad 305 that two connecting pins 201 connect one to one；The MEMS chip 10 has multiple 3rd weld pads 105, institute
Stating dimensional packaged circuit board 30 has multiple second weld pads 306 to connect one to one with the 3rd weld pad 105.
In the dimensional packaged circuit board, the wired circuit 307 includes：First wired circuit, first wired circuit are used
In connection first weld pad 305 and second weld pad 201；Second wired circuit, second wired circuit are used to connect
First weld pad 305 and second weld pad 201 are connect, and is connected with corresponding first connecting pin 21；3rd wiring
Circuit, the 3rd wired circuit connect for connecting the first weld pad 305 or the second weld pad 306 with corresponding described first
Connect 21 connection of end.
The asic chip 20 has opposite front 202 and the back side 203,203 court of the back side of the asic chip 20
It is set to the first surface 303；The front 202 of the asic chip 20 has the second functional unit 204 and with described the
4th weld pad 205 of two functional units 204 connection；The back side 203 of the asic chip 20 has the second connection end 201,
The second connection end 201 is connected with the 4th weld pad 205.
The back side 203 of the asic chip 20 has through hole 206, and the through hole 206 exposes the 4th weld pad 205；Institute
The back side 203 for stating asic chip 20 is provided with insulating layer 207, and the insulating layer covers the side wall of the 207 lids through hole 206, and prolongs
Extend the outside of the through hole 206；The surface of the insulating layer 207 covers wiring layer 208 again, the wiring layer again 208 and institute
The 4th weld pad 205 for stating 206 bottom of through hole connects, and extends to the outside of the through hole 206；It covers on the surface of the wiring layer again
Lid solder mask 209, the region that the solder mask 209 is located at outside the through hole 206 has opening, described to be open described in exposing again
Wiring layer 208, the second connection end 201 are arranged on the opening, and the second connection end 201 passes through the wiring layer again
208 are connected with the 4th weld pad 205.Optionally, the front 202 of the asic chip 20 covers matcoveredn 300, the guarantor
Sheath 300 covers second functional unit 204 and the 4th weld pad 205, on the one hand, can by the protective layer 300
To protect 202 and the 4th weld pad 205 of the second functional unit, on the other hand, it is ensured that the table of the asic chip 20
Face has preferable flatness, is fixed in order to be bonded with other structures part.
In encapsulating structure described in the embodiment of the present invention, the second connection end 201 is solder-bump.First connecting pin
21 be solder-bump.In the embodiment of the present invention, the solder-bump can be tin ball or metal coupling.
The front 101 of the MEMS chip 10 has multiple the 3rd weld pads 105 being connected with the first functional unit 103, right
The second surface 304 in dimensional packaged circuit board 30 answered has multiple the second weld pads being used for and the 3rd weld pad 105 is correspondingly connected with
306.Multiple the 4th weld pads 205 being connected with the second functional unit 204 in front of the asic chip 20, it is corresponding in encapsulation electricity
The first surface 303 of road plate 30 has multiple the first weld pads 305 being used for and the 4th weld pad 205 is correspondingly connected with.It welds part first
Pad 305 and/or the second weld pad of part 306 can pass through individual 3rd wired circuit and corresponding first connecting pin respectively
21 connections.The first weld pad of part 305 can be connected by wired circuit with corresponding second weld pad 306.The first weld pad of part
305 can be connected by wired circuit with corresponding second weld pad 306, and be connected with corresponding first connecting pin 21.
Optionally, the first surface 303 of the dimensional packaged circuit board 30 further includes the 3rd be connected with the interconnection circuit 307
Connecting pin (not shown), the 3rd connecting pin are used to bind plug-in element (not shown).The plug-in element bag
Include one in resistive element, capacity cell, inductance element and memory component or multiple.Envelope described in the embodiment of the present invention
In assembling structure, plug-in element can be bound by dimensional packaged circuit board 30, the envelope being multiplexed between MEMS chip 10 and asic chip 20
Device, circuit board integrates appearance element, and plug-in element will not increase the thickness of encapsulating structure, and improve integrated level.
It is right using a dimensional packaged circuit board 30 in encapsulating structure provided in an embodiment of the present invention by foregoing description
MEMS chip 10 is packaged with asic chip 20, and the dimensional packaged circuit board 30 has receiving hole 301, MEMS chip 10 and ASIC
Chip 20 is bundled in the both sides of the receiving hole respectively, and MEMS chip 10 is connected with asic chip 20 by dimensional packaged circuit board 30,
And pass through dimensional packaged circuit board 30 and be connected with external circuit, realize circuit interconnection convenient for encapsulating structure and other electronic components.This hair
Encapsulating structure described in bright embodiment, manufacture craft is simple, low manufacture cost, and integrated level is high.
Based on above-described embodiment, another embodiment of the present invention additionally provides a kind of method for packing of chip, for making
Encapsulating structure is stated, for the method for packing as shown in Fig. 6-Fig. 9, Fig. 6-Fig. 9 is a kind of method for packing provided in an embodiment of the present invention
Flow diagram, the method for packing includes：
Step S11：As described in Figure 6, a cutting board 41 to be cut is provided.
The cutting board to be cut 41 has multiple chip bonding regions 42, has between the adjacent chip bonding region 42
Cut raceway groove 43；Each chip bonding region 42 has the receiving hole 301 through the cutting board 41 to be cut；The chip
Binding region 42 has wired circuit 307.
The cutting board to be cut 41 forms above-mentioned dimensional packaged circuit board 30 for cutting, and each chip bonding region 42 corresponds to shape
Into the dimensional packaged circuit board 30 of an encapsulating structure.
Step S12：As described in Figure 7, asic chip 20 is bound in the one side in the chip bonding region 42, in the chip
The opposite side binding MEMS chip 10 of binding region.The sequencing of two kinds of chip bondings can be set according to demand, the present invention
This is not especially limited in embodiment.
The asic chip 20 covers the receiving hole 301, and the MEMS chip 10 covers the receiving hole 301.
Fig. 4 of above-described embodiment is can refer to, the MEMS chip 10 has opposite front 101 and the back side 102, just
Face 101 has the first functional unit 103；The MEMS chip 10 is just set facing towards the receiving hole 301, first work(
Energy unit 103 is oppositely arranged with the receiving hole 301；The asic chip 20 and the MEMS chip 10 with the wiring
Circuit 307 connects.
Optionally, the MEMS chip 10 further includes：Cover the capping 104 of first functional unit 103；Wherein, institute
Stating capping 104 has chamber Q, and the opening of the chamber Q is oppositely arranged with first functional unit 103；The capping 104
In in the receiving hole 301.There is gap between the top surface of the capping 104 and the asic chip 20.
Step S13：As described in Figure 8, in the chip bonding region 42 towards the one side table for setting the MEMS chip 10
Face forms the first connecting pin 21 being connected with the wired circuit 307, and first connecting pin 21 is used to connect with external circuit.
Step S14：As described in Figure 9, the cutting board to be cut 41 is split based on the cutting raceway groove 43, forms multiple encapsulation
Circuit board 30, each dimensional packaged circuit board 30 include a binding region 42, are tied up on each dimensional packaged circuit board 30
A fixed asic chip 20 and a MEMS chip 10.
Optionally, the top surface of the capping 104 is used to bind the asic chip 20 without departing from the dimensional packaged circuit board 30
Surface, the dimensional packaged circuit board 30 is exposed for binding outside the surface of the MEMS chip 10 in the bottom surface of the capping 104.
Optionally, the dimensional packaged circuit board 30 has opposite first surface 303 with second surface 304；First table
For binding the asic chip 20, the second surface 304 is used to bind the MEMS chip 10 in face 303.The ASIC cores
There is gap between piece 20 and the MEMS chip 10.
The first surface 303 has the first weld pad 305, and the second surface 304 has the second weld pad 306, and described the
One weld pad 305 and second weld pad 306 are connected with the wired circuit 307, and first connecting pin 21 is located at described
Second surface 304；The asic chip 20 has second connection end 201 towards the surface of the dimensional packaged circuit board 30；It is described
The front 101 of MEMS chip 10 has the 3rd weld pad 105 being connected with first functional unit 103.It is described in the chip
The one side binding asic chip 20 of binding region 42, the opposite side binding MEMS chip 10 in the chip bonding region 42 wrap
It includes：The second connection end 201 is connected with first weld pad 305, by the 3rd weld pad 105 and second weld pad
306 connections.
The method for packing further includes：Before the cutting board 41 to be cut is cut, used in the chip bonding region 42
Plug-in element is bound in the surface of binding asic chip 20.The surface has the 3rd connecting pin being connected with interconnection circuit 307, uses
In the binding plug-in element.
The asic chip 20 has multiple second connection ends 201, and the dimensional packaged circuit board 30 has multiple and institute
State the first weld pad 305 that second connection end 201 connects one to one；The MEMS chip 10 has multiple 3rd weld pads
105, the dimensional packaged circuit board 30 has multiple second weld pads 106 to connect one to one with the 3rd weld pad 105.Institute
Stating wired circuit 307 includes：First wired circuit, first wired circuit are used to connect first weld pad 305 and institute
State the second weld pad 306；Second wired circuit, second wired circuit is for connecting first weld pad 305 and described the
Two weld pads 306, and connected with corresponding first connecting pin 21；3rd wired circuit, the 3rd wired circuit are used to connect
The first weld pad 305 or the second weld pad 306 are connect, and is connected with corresponding first connecting pin 21.
As shown in above-described embodiment Fig. 5, the asic chip 20 has opposite front 202 and the back side 203, described
The back side 203 of asic chip 20 is set towards the first surface 303；The front 202 of the asic chip 20 has the second work(
Energy unit 204 and the 4th weld pad 205 being connected with second functional unit 204；The back side 203 of the asic chip 20 has
There is the second connection end 201, the second connection end 201 is connected with the 4th weld pad 205；It is described to be connected described second
End 201 be connected with first weld pad 305 including：By welding procedure, by the second connection end 201 and first weld pad
305 welding, so that the second functional unit 204 is connected with the interconnection circuit 307 in the encapsulated circuit 30.
The back side 203 of the asic chip 20 has through hole 206, and the through hole 206 exposes the 4th weld pad 205；Institute
The back side 203 for stating asic chip 20 is provided with insulating layer 207, and the insulating layer covers the side wall of the 207 lids through hole 206, and prolongs
Extend the outside of the through hole 206；The surface of the insulating layer 207 covers wiring layer 208 again, the wiring layer again 208 and institute
The 4th weld pad 205 for stating 206 bottom of through hole connects, and extends to the outside of the through hole 206；It covers on the surface of the wiring layer again
Lid solder mask 209, the region that the solder mask 209 is located at outside the through hole 206 has opening, described to be open described in exposing again
Wiring layer 208, the second connection end 201 are arranged on the opening, and the second connection end 201 passes through the wiring layer again
208 are connected with the 4th weld pad 205.Optionally, the front 202 of the asic chip 20 covers matcoveredn 300, the guarantor
Sheath 300 covers second functional unit 204 and the 4th weld pad 205.
Optionally, the second connection end 201 is solder-bump.First connecting pin 21 is solder-bump.The present invention
In embodiment, the solder-bump can be tin ball or metal coupling.
With reference to the production method flow that figure 10- Figure 13, Figure 10-Figure 13 are a kind of MEMS chip provided in an embodiment of the present invention
Schematic diagram, the production method include：
Step S21：As shown in Figure 10 and Figure 11, a wafer 100 is provided, the wafer 100 includes multiple MEMS chips 10,
There is cutting raceway groove 51 between adjacent MEMS chip.Wherein, Figure 10 is the front plan view of wafer 100, and Figure 11 is Figure 10 in P-
The sectional drawing of P '.
The front covering matcoveredn 400 of wafer 100, protective layer 400 cover each 10 positive first work(of MEMS chip
Energy unit 103, the first functional unit 103 are connected with the 3rd weld pad 105.
Step S22：As shown in figure 12, the surface that each MEMS chip 10 is corresponded in the front of wafer 100 sets capping
104, covering 104 has chamber Q.
Step S23：As shown in figure 13, the wafer 100 is split based on cutting raceway groove 51, forms multiple MEMS chips 10.
With reference to the production method flow that figure 14- Figure 21, Figure 14-Figure 21 are a kind of asic chip provided in an embodiment of the present invention
Schematic diagram, the production method include：
Step S31：As shown in Figure 14 and Figure 15, a wafer 200 is provided, the wafer 200 includes multiple asic chips 20,
There is cutting raceway groove 61 between adjacent asic chip 20.Wherein, Fig. 4 is the front plan view of wafer 100, and Figure 15 is Figure 14 in Q-
The sectional drawing of Q '.
The front covering matcoveredn 300 of wafer 200, protective layer 300 cover each 20 positive second work(of asic chip
It can 204 and the 4th weld pad 205 of unit.
Step S32：As shown in figure 16, wafer 200 is inverted, 63 surface of loading plate, wafer is fixed on by adhesive layer 62
200 back side is set upward.
Step S33：As shown in figure 17, through hole 206 is formed at the back side of the wafer 200, for exposing asic chip 20
Positive 4th weld pad 205.Before through hole 206 is formed reduction processing can be carried out in advance to the back side of wafer 200.Through hole
206 can be straight hole, double step through hole or trapezoidal hole.
Step S34：As shown in figure 18, insulating layer 207 is formed at the back side of the wafer 200, insulating layer 207 covers through hole
206 side wall, and expose the bottom of through hole 206.
Step S35：As shown in figure 19, wiring layer 208 again are formed on 207 surface of insulating layer.Wiring layer 208 is logical again
206 bottom of hole is connected with the 4th weld pad 205.
Step S36：As shown in figure 20, solder mask 209 is formed on 208 surface of wiring layer again, solder mask 209 is located at logical
Region outside hole 206 has opening.
Step S37：As shown in figure 21, second connection end 201 is formed in the opening.
By foregoing description, method for packing described in the embodiment of the present invention can be used for making envelope described in above-described embodiment
Assembling structure, without plastic package process, process is simple, low manufacture cost, using a dimensional packaged circuit board 30 to MEMS chip 10 with
Asic chip 20 is packaged, and the dimensional packaged circuit board 30 has receiving hole 301, and MEMS chip 10 is tied up respectively with asic chip 20
The both sides of the receiving hole are scheduled on, MEMS chip 10 is connected with asic chip 20 by dimensional packaged circuit board 30, and passes through encapsulation electricity
Road plate 30 is connected with external circuit, and circuit interconnection is realized convenient for encapsulating structure and other electronic components.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.For device disclosed in embodiment
For, since it is corresponded to the methods disclosed in the examples, so description is fairly simple, related part is said referring to method part
It is bright.
The foregoing description of the disclosed embodiments enables professional and technical personnel in the field to realize or use the present invention.
A variety of modifications of these embodiments will be apparent for those skilled in the art, it is as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and the principles and novel features disclosed herein phase one
The most wide scope caused.
Claims (26)
1. a kind of encapsulating structure of chip, which is characterized in that the encapsulating structure includes：
Dimensional packaged circuit board, the dimensional packaged circuit board have receiving hole；
Asic chip, the asic chip is bundled in the one side of the dimensional packaged circuit board, and covers the receiving hole；
MEMS chip, the MEMS chip is bundled in the opposite side of the dimensional packaged circuit board, and covers the receiving hole；It is described
MEMS chip has opposite front and the back side, and front has the first functional unit；The MEMS chip just facing towards
The receiving hole is set, and first functional unit is oppositely arranged with the receiving hole；
Wherein, the dimensional packaged circuit board has wired circuit and the first connecting pin that is connected with the wired circuit, and described the
One connecting pin is used to connect with external circuit；The asic chip and the MEMS chip are connected with the wired circuit.
2. encapsulating structure according to claim 1, which is characterized in that the MEMS chip further includes：Cover described first
The capping of functional unit；
Wherein, the capping has chamber, and the opening of the chamber is oppositely arranged with first functional unit；The capping position
In in the receiving hole.
3. encapsulating structure according to claim 2, which is characterized in that between the top surface of the capping and the asic chip
With gap.
4. encapsulating structure according to claim 2, which is characterized in that the top surface of the capping is without departing from the encapsulated circuit
Plate is used to bind the surface of the asic chip, and the dimensional packaged circuit board is exposed for binding the MEMS in the bottom surface of the capping
Outside the surface of chip.
5. encapsulating structure according to claim 1, which is characterized in that the dimensional packaged circuit board has opposite first surface
With second surface；For binding the asic chip, the second surface is used to bind the MEMS chip first surface.
6. encapsulating structure according to claim 5, which is characterized in that have between the asic chip and the MEMS chip
There is gap.
7. encapsulating structure according to claim 5, which is characterized in that the first surface has the first weld pad, and described the
Two surfaces have the second weld pad, and first weld pad and second weld pad are connected with the wired circuit, and described first
Connecting pin is located at the second surface；
The asic chip has second connection end, the second connection end and described the towards the surface of the dimensional packaged circuit board
One weld pad connects；
The front of the MEMS chip has the 3rd weld pad that is connected with first functional unit, the 3rd weld pad with it is described
Second weld pad connects.
8. encapsulating structure according to claim 7, which is characterized in that the asic chip has multiple second connections
End, the dimensional packaged circuit board have multiple the first weld pads to connect one to one with the second connection end；
The MEMS chip has multiple 3rd weld pads, and the dimensional packaged circuit board has multiple and the 3rd weld pad one by one
Second weld pad being correspondingly connected with.
9. encapsulating structure according to claim 7, which is characterized in that the wired circuit includes：
First wired circuit, first wired circuit are used to connect first weld pad and second weld pad；
Second wired circuit, second wired circuit for connecting first weld pad and second weld pad, and with it is right
First connecting pin connection answered；
3rd wired circuit, the 3rd wired circuit for connecting the first weld pad or the second weld pad, and with it is corresponding described
First connecting pin connects.
10. encapsulating structure according to claim 7, which is characterized in that the asic chip have opposite front and
The back side, the back side of the asic chip are set towards the first surface；
The front of the asic chip has the second functional unit and the 4th weld pad being connected with second functional unit；
The back side of the asic chip has the second connection end, and the second connection end is connected with the 4th weld pad.
11. encapsulating structure according to claim 10, which is characterized in that the back side of the asic chip has through hole, institute
It states through hole and exposes the 4th weld pad；
The back side of the asic chip is provided with insulating layer, and the insulating layer covers the side wall of the through hole, and extends to described
The outside of through hole；
The surface of insulating layer is connected covered with wiring layer again, the wiring layer again with the 4th weld pad of the via bottoms, and
Extend to the outside of the through hole；
The surface covering solder mask of the wiring layer again, the region that the solder mask is located at outside the through hole has opening, institute
State opening expose described in wiring layer again, the second connection end is arranged on the opening, the second connection end by it is described again
Wiring layer is connected with the 4th weld pad.
12. encapsulating structure according to claim 7, which is characterized in that the second connection end is solder-bump.
13. encapsulating structure according to claim 1, which is characterized in that first connecting pin is solder-bump.
14. a kind of method for packing of chip, which is characterized in that the method for packing includes：
A cutting board to be cut is provided, the cutting board to be cut has multiple chip bonding regions, the adjacent chip bonding region
Between have cutting raceway groove；Each chip bonding region has the receiving hole through the cutting board to be cut；The chip
Binding region has wired circuit；
Asic chip is bound in the one side in the chip bonding region, the opposite side in the chip bonding region binds MEMS cores
Piece, the asic chip cover the receiving hole, and the MEMS chip covers the receiving hole；The MEMS chip has opposite
Front and the back side, front have the first functional unit；The MEMS chip is just set facing towards the receiving hole, institute
The first functional unit is stated to be oppositely arranged with the receiving hole；The asic chip and the MEMS chip are electric with the wiring
Road connects；
Form what is be connected with the wired circuit in a side surface of the chip bonding region towards the setting MEMS chip
First connecting pin, first connecting pin are used to connect with external circuit；
The cutting board to be cut is split based on the cutting raceway groove, forms multiple dimensional packaged circuit boards, each dimensional packaged circuit board
Including a binding region, an asic chip and a MEMS are bound on each dimensional packaged circuit board
Chip.
15. method for packing according to claim 14, which is characterized in that the MEMS chip further includes：Cover described
The capping of one functional unit；
Wherein, the capping has chamber, and the opening of the chamber is oppositely arranged with first functional unit；The capping position
In in the receiving hole.
16. method for packing according to claim 15, which is characterized in that the top surface of the capping and the asic chip it
Between have gap.
17. method for packing according to claim 15, which is characterized in that the top surface of the capping is without departing from the encapsulation electricity
Road plate is used to bind the surface of the asic chip, and the bottom surface exposing dimensional packaged circuit board of the capping is described for binding
Outside the surface of MEMS chip.
18. method for packing according to claim 14, which is characterized in that the dimensional packaged circuit board has the first opposite table
Face is with second surface；For binding the asic chip, the second surface is used to bind the MEMS cores first surface
Piece.
19. method for packing according to claim 18, which is characterized in that between the asic chip and the MEMS chip
With gap.
20. method for packing according to claim 18, which is characterized in that the first surface has the first weld pad, described
Second surface has the second weld pad, and first weld pad and second weld pad be connected with the wired circuit, and described the
One connecting pin is located at the second surface；The asic chip has second connection end towards the surface of the dimensional packaged circuit board；
The front of the MEMS chip has the 3rd weld pad being connected with first functional unit；
Described to bind asic chip in the one side in the chip bonding region, the opposite side in the chip bonding region is bound
MEMS chip includes：The second connection end is connected with first weld pad, by the 3rd weld pad and second weld pad
Connection.
21. method for packing according to claim 20, which is characterized in that the asic chip has multiple described second to connect
End is connect, the dimensional packaged circuit board has multiple the first weld pads to connect one to one with the second connection end；
The MEMS chip has multiple 3rd weld pads, and the dimensional packaged circuit board has multiple and the 3rd weld pad one by one
Second weld pad being correspondingly connected with.
22. method for packing according to claim 20, which is characterized in that the wired circuit includes：
First wired circuit, first wired circuit are used to connect first weld pad and second weld pad；
Second wired circuit, second wired circuit for connecting first weld pad and second weld pad, and with it is right
First connecting pin connection answered；
3rd wired circuit, the 3rd wired circuit for connecting the first weld pad or the second weld pad, and with it is corresponding described
First connecting pin connects.
23. method for packing according to claim 20, which is characterized in that the asic chip have opposite front and
The back side, the back side of the asic chip are set towards the first surface；The front of the asic chip has the function of the second list
Member and the 4th weld pad being connected with second functional unit；The back side of the asic chip has the second connection end,
The second connection end is connected with the 4th weld pad；
It is described the second connection end is connected with first weld pad including：By welding procedure, by the second connection end
It is welded with first weld pad.
24. method for packing according to claim 23, which is characterized in that the back side of the asic chip has through hole, institute
It states through hole and exposes the 4th weld pad；
The back side of the asic chip is provided with insulating layer, and the insulating layer covers the side wall of the through hole, and extends to described
The outside of through hole；
Wiring layer, the wiring layer again are connected with the 4th weld pad of the via bottoms again for the covering of the surface of insulating layer, and
Extend to the outside of the through hole；
The covering solder mask for connecting up layer surface again, the region that the solder mask is located at outside the through hole have opening, institute
State opening expose described in wiring layer again, the second connection end is arranged on the opening, the second connection end by it is described again
Wiring layer is connected with the 4th weld pad.
25. method for packing according to claim 20, which is characterized in that the second connection end is solder-bump.
26. method for packing according to claim 14, which is characterized in that first connecting pin is solder-bump.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711469223.2A CN108063126A (en) | 2017-12-29 | 2017-12-29 | The encapsulating structure and method for packing of a kind of chip |
| US16/211,090 US20190202685A1 (en) | 2017-12-29 | 2018-12-05 | Chip package and chip packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711469223.2A CN108063126A (en) | 2017-12-29 | 2017-12-29 | The encapsulating structure and method for packing of a kind of chip |
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| CN108063126A true CN108063126A (en) | 2018-05-22 |
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| CN201711469223.2A Pending CN108063126A (en) | 2017-12-29 | 2017-12-29 | The encapsulating structure and method for packing of a kind of chip |
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| CN111377390A (en) * | 2018-12-27 | 2020-07-07 | 中芯集成电路（宁波）有限公司上海分公司 | MEMS packaging structure and manufacturing method thereof |
| CN111377390B (en) * | 2018-12-27 | 2023-04-07 | 中芯集成电路（宁波）有限公司上海分公司 | MEMS packaging structure and manufacturing method thereof |
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