WO2007088757A1 - Memory card and memory card manufacturing method - Google Patents

Memory card and memory card manufacturing method Download PDF

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Publication number
WO2007088757A1
WO2007088757A1 PCT/JP2007/051055 JP2007051055W WO2007088757A1 WO 2007088757 A1 WO2007088757 A1 WO 2007088757A1 JP 2007051055 W JP2007051055 W JP 2007051055W WO 2007088757 A1 WO2007088757 A1 WO 2007088757A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
semiconductor chip
memory card
chip
card according
Prior art date
Application number
PCT/JP2007/051055
Other languages
French (fr)
Japanese (ja)
Inventor
Hidenobu Nishikawa
Hiroyuki Yamada
Shuichi Takeda
Atsunobu Iwamoto
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to CN2007800031807A priority Critical patent/CN101375299B/en
Priority to JP2007556823A priority patent/JP4946872B2/en
Priority to US12/160,960 priority patent/US7933127B2/en
Publication of WO2007088757A1 publication Critical patent/WO2007088757A1/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5388Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06572Auxiliary carrier between devices, the carrier having an electrical connection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01087Francium [Fr]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09072Hole or recess under component or special relationship between hole and component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10515Stacked components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip

Definitions

  • the present invention relates to a memory card and a manufacturing method thereof.
  • a memory card incorporating a memory chip is known as one of recording media for recording information. Since memory cards are excellent in portability, they are widely used as recording media for portable electronic devices such as portable information terminals and mobile phones. These portable electronic devices have the viewpoint of improving portability, etc. The miniaturization and large capacity have been promoted year by year, and accordingly, further miniaturization of memory cards and large capacity have been required. Usually, memory cards are required to have a large capacity while satisfying the standards because their shape, size, thickness, etc. are defined by the standards.
  • a plurality of memory substrates on which memory chips are mounted are stacked and mounted on one surface of the base substrate, and a control chip for controlling the operation of the memory chip is mounted on the other surface, thereby providing a memory.
  • a technique for increasing the capacity of a card is disclosed (for example, see Patent Document 1).
  • the memory chip and the control chip are mounted on the lead frame by wire bonding. Therefore, it is necessary to seal each chip carrier, lead frame, etc. with a thermosetting resin after mounting. At this time, since a thick sealing layer that sufficiently covers the memory chip and wires is required, the memory card can be downsized. There is a limit to thinning. In addition, since a sealing step is required separately from the mounting step, there is a limit to reducing the manufacturing cost. In addition, the quality of each chip can be checked only after it has been mounted on the S lead frame with full chip strength. For this reason, when mounting defects occur in some chips, the defects cannot be detected until the mounting of the remaining chips is completed, increasing the production cost.
  • Patent Document 1 Japanese Patent Laid-Open No. 2003-108963
  • Patent Document 2 JP 2004-13738 A
  • a memory card of the present invention includes a first circuit board, a first semiconductor chip mounted on the upper surface of the first circuit board, and a partial region of the lower surface facing the first circuit board; A second circuit board in which the lower surface of the first circuit board is bonded to the upper surface; and a second circuit board that is mounted on the upper surface of the second circuit board and at least a part other than a partial region of the lower surface of the first semiconductor chip.
  • the first and second semiconductor chips can be stacked without being sandwiched between the first and second semiconductor chips, so that the memory card can be reduced in size and thickness.
  • the method of manufacturing a memory card of the present invention includes: a) a step of mounting only a partial region of the lower surface of the first semiconductor chip on the upper surface of the first circuit board so as to face the first circuit board; B) mounting the second semiconductor chip on the upper surface of the second circuit board; and c) at least a part of the second semiconductor chip other than a part of the lower surface of the first semiconductor chip. And d) covering the first semiconductor chip and the first circuit board and the second semiconductor chip with a cover on the upper surface side of the second circuit board. Includes steps and.
  • a memory card can be manufactured with high productivity by a simple method as well as downsizing and thinning.
  • FIG. 1 is a plan view showing a configuration of a memory card according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along the line 2-2 in FIG.
  • FIG. 3A is a flowchart of the method for manufacturing the memory card according to the first embodiment of the present invention.
  • FIG. 3B is a flowchart of the method for manufacturing the memory card according to the first embodiment of the present invention.
  • FIG. 4A is a diagram showing a state in the middle of the method for manufacturing the memory card according to the first embodiment of the present invention.
  • FIG. 4B is a diagram showing a state in the middle of the method of manufacturing the memory card according to the first embodiment of the present invention.
  • FIG. 4C is a diagram showing a state in the middle of the method for manufacturing the memory card according to the first embodiment of the present invention.
  • FIG. 5 is a plan view showing a configuration of a memory card according to the second embodiment of the present invention.
  • FIG. 6 is a cross-sectional view taken along the line 6-6 in FIG.
  • FIG. 7 is a plan view showing a configuration of another example of the memory card according to the second embodiment of the present invention.
  • FIG. 1 is a plan view showing the configuration of the memory card 1 according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the memory card 1 taken along the line 2-2 in FIG.
  • FIG. 1 in order to facilitate understanding of the internal structure of the memory card 1, only the outline of the cover portion 7 is indicated by a broken line.
  • the sealing resin used for mounting a semiconductor chip is not shown.
  • an SD memory card (Secure Digital memory card) will be described as an example of the memory card 1.
  • the length and width of the memory card 1 size in the horizontal and vertical directions in Fig. 1) and thickness (size in the vertical direction in Fig. 2) are 14.9 mm and 15.1 mm, respectively. 10.9 mm to 11.1 mm and 0.9 mm to 1.1 mm.
  • the respective sizes are 15 mm, 11 mm, and lm m.
  • the upper side and the lower side in FIG. 2 will be described as the upper side and the lower side of the memory card 1, respectively, but the same applies to the second embodiment described below.
  • the memory card 1 includes a first circuit board 2 and a first circuit board 2 each having an outer periphery and an inner periphery formed of a so-called square-shaped frame-shaped substrate.
  • the first semiconductor chip 3 mounted with a ball bump (so-called “stud bump”, hereinafter simply referred to as “bump”) 33 on the upper surface 21 which is the upper main surface in FIG.
  • the second circuit board 4 in which the lower surface 22 of the first circuit board 2 is bonded to the upper surface 41, the second semiconductor chip 5 mounted with the bumps 53 on the upper surface 41 of the second circuit board 4, and the second It is mounted on the upper surface 41 of the circuit board 4 using solder.
  • the thickness of the memory card 1 at the position where the first semiconductor chip 3 and the second semiconductor chip 5 are mounted is 0.6 mm or more and 0.8 mm or less (0.7 mm in the present embodiment).
  • the second circuit board 4 is a glass epoxy board equivalent to FR-4.5 and has a thickness of 0.1 mm or more and 0.4 mm or less (0.16 mm in the present embodiment). As shown in FIG. 2, the second circuit board 4 has an electrode 411 to which the first circuit board 2 is bonded, an electrode 412 to which the second semiconductor chip 5 is bonded, and an electrode 413 to which the chip component 6 is bonded. Prepare for 41. Further, the second circuit board 4 includes a plurality of external electrodes 421 on the lower surface 42 for connection with external electronic devices. The external electrode 421 is electrically connected to the wiring provided on the upper surface 41 via a through hole (not shown) communicating from the lower surface 42 of the second circuit board 4 to the upper surface 41.
  • the thickness of the first circuit board 2 is 0.1 mm or more and 0.4 mm or less (0.12 mm in the present embodiment).
  • a plurality of electrodes 211 to which the first semiconductor chip 3 is bonded are provided on the upper surface 21 of the first circuit board 2 along the inner periphery of the first circuit board 2.
  • An electrode 221 is provided on the lower surface 22 of the first circuit board 2, and the electrode 221 is joined to the electrode 411 on the upper surface 41 of the second circuit board 4 via solder.
  • the first semiconductor chip 3 and the second semiconductor chip 5 are bare chips, and the thicknesses are 0.05 mm or more and 0.3 mm or less, respectively.
  • the first semiconductor chip 3 is a memory chip for storing information
  • the second semiconductor chip 5 is a control chip for controlling the first semiconductor chip 3.
  • the first semiconductor chip 3 includes bumps 33 formed on the electrodes on the lower surface 32, and the bumps 33 are bonded to the electrodes 211 of the first circuit board 2 by the sealing resin 34 (the contact is maintained and is in a state of being removed). Included).
  • the second semiconductor chip 5 includes bumps 53 formed on the electrodes on the lower surface 52, and the bumps 53 are bonded to the electrodes 412 of the second circuit board 4 by the sealing resin 54 (the state in which the contact is maintained and is maintained). Including).
  • the sealing resins 34 and 54 a non-conductive resin film such as a film-like resin material attached to the upper surface 21 of the first circuit board 2 and the upper surface 41 of the second circuit board 4 (NCF (Non-Conductive Film)) is used.
  • NCF Non-Conductive Film
  • the bump 33 is surrounded by the sealing resin 34 interposed between the first semiconductor chip 3 and the first circuit board 2.
  • the enclosure is covered.
  • the periphery of the bump 53 is covered with a sealing resin 54 interposed between the second semiconductor chip 5 and the second circuit board 4.
  • the lower surface 32 of the first semiconductor chip 3 is rectangular, and only the frame-shaped region along the outer periphery of the lower surface 32 (the region near the two sets of edges facing each other on the lower surface 32) is the first circuit board 2. Opposite. That is, in the memory card 1, only a part of the lower surface 32 of the first semiconductor chip 3 faces the upper surface 21 of the first circuit board 2.
  • the second semiconductor chip 5 is spaced apart from the inner periphery of the first circuit board 2 and inside the first circuit board 2 (rectangular opening 20 of the first circuit board 2 (see FIG. 1)). Has been placed.
  • the upper surface 51 of the second semiconductor chip 5 is a region in the vicinity of the center of the lower surface 32 of the first semiconductor chip 3 (other than the partial region of the lower surface 32 facing the first circuit board 2). Part area).
  • the memory card 1 is provided between the lower surface 32 of the first semiconductor chip 3 and the upper surface 51 of the second semiconductor chip 5, and the first semiconductor chip 3 and the first semiconductor chip 3 2
  • a fixing member 8 such as an adhesive for fixing the semiconductor chip 5 to each other is further provided.
  • the cover portion 7 is made of a molded part made of resin, and includes a first semiconductor chip 3, a first circuit board 2, a second semiconductor chip 5, and a recess 71 that accommodates the chip part 6.
  • the force bar portion 7 is attached to the second circuit board 4 through the opening of the recess 71.
  • FIGS. 3A and 3B are flowcharts of the manufacturing method of the memory card 1
  • FIGS. 4A to 4C are diagrams showing states in the middle of the manufacturing method of the memory card 1.
  • FIG. 4A to 4C, as in FIG. 2 the memory card 1 is shown in a cross-sectional view taken along the line 2-2 in FIG.
  • bumps 33 are formed on the electrodes on the lower surface 32 of the first semiconductor chip 3 (step S 11).
  • a sealing resin 34 such as NCF is attached to the electrode 211 on the upper surface 21 of the first circuit board 2. Thereby, the sealing resin 34 is applied to the electrode 211 (step S12).
  • the lower surface 32 of the first semiconductor chip 3 is held facing the upper surface 21 of the first circuit board 2 by a mounting apparatus (not shown). Then, the bump 33 is connected to the electrode 211 through the sealing resin 34. After the position of the first semiconductor chip 3 is adjusted so as to face the first semiconductor chip 3, the first semiconductor chip 3 is pressed against the first circuit board 2. At this time, only a part of the lower surface 32 of the first semiconductor chip 3 (a frame-shaped region along the outer periphery of the lower surface 32) faces the upper surface 21 of the first circuit board 2. Further, in a state where the first semiconductor chip 3 is pressed against the first circuit board 2, the first semiconductor chip 3 is heated, and the first semiconductor chip 3 is electrically connected to the first circuit board 2 with the bumps 33 interposed therebetween.
  • the sealing resin 34 is cured by heat, and the first semiconductor chip 3 is bonded to the first circuit board 2 and mounted (step S13).
  • the first circuit board 2 and the first semiconductor chip 3 mounted on the first circuit board 2 are collectively referred to as a “memory module”.
  • step S14 bumps 53 are formed on the electrodes on the lower surface 52 of the second semiconductor chip 5 (step S14).
  • a sealing resin 54 such as NCF is attached to the electrode 412 on the upper surface 41 of the second circuit board 4. Thereby, the sealing resin 54 is applied to the electrode 412 (step S15).
  • Step S16 the second circuit board 4 and the second semiconductor chip 5 mounted on the second circuit board 4 are collectively referred to as “controller module”.
  • the second semiconductor chip 5 is mounted on the upper surface 41 of the second circuit board 4 by the above-described Step 14 to Step 16.
  • an electrical inspection of the memory module and the controller module is performed by a inspection device (not shown). That is, by passing electricity through the first circuit board 2 to the memory module, whether the first semiconductor chip 3 is mounted on the first circuit board 2 is good or bad, for example, the first semiconductor chip 3 and the first circuit board 2 The electrical connection of the first semiconductor chip 3 It is electrically inspected whether or not it moves (step S17). In addition, by passing electricity through the second circuit board 4 to the controller module, whether the second semiconductor chip 5 is mounted on the second circuit board 4 is electrically inspected (step S18).
  • cream solder is applied to the upper surface 41 of the second circuit board 4 through a mask as shown in FIG. 4C. It is applied on the electrode 411 and the electrode 413 (step S19). Further, a fixing member 8 such as an adhesive is applied to the upper surface 51 of the second semiconductor chip 5 (step S20).
  • the position of the first circuit board 2 is adjusted so that the electrode 221 on the lower surface 22 of the first circuit board 2 faces the electrode 411 of the second circuit board 4 via solder.
  • the first circuit board 2 is mounted on the second circuit board 4.
  • the chip component 6 is mounted on the electrode 413 of the second circuit board 4 via solder.
  • the fixing member 8 on the upper surface 51 of the second semiconductor chip 5 is pressed by the lower surface 32 of the first semiconductor chip 3.
  • the fixing member 8 extends from the space between the first semiconductor chip 3 and the second semiconductor chip 5 to the space around the second semiconductor chip 5, and is cured in this state. .
  • an area near the center of the lower surface 32 of the first semiconductor chip 3 (a part of the lower surface 32 of the first semiconductor chip 3 other than a part of the area facing the first circuit board 2).
  • the electrode 221 on the lower surface 22 of the first circuit board 2 is joined to the electrode 411 on the upper surface 41 of the second circuit board 4 with the upper surface 51 facing the second semiconductor chip 5.
  • the electrode of the chip component 6 is bonded to the electrode 413 of the second circuit board 4 (step S21).
  • the cover portion 7 is attached to the second circuit board 4 to which the memory module and the chip component 6 are joined through the opening of the recess 71.
  • the first semiconductor chip 3, the first circuit board 2, the second semiconductor chip 5, and the chip component 6 are covered with the force bar portion 7 on the upper surface 41 side of the second circuit board 4, and the memory card 1 is manufactured. (Step S22).
  • step S17 when a mounting failure of the first semiconductor chip 3 to the first circuit board 2 is detected in step S17, other normal memory modules are prepared and the normal modules are connected to each other. Be joined. Similarly, if a mounting failure of the second semiconductor chip 5 to the second circuit board 4 is detected in step S18, another normal component is detected. Troller modules are prepared and normal modules are joined together. In addition, repair work (for example, semiconductor chip unbonding or re-mounting) is performed on modules for which defective mounting has been detected.
  • repair work for example, semiconductor chip unbonding or re-mounting
  • the memory card 1 can be reduced in size and thickness. .
  • the first semiconductor chip 3 is mounted on the first circuit board
  • the second semiconductor chip 5 is mounted on the second circuit board 4
  • each is modularized. Laminate in state. Therefore, before stacking both modules, each module can be electrically inspected, and the mounting quality of the first semiconductor chip 3 and the second semiconductor chip 5 can be individually inspected. As a result, mounting defects can be detected before the memory module and controller module are stacked, reducing production costs.
  • thermosetting resin having a low viscosity there is a case where a cover portion of a memory card is usually formed by forming a thermosetting resin by covering a semiconductor chip or the like on the upper surface side of the circuit board.
  • the first semiconductor chip 3 and the second semiconductor chip 5 are flip-chip connected to the first circuit board 2 and the second circuit board 4 with the bumps 33 and 53 interposed therebetween.
  • the first semiconductor chip 3 and the second semiconductor chip 5 are flip-chip connected to the first circuit board 2 and the second circuit board 4 with the bumps 33 and 53 interposed therebetween.
  • it is not always necessary to seal the first semiconductor chip 3, the second semiconductor chip 5, and the first circuit board 2 with a thermosetting resin or the like or to form a cover portion.
  • the degree of freedom in selecting the material and formation method of the cover part 7 is improved.
  • the flip chip mounting of the first semiconductor chip 3 and the second semiconductor chip 5 improves the reliability during mounting compared to the wire bonding mounting.
  • the electrical connection between each semiconductor chip and each circuit board is achieved.
  • Manufacturing of the memory card 1 can be simplified by omitting the step of separately sealing the connection portion.
  • the cover part 7 made of molded parts covers the first semiconductor chip 3, the first circuit board 2 and the second semiconductor chip 5, etc., when the cover part is formed by sealing with a thermosetting resin or the like. In comparison, the manufacturing of the memory card 1 can be further simplified.
  • the first semiconductor chip 3 is joined to the first circuit board 2 in a frame-like region along the outer periphery of the lower surface 32 of the first semiconductor chip 3. 2 can be firmly fixed. Then, in order to further fix the lower surface 32 of the first semiconductor chip 3 and the upper surface 51 of the second semiconductor chip 5 with the fixing member 8 made of an adhesive, the first semiconductor chip 3 is indirectly and firmly fixed to the second circuit board 4. Can be fixed to.
  • FIG. 5 is a plan view showing the configuration of the memory card la according to the second embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of the memory card la taken along line 6-6 in FIG. FIG.
  • FIG. 5 in order to facilitate understanding of the internal structure of the memory card la, only the outline of the cover portion 7a is indicated by a broken line.
  • the sealing resin used for mounting the semiconductor chip is not shown.
  • the memory card la includes a first circuit board 2a having a shape different from that of the first circuit board 2 of the memory card 1 shown in FIGS.
  • the memory card la includes a cover portion 7a formed of a thermoplastic resin.
  • Other configurations are the same as those in FIGS. 1 and 2, and will be described with the same reference numerals. Further, the flow of the method for manufacturing the memory card la is almost the same as that of the first embodiment, so the description will be simplified.
  • the first circuit board 2a is a so-called open circuited circuit board having a rectangular outer periphery and inner periphery shown in FIG. It has a U-shaped shape.
  • the memory card la faces a pair of edges of the lower surface 32 of the first semiconductor chip 3 facing each other and a region force in the vicinity of one edge orthogonal to the one set of edges, and faces the upper surface 21 of the first circuit board 2a. is doing. Therefore, a part of the second semiconductor chip 5 does not overlap the first semiconductor chip 3. That is, the memory card la is the upper surface 5 of the second semiconductor chip 5. Only a part of 1 has a configuration facing a part of the region other than a part of the bottom surface 32 of the first semiconductor chip 3 facing the first circuit board 2a.
  • bumps 33 are formed on the electrodes on the lower surface 32 of the first semiconductor chip 3, and the sealing resin 34 is applied to the electrodes 211 on the upper surface 21 of the first circuit board 2a (steps S11 and S12). ).
  • the first semiconductor chip 3 is electrically connected to the first circuit board 2a with the bumps 33 interposed therebetween, and the sealing resin 34 is cured to attach the first semiconductor chip 3 to the first circuit board 2a.
  • Step S13 Through the above-described steps, the first semiconductor chip 3 is mounted on the first circuit board 2a.
  • bumps 53 are formed on the electrodes on the lower surface 52 of the second semiconductor chip 5, and the sealing resin 54 is applied to the electrodes 412 on the upper surface 41 of the second circuit board 4 (steps S14 and S15). ).
  • the second semiconductor chip 5 is electrically connected to the second circuit board 4 with the bumps 53 interposed therebetween, and the sealing resin 54 is cured so that the second semiconductor chip 5 is attached to the second circuit board 4.
  • Join Step S16.
  • the second semiconductor chip 5 is mounted on the upper surface 41 of the second circuit board 4.
  • step S17 whether or not the first semiconductor chip 3 is mounted on the first circuit board 2a is electrically inspected via the first circuit board 2a.
  • step S18 whether the second semiconductor chip 5 is mounted on the second circuit board 4 is electrically inspected via the second circuit board 4.
  • solder is applied to the electrodes 411 and 413 on the upper surface 41 of the second circuit board 4 (step S19). Further, the fixing member 8 made of an adhesive is applied to the upper surface 51 of the second semiconductor chip 5 (step S20). Then, the first circuit board 2a and the chip part 6 are mounted on the second circuit board 4 and reflowed to join the first circuit board 2a and the chip part 6 to the second circuit board 4 (step S21).
  • thermoplastic resin covering the first semiconductor chip 3, the first circuit board 2a, the second semiconductor chip 5 and the chip component 6 is formed on the second circuit board 4 by, for example, insert molding, and the cover portion. 7a is formed.
  • the memory card la is manufactured through the above steps.
  • the first semiconductor chip 3 and the second semiconductor chip 5 are sandwiched between them. Therefore, the memory card la can be reduced in size and thickness.
  • at least a part of the second semiconductor chip 5 is other than a part of the region facing the first circuit board 2a on the lower surface 32 of the first semiconductor chip 3. The other part of the area is opposed to it.
  • the memory module and the controller module are inspected before being stacked, it is possible to individually determine whether the first semiconductor chip 3 and the second semiconductor chip 5 are mounted correctly. , Productivity and production cost can be reduced.
  • the first semiconductor chip 3 and the second semiconductor chip 5 are flip-chip mounted, so that the material of the cover portion 7a
  • the degree of freedom in selecting the formation method can be improved.
  • the flip chip mounting of the first semiconductor chip 3 and the second semiconductor chip 5 improves the reliability during mounting compared to wire bonding mounting.
  • the force S can be firmly fixed to the first circuit board 2a.
  • the first semiconductor chip 3 can be indirectly and firmly fixed to the second circuit board 4 by the fixing member 8 made of an adhesive.
  • the cover portion 7a is formed of a thermoplastic resin, thereby reducing the hardness of the cover portion 7a and increasing the reliability such as safety. Can do.
  • the force S described using the first semiconductor chip 3 and the second semiconductor chip 5 as an example of the memory chip and the control chip is not limited to this.
  • other bare chips such as ASIC may be used as the first semiconductor chip 3 and the second semiconductor chip 5.
  • two memory chips are stacked as the first semiconductor chip 3 and the second semiconductor chip 5, and the two memory chips are controlled by a control chip mounted on another area of the second circuit board 4.
  • a memory / controller combined chip for storing information and controlling other memory chips may be mounted on the second circuit board 4. This At this time, the semiconductor chip may not be a chip having a semiconductor function as a whole as long as it is a chip partially utilizing a semiconductor function.
  • the first semiconductor chip 3 is bonded to the first circuit board in a frame-like region along the outer periphery of the lower surface 32 or in a region near the three edges of the lower surface 32. I explained in, but this is limited to this.
  • a first circuit board 2b composed of two parallel boards is bonded onto the second circuit board 4, and the lower surfaces of the first semiconductor chip 3 are connected to each other.
  • a configuration may be adopted in which the first circuit board 2b is opposed and joined in a region in the vicinity of a pair of opposing edges.
  • the bumps 33 and 53 are described as examples formed on the electrodes of the first semiconductor chip 3 and the electrodes of the second semiconductor chip. It may be formed on the electrode 211 and on the electrode 412 of the second circuit board 4. In addition to the ball bumps, other types of ball bumps such as solder bumps, solder bumps, and the like may be used as the bumps 33 and 53.
  • the force S described as an example of sticking NCF or the like as the sealing resin is not limited to this.
  • the sealing resin may be formed using a non-conductive resin paste, an anisotropic conductive resin film, or an anisotropic conductive resin paste.
  • the example in which the second circuit board 4 of the second semiconductor chip 5 is mounted after the first circuit board of the first semiconductor chip 3 is mounted has been described. I can't.
  • the mounting of the second circuit board 4 of the second semiconductor chip 5 may be performed in parallel with the mounting of the first circuit board of the first semiconductor chip 3 before the mounting of the first semiconductor chip 3. You may go. Similarly, whether the mounting of the first circuit board of the first semiconductor chip 3 is inspected before the mounting of the second circuit board 4 of the second semiconductor chip 5 is performed. You can go in parallel with the implementation.
  • the present invention is not limited to this. If necessary, at least one of mounting the first semiconductor chip 3 on the first circuit board and mounting the second semiconductor chip 5 on the second circuit board 4 may be performed by wire bonding. However, the first semiconductor chip 3 and the second semiconductor chip 2 are improved in terms of improving the mounting reliability and improving the degree of freedom in selecting the cover material and the forming method.
  • the semiconductor chip 5 is preferably mounted on the circuit board by flip chip mounting.
  • the cover portion is formed of a thermoplastic resin.
  • the cover may be formed by molding a thermosetting resin.
  • the memory card of the present invention may be used as another card type recording medium other than an SD card, such as an IC card.
  • the present invention is useful in a technical field such as a memory card that records information, and that is particularly required to be reduced in size and thickness.

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Abstract

A memory card (1) is provided with a first circuit board (2); a first semiconductor chip (3), which is mounted on an upper plane (21) of the first circuit board (2) and has only a partial region of a lower plane (32) face the first circuit board (2); a second circuit board (4) wherein a lower plane (22) of the first circuit board (2) is bonded on an upper plane (41); a second semiconductor chip (5), which is mounted on the upper plane (41) of the second circuit board (4) and at least partially faces a partial region other than the partial region of the lower plane (32) of the first semiconductor chip (3); and a cover section (7) for covering the first semiconductor chip (3), the first circuit board (2) and the second semiconductor chip (5), on the side of the upper plane (41) of the second circuit board (4).

Description

明 細 書  Specification
メモリカードおよびメモリカードの製造方法  Memory card and memory card manufacturing method
技術分野  Technical field
[0001] 本発明は、メモリカードおよびその製造方法に関する。  The present invention relates to a memory card and a manufacturing method thereof.
背景技術  Background art
[0002] 従来、情報を記録する記録媒体の一つとしてメモリチップが内蔵されたメモリカード が知られている。そして、メモリカードは携帯性に優れているため、携帯型情報端末 や携帯電話などの携帯型電子機器の記録媒体として広く使用されている。これらの 携帯型電子機器は携帯性向上などの観点力 年々小型化と大容量ィヒが進められ、 これに伴ってさらにメモリカードの小型化と大容量ィ匕が要求されている。通常、メモリ カードには、その形状や大きさ、厚さなどが規格で定められているため、規格を満足 しつつ大容量化を実現することが求められる。  Conventionally, a memory card incorporating a memory chip is known as one of recording media for recording information. Since memory cards are excellent in portability, they are widely used as recording media for portable electronic devices such as portable information terminals and mobile phones. These portable electronic devices have the viewpoint of improving portability, etc. The miniaturization and large capacity have been promoted year by year, and accordingly, further miniaturization of memory cards and large capacity have been required. Usually, memory cards are required to have a large capacity while satisfying the standards because their shape, size, thickness, etc. are defined by the standards.
[0003] そこで、ベース基板の一方の面にメモリチップが実装された複数のメモリ用基板を 積層して実装し、他方の面にメモリチップの動作を制御するコントロールチップを実 装して、メモリカードの容量を大きくする技術が開示されている(例えば、特許文献 1 参照)。  [0003] Therefore, a plurality of memory substrates on which memory chips are mounted are stacked and mounted on one surface of the base substrate, and a control chip for controlling the operation of the memory chip is mounted on the other surface, thereby providing a memory. A technique for increasing the capacity of a card is disclosed (for example, see Patent Document 1).
[0004] また、リードフレーム上に搭載されたメモリチップ上に、もう 1つのメモリチップをずら して積層する。そして、 2つのメモリチップの電極およびリードフレーム上に搭載され たコントロールチップの電極を金ワイヤを介してリードフレームに接続して、メモリカー ドを薄型化する技術が開示されている (例えば、特許文献 2参照)。  [0004] In addition, another memory chip is shifted and stacked on the memory chip mounted on the lead frame. Then, a technology for thinning the memory card by connecting the electrodes of the two memory chips and the electrodes of the control chip mounted on the lead frame to the lead frame via gold wires is disclosed (for example, patents). Reference 2).
[0005] しかしながら、特許文献 1のメモリカードでは、メモリチップとコントロールチップとを ベース基板の異なる面に実装するため、メモリカードの薄型化に限界がある。また、メ モリ用基板を積層することもメモリカードの薄型化を妨げる原因となっている。 However, in the memory card of Patent Document 1, since the memory chip and the control chip are mounted on different surfaces of the base substrate, there is a limit to reducing the thickness of the memory card. In addition, stacking memory substrates is another factor that hinders the thinning of memory cards.
[0006] また、特許文献 2のメモリカードでは、メモリチップやコントロールチップのリードフレ ームへの実装をワイヤボンディングで行う。そのため、実装後にこれらの各チップゃヮ ィャ、リードフレームなどを熱硬化性樹脂などにより封止する必要がある。このとき、メ モリチップやワイヤを十分に覆う厚い封止層が必要となるため、メモリカードの小型化 や薄型化に限界がある。また、実装ステップとは別に封止ステップが必要となるため、 製造コストの低減にも限界がある。さらに、各チップの実装の良否の検査を、全チップ 力 Sリードフレームに実装された後にしか行うことができなレ、。そのため、一部のチップ に実装不良が生じた場合、残りのチップの実装終了まで不良を検出することができ ず、生産コストが増加する。 [0006] In the memory card of Patent Document 2, the memory chip and the control chip are mounted on the lead frame by wire bonding. Therefore, it is necessary to seal each chip carrier, lead frame, etc. with a thermosetting resin after mounting. At this time, since a thick sealing layer that sufficiently covers the memory chip and wires is required, the memory card can be downsized. There is a limit to thinning. In addition, since a sealing step is required separately from the mounting step, there is a limit to reducing the manufacturing cost. In addition, the quality of each chip can be checked only after it has been mounted on the S lead frame with full chip strength. For this reason, when mounting defects occur in some chips, the defects cannot be detected until the mounting of the remaining chips is completed, increasing the production cost.
特許文献 1 :特開 2003— 108963号公報  Patent Document 1: Japanese Patent Laid-Open No. 2003-108963
特許文献 2:特開 2004— 13738号公報  Patent Document 2: JP 2004-13738 A
発明の開示  Disclosure of the invention
[0007] 本発明のメモリカードは、第 1回路基板と、第 1回路基板の上面に実装されるととも に下面の一部の領域のみが第 1回路基板と対向する第 1半導体チップと、上面に第 1回路基板の下面が接合された第 2回路基板と、第 2回路基板の上面に実装されると ともに少なくとも一部が第 1半導体チップの下面の一部の領域以外の他の一部の領 域と対向する第 2半導体チップと、第 2回路基板の上面側において第 1半導体チップ 、第 1回路基板と第 2半導体チップを覆うカバー部とを備える。  [0007] A memory card of the present invention includes a first circuit board, a first semiconductor chip mounted on the upper surface of the first circuit board, and a partial region of the lower surface facing the first circuit board; A second circuit board in which the lower surface of the first circuit board is bonded to the upper surface; and a second circuit board that is mounted on the upper surface of the second circuit board and at least a part other than a partial region of the lower surface of the first semiconductor chip. A second semiconductor chip facing the region of the part, a first semiconductor chip on the upper surface side of the second circuit board, and a cover part covering the first circuit board and the second semiconductor chip.
[0008] この構成により、第 1半導体チップと第 2半導体チップとの間に回路基板を挟むこと なく重ねて配置できるため、メモリカードの小型化と薄型化を実現することができる。  [0008] With this configuration, the first and second semiconductor chips can be stacked without being sandwiched between the first and second semiconductor chips, so that the memory card can be reduced in size and thickness.
[0009] また、本発明のメモリカードの製造方法は、 a)第 1半導体チップの下面の一部の領 域のみを第 1回路基板と対向させて第 1回路基板の上面に実装するステップと、 b)第 2回路基板の上面に第 2半導体チップを実装するステップと、 c)第 2半導体チップの 少なくとも一部を第 1半導体チップの下面の一部の領域以外の他の一部の領域と対 向させて第 2回路基板の上面に接合するステップと、 d)第 2回路基板の上面側にお レ、て第 1半導体チップ、第 1回路基板と第 2半導体チップをカバー部で覆うステップと を含む。  [0009] Further, the method of manufacturing a memory card of the present invention includes: a) a step of mounting only a partial region of the lower surface of the first semiconductor chip on the upper surface of the first circuit board so as to face the first circuit board; B) mounting the second semiconductor chip on the upper surface of the second circuit board; and c) at least a part of the second semiconductor chip other than a part of the lower surface of the first semiconductor chip. And d) covering the first semiconductor chip and the first circuit board and the second semiconductor chip with a cover on the upper surface side of the second circuit board. Includes steps and.
[0010] この方法により、小型化と薄型化とともに、簡単な方法でメモリカードを生産性よく作 製できる。  [0010] By this method, a memory card can be manufactured with high productivity by a simple method as well as downsizing and thinning.
図面の簡単な説明  Brief Description of Drawings
[0011] [図 1]図 1は、本発明の第 1の実施の形態に係るメモリカードの構成を示す平面図で ある。 [図 2]図 2は、図 1の 2— 2線の位置で切断した断面図である。 FIG. 1 is a plan view showing a configuration of a memory card according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line 2-2 in FIG.
園 3A]図 3Aは、本発明の第 1の実施の形態に係るメモリカードの製造方法のフロー チャートである。 3A] FIG. 3A is a flowchart of the method for manufacturing the memory card according to the first embodiment of the present invention.
[図 3B]図 3Bは、本発明の第 1の実施の形態に係るメモリカードの製造方法のフロー チャートである。  FIG. 3B is a flowchart of the method for manufacturing the memory card according to the first embodiment of the present invention.
園 4A]図 4Aは、本発明の第 1の実施の形態に係るメモリカードの製造方法の途中の 状態を示す図である。 4A] FIG. 4A is a diagram showing a state in the middle of the method for manufacturing the memory card according to the first embodiment of the present invention.
[図 4B]図 4Bは、本発明の第 1の実施の形態に係るメモリカードの製造方法の途中の 状態を示す図である。  FIG. 4B is a diagram showing a state in the middle of the method of manufacturing the memory card according to the first embodiment of the present invention.
園 4C]図 4Cは、本発明の第 1の実施の形態に係るメモリカードの製造方法の途中の 状態を示す図である。 4C] FIG. 4C is a diagram showing a state in the middle of the method for manufacturing the memory card according to the first embodiment of the present invention.
園 5]図 5は、本発明の第 2の実施の形態に係るメモリカードの構成を示す平面図で ある。 FIG. 5 is a plan view showing a configuration of a memory card according to the second embodiment of the present invention.
[図 6]図 6は、図 5の 6— 6線の位置で切断した断面図である。  FIG. 6 is a cross-sectional view taken along the line 6-6 in FIG.
園 7]図 7は、本発明の第 2の実施の形態に係るメモリカードの他の例の構成を示す 平面図である。 7] FIG. 7 is a plan view showing a configuration of another example of the memory card according to the second embodiment of the present invention.
符号の説明 Explanation of symbols
1 , la, lb メモリカード  1, la, lb memory card
2, 2a, 2b 第 1回路基板  2, 2a, 2b 1st circuit board
3 第 1半導体チップ  3 First semiconductor chip
4 第 2回路基板  4 Second circuit board
5 第 2半導体チップ  5 Second semiconductor chip
6 チップ部品  6 Chip parts
7, 7a カバー部  7, 7a Cover part
8 固定部材  8 Fixing member
20 開口部  20 opening
21 , 41, 51 , 52 上面  21, 41, 51, 52 Top surface
22, 32, 42 下面 33, 53 バンプ 22, 32, 42 bottom 33, 53 Bump
34, 54 封止樹脂  34, 54 Sealing resin
71 凹部  71 recess
211 , 221, 411 , 412, 413 電極  211, 221, 411, 412, 413 electrodes
421 外部電極  421 External electrode
S11〜S22 ステップ  S11 to S22 steps
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0013] 以下、本発明の実施の形態について、図面を参照しながら説明する。なお、同じ要 素については同じ符号を付し、説明を省略する場合がある。  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the same elements are denoted by the same reference numerals and description thereof may be omitted.
[0014] (第 1の実施の形態)  [0014] (First embodiment)
図 1は、本発明の第 1の実施の形態に係るメモリカード 1の構成を示す平面図であ る。図 2は、メモリカード 1を図 1の 2— 2線の位置で切断した断面図である。なお、図 1 では、メモリカード 1の内部構造の理解を容易にするために、カバー部 7については 輪郭のみを破線で示している。また、図 1では、半導体チップの実装などに利用され る封止樹脂は図示していない。  FIG. 1 is a plan view showing the configuration of the memory card 1 according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view of the memory card 1 taken along the line 2-2 in FIG. In FIG. 1, in order to facilitate understanding of the internal structure of the memory card 1, only the outline of the cover portion 7 is indicated by a broken line. In FIG. 1, the sealing resin used for mounting a semiconductor chip is not shown.
[0015] 本実施の形態では、メモリカード 1として、 SDメモリカード(Secure Digital mem ory card)を例に説明する。通常、メモリカード 1の長さと幅(図 1中の左右方向と上 下方向の大きさ)および厚さ(図 2中の上下方向の大きさ)は、それぞれ、 14. 9mm 以上 15. 1mm以下、 10. 9mm以上 11. 1mm以下および 0. 9mm以上 1. 1mm以 下である。なお、本実施の形態では、それぞれの大きさを 15mm、 11mmおよび lm mとする。また、便宜上、図 2中の上側および下側をそれぞれ、メモリカード 1の上側 および下側として説明するが、以下の第 2の実施の形態においても同様である。  In the present embodiment, an SD memory card (Secure Digital memory card) will be described as an example of the memory card 1. Usually, the length and width of the memory card 1 (size in the horizontal and vertical directions in Fig. 1) and thickness (size in the vertical direction in Fig. 2) are 14.9 mm and 15.1 mm, respectively. 10.9 mm to 11.1 mm and 0.9 mm to 1.1 mm. In the present embodiment, the respective sizes are 15 mm, 11 mm, and lm m. For convenience, the upper side and the lower side in FIG. 2 will be described as the upper side and the lower side of the memory card 1, respectively, but the same applies to the second embodiment described below.
[0016] 図 1と図 2に示すように、メモリカード 1は、外周と内周が、いわゆる口の字型の矩形 状の額縁状基板からなる第 1回路基板 2と、第 1回路基板 2の図 2中の上側の主面で ある上面 21にボールバンプ(いわゆる「スタッドバンプ」であり、以下、単に「バンプ」と レ、う。) 33を挟んで実装される第 1半導体チップ 3と、上面 41に第 1回路基板 2の下面 22が接合される第 2回路基板 4と、第 2回路基板 4の上面 41にバンプ 53を挟んで実 装される第 2半導体チップ 5と、第 2回路基板 4の上面 41にはんだを用いて実装され る抵抗などの微細なチップ部品 6と、第 2回路基板 4の上面 41側において第 1半導体 チップ 3、第 1回路基板 2、第 2半導体チップ 5とチップ部品 6とを覆うカバー部 7を備 える。そして、第 1半導体チップ 3と第 2半導体チップ 5を実装する位置のメモリカード 1の厚さは 0. 6mm以上 0. 8mm以下(本実施の形態では、 0. 7mm)である。 [0016] As shown in FIGS. 1 and 2, the memory card 1 includes a first circuit board 2 and a first circuit board 2 each having an outer periphery and an inner periphery formed of a so-called square-shaped frame-shaped substrate. The first semiconductor chip 3 mounted with a ball bump (so-called “stud bump”, hereinafter simply referred to as “bump”) 33 on the upper surface 21 which is the upper main surface in FIG. The second circuit board 4 in which the lower surface 22 of the first circuit board 2 is bonded to the upper surface 41, the second semiconductor chip 5 mounted with the bumps 53 on the upper surface 41 of the second circuit board 4, and the second It is mounted on the upper surface 41 of the circuit board 4 using solder. And a cover part 7 that covers the first semiconductor chip 3, the first circuit board 2, the second semiconductor chip 5 and the chip part 6 on the upper surface 41 side of the second circuit board 4. Yeah. The thickness of the memory card 1 at the position where the first semiconductor chip 3 and the second semiconductor chip 5 are mounted is 0.6 mm or more and 0.8 mm or less (0.7 mm in the present embodiment).
[0017] 第 2回路基板 4は、 FR-4. 5相当のガラスエポキシ基板であり、厚さは 0. 1mm以 上 0. 4mm以下(本実施の形態では、 0. 16mm)である。図 2に示すように、第 2回路 基板 4は、第 1回路基板 2が接合される電極 411、第 2半導体チップ 5が接合される電 極 412およびチップ部品 6が接合される電極 413を上面 41に備える。さらに、第 2回 路基板 4は、外部の電子機器との接続用の複数の外部電極 421を下面 42に備える 。外部電極 421は、第 2回路基板 4の下面 42から上面 41へと連通するスルーホール (図示せず)を介して、上面 41上に設けられている配線と電気的に接続される。  The second circuit board 4 is a glass epoxy board equivalent to FR-4.5 and has a thickness of 0.1 mm or more and 0.4 mm or less (0.16 mm in the present embodiment). As shown in FIG. 2, the second circuit board 4 has an electrode 411 to which the first circuit board 2 is bonded, an electrode 412 to which the second semiconductor chip 5 is bonded, and an electrode 413 to which the chip component 6 is bonded. Prepare for 41. Further, the second circuit board 4 includes a plurality of external electrodes 421 on the lower surface 42 for connection with external electronic devices. The external electrode 421 is electrically connected to the wiring provided on the upper surface 41 via a through hole (not shown) communicating from the lower surface 42 of the second circuit board 4 to the upper surface 41.
[0018] 第 1回路基板 2の厚さは、 0. 1mm以上 0. 4mm以下(本実施の形態では、 0. 12 mm)である。そして、第 1回路基板 2の上面 21には、第 1半導体チップ 3が接合され る複数の電極 211が、第 1回路基板 2の内周に沿って設けられている。また、第 1回 路基板 2の下面 22には電極 221が設けられ、電極 221は、はんだを介して第 2回路 基板 4の上面 41の電極 411に接合される。  [0018] The thickness of the first circuit board 2 is 0.1 mm or more and 0.4 mm or less (0.12 mm in the present embodiment). A plurality of electrodes 211 to which the first semiconductor chip 3 is bonded are provided on the upper surface 21 of the first circuit board 2 along the inner periphery of the first circuit board 2. An electrode 221 is provided on the lower surface 22 of the first circuit board 2, and the electrode 221 is joined to the electrode 411 on the upper surface 41 of the second circuit board 4 via solder.
[0019] 第 1半導体チップ 3と第 2半導体チップ 5はベアチップであり、厚さはそれぞれ 0. 05 mm以上 0. 3mm以下である。ここで、第 1半導体チップ 3は情報を記憶するメモリチ ップで、第 2半導体チップ 5は第 1半導体チップ 3を制御するコントロールチップである 。第 1半導体チップ 3は、下面 32の電極上に形成されたバンプ 33を備え、バンプ 33 は封止樹脂 34により第 1回路基板 2の電極 211に接合 (接触が保たれてレ、る状態を 含む)されている。また、第 2半導体チップ 5は下面 52の電極上に形成されたバンプ 53を備え、バンプ 53は封止樹脂 54により第 2回路基板 4の電極 412に接合 (接触が 保たれてレ、る状態を含む)されてレ、る。  The first semiconductor chip 3 and the second semiconductor chip 5 are bare chips, and the thicknesses are 0.05 mm or more and 0.3 mm or less, respectively. Here, the first semiconductor chip 3 is a memory chip for storing information, and the second semiconductor chip 5 is a control chip for controlling the first semiconductor chip 3. The first semiconductor chip 3 includes bumps 33 formed on the electrodes on the lower surface 32, and the bumps 33 are bonded to the electrodes 211 of the first circuit board 2 by the sealing resin 34 (the contact is maintained and is in a state of being removed). Included). In addition, the second semiconductor chip 5 includes bumps 53 formed on the electrodes on the lower surface 52, and the bumps 53 are bonded to the electrodes 412 of the second circuit board 4 by the sealing resin 54 (the state in which the contact is maintained and is maintained). Including).
[0020] 本実施の形態では、封止樹脂 34、 54として、第 1回路基板 2の上面 21と第 2回路 基板 4の上面 41に貼付されるフィルム状の樹脂材料などの非導電性樹脂フィルム( NCF (Non - Conductive Film) )が利用される。そして、メモリカード 1では、第 1 半導体チップ 3と第 1回路基板 2との間に介在する封止樹脂 34によりバンプ 33の周 囲が覆われる。また、第 2半導体チップ 5と第 2回路基板 4との間に介在する封止樹脂 54によりバンプ 53の周囲が覆われる。 [0020] In the present embodiment, as the sealing resins 34 and 54, a non-conductive resin film such as a film-like resin material attached to the upper surface 21 of the first circuit board 2 and the upper surface 41 of the second circuit board 4 (NCF (Non-Conductive Film)) is used. In the memory card 1, the bump 33 is surrounded by the sealing resin 34 interposed between the first semiconductor chip 3 and the first circuit board 2. The enclosure is covered. Further, the periphery of the bump 53 is covered with a sealing resin 54 interposed between the second semiconductor chip 5 and the second circuit board 4.
[0021] 第 1半導体チップ 3の下面 32は矩形であり、その下面 32の外周に沿う額縁状の領 域(下面 32において互いに対向する 2組のエッジ近傍の領域)のみが第 1回路基板 2と対向する。すなわち、メモリカード 1では、第 1半導体チップ 3の下面 32の一部の 領域のみが第 1回路基板 2の上面 21と対向することになる。  [0021] The lower surface 32 of the first semiconductor chip 3 is rectangular, and only the frame-shaped region along the outer periphery of the lower surface 32 (the region near the two sets of edges facing each other on the lower surface 32) is the first circuit board 2. Opposite. That is, in the memory card 1, only a part of the lower surface 32 of the first semiconductor chip 3 faces the upper surface 21 of the first circuit board 2.
[0022] 第 2半導体チップ 5は、第 1回路基板 2の内周と離間して、第 1回路基板 2の内側( 第 1回路基板 2の矩形状の開口部 20 (図 1参照))に配置されている。そして、第 2半 導体チップ 5の上面 51は、第 1半導体チップ 3の下面 32の中央近傍の領域(下面 32 のうち、第 1回路基板 2と対向する上記一部の領域以外の他の一部の領域)と対向す る。  [0022] The second semiconductor chip 5 is spaced apart from the inner periphery of the first circuit board 2 and inside the first circuit board 2 (rectangular opening 20 of the first circuit board 2 (see FIG. 1)). Has been placed. The upper surface 51 of the second semiconductor chip 5 is a region in the vicinity of the center of the lower surface 32 of the first semiconductor chip 3 (other than the partial region of the lower surface 32 facing the first circuit board 2). Part area).
[0023] また、メモリカード 1は、図 2に示すように、第 1半導体チップ 3の下面 32と第 2半導 体チップ 5の上面 51との間に設けられ、第 1半導体チップ 3と第 2半導体チップ 5とを 互いに固定する接着剤などの固定部材 8をさらに備える。  Further, as shown in FIG. 2, the memory card 1 is provided between the lower surface 32 of the first semiconductor chip 3 and the upper surface 51 of the second semiconductor chip 5, and the first semiconductor chip 3 and the first semiconductor chip 3 2 A fixing member 8 such as an adhesive for fixing the semiconductor chip 5 to each other is further provided.
[0024] カバー部 7は、樹脂により形成された成型部品からなり、第 1半導体チップ 3、第 1回 路基板 2、第 2半導体チップ 5とチップ部品 6を収容する凹部 71を備える。そして、力 バー部 7は、凹部 71の開口を介して第 2回路基板 4に取り付けられる。  [0024] The cover portion 7 is made of a molded part made of resin, and includes a first semiconductor chip 3, a first circuit board 2, a second semiconductor chip 5, and a recess 71 that accommodates the chip part 6. The force bar portion 7 is attached to the second circuit board 4 through the opening of the recess 71.
[0025] 以下に、本発明の第 1の実施の形態に係るメモリカード 1の製造方法について説明 する。図 3Aと図 3Bは、メモリカード 1の製造方法のフローチャートであり、図 4Aから 図 4Cは、メモリカード 1の製造方法の途中の状態を示す図である。なお、図 4Aから 図 4Cでは、図 2と同様に、メモリカード 1を図 1の 2— 2線の位置で切断した断面図で 示している。  [0025] A method for manufacturing the memory card 1 according to the first embodiment of the present invention will be described below. FIGS. 3A and 3B are flowcharts of the manufacturing method of the memory card 1, and FIGS. 4A to 4C are diagrams showing states in the middle of the manufacturing method of the memory card 1. FIG. 4A to 4C, as in FIG. 2, the memory card 1 is shown in a cross-sectional view taken along the line 2-2 in FIG.
[0026] まず、図 4Aに示すように、第 1半導体チップ 3の下面 32の電極上にバンプ 33を形 成する(ステップ S 11)。  First, as shown in FIG. 4A, bumps 33 are formed on the electrodes on the lower surface 32 of the first semiconductor chip 3 (step S 11).
[0027] 次に、第 1回路基板 2の上面 21の電極 211に、例えば NCFなどの封止樹脂 34を 貼付する。これにより、封止樹脂 34が電極 211に付与される (ステップ S12)。  Next, a sealing resin 34 such as NCF is attached to the electrode 211 on the upper surface 21 of the first circuit board 2. Thereby, the sealing resin 34 is applied to the electrode 211 (step S12).
[0028] 次に、実装装置(図示せず)により、第 1半導体チップ 3の下面 32が第 1回路基板 2 の上面 21と対向して保持される。そして、バンプ 33が封止樹脂 34を介して電極 211 と対向するように第 1半導体チップ 3の位置を調整した後、第 1半導体チップ 3を第 1 回路基板 2に押圧する。このとき、第 1半導体チップ 3の下面 32の一部の領域(下面 32の外周に沿う額縁状の領域)のみが第 1回路基板 2の上面 21と対向する。さらに、 第 1半導体チップ 3を第 1回路基板 2に押圧した状態で、第 1半導体チップ 3を加熱し 、第 1半導体チップ 3をバンプ 33を挟んで第 1回路基板 2と電気的に接続する。これ により、封止樹脂 34が熱により硬化して、第 1半導体チップ 3が第 1回路基板 2に接 合され、実装される (ステップ S13)。以下では、第 1回路基板 2と第 1回路基板 2に実 装された第 1半導体チップ 3をまとめて「メモリモジュール」という。 Next, the lower surface 32 of the first semiconductor chip 3 is held facing the upper surface 21 of the first circuit board 2 by a mounting apparatus (not shown). Then, the bump 33 is connected to the electrode 211 through the sealing resin 34. After the position of the first semiconductor chip 3 is adjusted so as to face the first semiconductor chip 3, the first semiconductor chip 3 is pressed against the first circuit board 2. At this time, only a part of the lower surface 32 of the first semiconductor chip 3 (a frame-shaped region along the outer periphery of the lower surface 32) faces the upper surface 21 of the first circuit board 2. Further, in a state where the first semiconductor chip 3 is pressed against the first circuit board 2, the first semiconductor chip 3 is heated, and the first semiconductor chip 3 is electrically connected to the first circuit board 2 with the bumps 33 interposed therebetween. . As a result, the sealing resin 34 is cured by heat, and the first semiconductor chip 3 is bonded to the first circuit board 2 and mounted (step S13). Hereinafter, the first circuit board 2 and the first semiconductor chip 3 mounted on the first circuit board 2 are collectively referred to as a “memory module”.
[0029] 上述のステップ 11からステップ 13により、第 1半導体チップ 3の下面 32の一部の領 域のみが第 1回路基板 2と対向して第 1回路基板 2の上面 21に実装される。  Through steps 11 to 13 described above, only a part of the lower surface 32 of the first semiconductor chip 3 is mounted on the upper surface 21 of the first circuit board 2 so as to face the first circuit board 2.
[0030] 次に、図 4Bに示すように、第 2半導体チップ 5の下面 52の電極上にバンプ 53を形 成する(ステップ S14)。そして、第 2回路基板 4の上面 41の電極 412に、例えば NC Fなどの封止樹脂 54を貼付する。これにより、封止樹脂 54が電極 412に付与される( ステップ S 15)。  Next, as shown in FIG. 4B, bumps 53 are formed on the electrodes on the lower surface 52 of the second semiconductor chip 5 (step S14). Then, a sealing resin 54 such as NCF is attached to the electrode 412 on the upper surface 41 of the second circuit board 4. Thereby, the sealing resin 54 is applied to the electrode 412 (step S15).
[0031] 次に、実装装置の保持部で第 2半導体チップ 5の下面 52を第 2回路基板 4の上面 4 1に向けて保持する。そして、バンプ 53が封止樹脂 54を介して電極 412と対向する ように第 2半導体チップ 5の位置を調整する。さらに、第 2半導体チップ 5を第 2回路 基板 4に押圧した状態で、第 2半導体チップ 5を加熱して、第 2半導体チップ 5をバン プ 53を挟んで第 2回路基板 4と電気的に接続する。これにより、封止樹脂 54が硬化 して、第 2半導体チップ 5が第 2回路基板 4に接合され、実装される。 (ステップ S16)。 以下では、第 2回路基板 4と第 2回路基板 4に実装された第 2半導体チップ 5をまとめ て「コントローラモジユーノレ」とレ、う。  Next, the lower surface 52 of the second semiconductor chip 5 is held toward the upper surface 41 of the second circuit board 4 by the holding unit of the mounting apparatus. Then, the position of the second semiconductor chip 5 is adjusted so that the bump 53 faces the electrode 412 through the sealing resin 54. Further, in a state where the second semiconductor chip 5 is pressed against the second circuit board 4, the second semiconductor chip 5 is heated, and the second semiconductor chip 5 is electrically connected to the second circuit board 4 with the bump 53 interposed therebetween. Connecting. Thereby, the sealing resin 54 is cured, and the second semiconductor chip 5 is bonded to the second circuit board 4 and mounted. (Step S16). Hereinafter, the second circuit board 4 and the second semiconductor chip 5 mounted on the second circuit board 4 are collectively referred to as “controller module”.
[0032] 上述のステップ 14からステップ 16により、第 2半導体チップ 5が第 2回路基板 4の上 面 41に実装される。  The second semiconductor chip 5 is mounted on the upper surface 41 of the second circuit board 4 by the above-described Step 14 to Step 16.
[0033] 次に、検查装置(図示せず)で、メモリモジュールとコントローラモジュールの電気的 な検查を行う。すなわち、第 1回路基板 2を介してメモリモジュールに電気を流すこと により、第 1半導体チップ 3の第 1回路基板 2に対する実装の良否、例えば第 1半導 体チップ 3と第 1回路基板 2との電気的接続の良否や第 1半導体チップ 3が正常に作 動するか否かなどが電気的に検査される (ステップ S17)。また、第 2回路基板 4を介 してコントローラモジュールに電気を流すことにより、第 2半導体チップ 5の第 2回路基 板 4に対する実装の良否が電気的に検査される(ステップ S18)。 [0033] Next, an electrical inspection of the memory module and the controller module is performed by a inspection device (not shown). That is, by passing electricity through the first circuit board 2 to the memory module, whether the first semiconductor chip 3 is mounted on the first circuit board 2 is good or bad, for example, the first semiconductor chip 3 and the first circuit board 2 The electrical connection of the first semiconductor chip 3 It is electrically inspected whether or not it moves (step S17). In addition, by passing electricity through the second circuit board 4 to the controller module, whether the second semiconductor chip 5 is mounted on the second circuit board 4 is electrically inspected (step S18).
[0034] 次に、メモリモジュールとコントローラモジュールの実装が正常であると判断されると 、図 4Cに示すように、第 2回路基板 4の上面 41にマスクを介してクリームはんだが塗 布され、電極 411と電極 413上に付与される(ステップ S19)。また、第 2半導体チップ 5の上面 51には接着剤などの固定部材 8が付与される (ステップ S20)。  Next, when it is determined that the mounting of the memory module and the controller module is normal, cream solder is applied to the upper surface 41 of the second circuit board 4 through a mask as shown in FIG. 4C. It is applied on the electrode 411 and the electrode 413 (step S19). Further, a fixing member 8 such as an adhesive is applied to the upper surface 51 of the second semiconductor chip 5 (step S20).
[0035] 次に、第 1回路基板 2の下面 22の電極 221が第 2回路基板 4の電極 411とはんだを 介して対向するように第 1回路基板 2の位置を調整する。そして、第 1回路基板 2を第 2回路基板 4上に搭載する。同様に、第 2回路基板 4の電極 413上にチップ部品 6を はんだを介して搭載する。このとき、第 2半導体チップ 5の上面 51上の固定部材 8は 、第 1半導体チップ 3の下面 32により押圧される。そして、図 2に示すように、固定部 材 8は、第 1半導体チップ 3と第 2半導体チップ 5との間の空間から第 2半導体チップ 5 の周囲の空間にまで広がり、この状態で硬化する。その後、メモリモジュール、コント ローラモジュールとチップ部品 6のリフローを行う。これにより、第 1半導体チップ 3の 下面 32の中央近傍の領域 (第 1半導体チップ 3の下面 32のうち、第 1回路基板 2と対 向する一部の領域以外の他の一部の領域)を第 2半導体チップ 5の上面 51と対向さ せて、第 1回路基板 2の下面 22の電極 221が第 2回路基板 4の上面 41の電極 411と 接合される。また、チップ部品 6の電極が第 2回路基板 4の電極 413と接合される(ス テツプ S21)。  Next, the position of the first circuit board 2 is adjusted so that the electrode 221 on the lower surface 22 of the first circuit board 2 faces the electrode 411 of the second circuit board 4 via solder. Then, the first circuit board 2 is mounted on the second circuit board 4. Similarly, the chip component 6 is mounted on the electrode 413 of the second circuit board 4 via solder. At this time, the fixing member 8 on the upper surface 51 of the second semiconductor chip 5 is pressed by the lower surface 32 of the first semiconductor chip 3. Then, as shown in FIG. 2, the fixing member 8 extends from the space between the first semiconductor chip 3 and the second semiconductor chip 5 to the space around the second semiconductor chip 5, and is cured in this state. . Then, reflow the memory module, controller module, and chip component 6. As a result, an area near the center of the lower surface 32 of the first semiconductor chip 3 (a part of the lower surface 32 of the first semiconductor chip 3 other than a part of the area facing the first circuit board 2). The electrode 221 on the lower surface 22 of the first circuit board 2 is joined to the electrode 411 on the upper surface 41 of the second circuit board 4 with the upper surface 51 facing the second semiconductor chip 5. In addition, the electrode of the chip component 6 is bonded to the electrode 413 of the second circuit board 4 (step S21).
[0036] 次に、カバー部 7を、その凹部 71の開口を介してメモリモジュールとチップ部品 6が 接合された第 2回路基板 4に取り付ける。これにより、第 2回路基板 4の上面 41側に おいて第 1半導体チップ 3、第 1回路基板 2、第 2半導体チップ 5とチップ部品 6が力 バー部 7で覆われ、メモリカード 1が作製される(ステップ S22)。  Next, the cover portion 7 is attached to the second circuit board 4 to which the memory module and the chip component 6 are joined through the opening of the recess 71. As a result, the first semiconductor chip 3, the first circuit board 2, the second semiconductor chip 5, and the chip component 6 are covered with the force bar portion 7 on the upper surface 41 side of the second circuit board 4, and the memory card 1 is manufactured. (Step S22).
[0037] さらに、上記メモリカード 1の製造では、ステップ S17において第 1半導体チップ 3の 第 1回路基板 2に対する実装不良が検出された場合、他の正常なメモリモジュールが 準備され正常なモジュール同士が接合される。同様に、ステップ S18において第 2半 導体チップ 5の第 2回路基板 4に対する実装不良が検出された場合、他の正常なコン トローラモジュールが準備され正常なモジュール同士が接合される。また、実装不良 が検出されたモジュールに対してはリペア作業 (例えば、半導体チップの接合解除や 再実装)が行われる。 [0037] Further, in the manufacture of the memory card 1, when a mounting failure of the first semiconductor chip 3 to the first circuit board 2 is detected in step S17, other normal memory modules are prepared and the normal modules are connected to each other. Be joined. Similarly, if a mounting failure of the second semiconductor chip 5 to the second circuit board 4 is detected in step S18, another normal component is detected. Troller modules are prepared and normal modules are joined together. In addition, repair work (for example, semiconductor chip unbonding or re-mounting) is performed on modules for which defective mounting has been detected.
[0038] 以上に説明したように、第 1の実施の形態によれば、第 1半導体チップ 3の下面 32 の一部の領域のみが、対向する第 1回路基板 2の上面 21に実装される。そして、第 1 回路基板 2を第 2回路基板 4の上面 41に接合することにより、第 1半導体チップ 3の 下面 32の上記一部の領域以外の他の一部の領域が、第 2回路基板 4の上面 41に 実装された第 2半導体チップ 5と対向する。この結果、第 1半導体チップ 3と第 2半導 体チップ 5とを、その間に別の回路基板を挟むことなく重ねて配置できるため、メモリ カード 1の小型化と薄型化を実現することができる。  As described above, according to the first embodiment, only a partial region of the lower surface 32 of the first semiconductor chip 3 is mounted on the upper surface 21 of the opposing first circuit board 2. . Then, by joining the first circuit board 2 to the upper surface 41 of the second circuit board 4, a part of the other area of the lower surface 32 of the first semiconductor chip 3 other than the part of the second circuit board 4 It faces the second semiconductor chip 5 mounted on the upper surface 41 of 4. As a result, since the first semiconductor chip 3 and the second semiconductor chip 5 can be stacked without interposing another circuit board therebetween, the memory card 1 can be reduced in size and thickness. .
[0039] また、第 1の実施の形態によれば、第 1半導体チップ 3を第 1回路基板に、第 2半導 体チップ 5を第 2回路基板 4に実装し、それぞれをモジュールィヒした状態で積層する 。そのため、両モジュールを積層する前に、各モジュールの電気的検査を行い、第 1 半導体チップ 3と第 2半導体チップ 5の実装の良否を個別に検査できる。その結果、 実装不良をメモリモジュールとコントローラモジュールの積層前に検出できるので、生 産コストが低減する。  [0039] According to the first embodiment, the first semiconductor chip 3 is mounted on the first circuit board, the second semiconductor chip 5 is mounted on the second circuit board 4, and each is modularized. Laminate in state. Therefore, before stacking both modules, each module can be electrically inspected, and the mounting quality of the first semiconductor chip 3 and the second semiconductor chip 5 can be individually inspected. As a result, mounting defects can be detected before the memory module and controller module are stacked, reducing production costs.
[0040] 一方、従来、半導体チップを、例えばワイヤボンディングにより回路基板に実装する 場合、実装後に半導体チップとワイヤを、例えば粘度が低い熱硬化性樹脂などにより 封止するステップが必要となる。そこで、通常、回路基板の上面側で半導体チップな どを覆って熱硬化性樹脂を成形し、メモリカードのカバー部を形成する場合がある。  [0040] On the other hand, conventionally, when a semiconductor chip is mounted on a circuit board by wire bonding, for example, a step of sealing the semiconductor chip and the wire after mounting with, for example, a thermosetting resin having a low viscosity is required. Therefore, there is a case where a cover portion of a memory card is usually formed by forming a thermosetting resin by covering a semiconductor chip or the like on the upper surface side of the circuit board.
[0041] これに対して、第 1の実施の形態では、第 1半導体チップ 3と第 2半導体チップ 5を、 バンプ 33、 53を挟んで第 1回路基板 2と第 2回路基板 4にフリップチップ実装する。そ のため、必ずしも熱硬化性樹脂などにより第 1半導体チップ 3、第 2半導体チップ 5と 第 1回路基板 2などを封止したり、カバー部を形成する必要がない。その結果、カバ 一部 7の材料や形成方法の選択の自由度が向上する。また、第 1半導体チップ 3と第 2半導体チップ 5のフリップチップ実装により、ワイヤボンディング実装に比べて、実装 時の信頼性が向上する。さらに、第 1半導体チップ 3と第 2半導体チップ 5を封止樹脂 34、 54を介して回路基板に実装するため、各半導体チップと各回路基板との電気的 接続部を別途封止するステップの省略により、メモリカード 1の製造を簡素化すること ができる。また、成型部品からなるカバー部 7で第 1半導体チップ 3、第 1回路基板 2と 第 2半導体チップ 5などを覆う構成により、熱硬化性樹脂などで封止してカバー部を 形成する場合に比べて、メモリカード 1の製造をより簡素化することができる。 On the other hand, in the first embodiment, the first semiconductor chip 3 and the second semiconductor chip 5 are flip-chip connected to the first circuit board 2 and the second circuit board 4 with the bumps 33 and 53 interposed therebetween. Implement. Therefore, it is not always necessary to seal the first semiconductor chip 3, the second semiconductor chip 5, and the first circuit board 2 with a thermosetting resin or the like or to form a cover portion. As a result, the degree of freedom in selecting the material and formation method of the cover part 7 is improved. Further, the flip chip mounting of the first semiconductor chip 3 and the second semiconductor chip 5 improves the reliability during mounting compared to the wire bonding mounting. Furthermore, since the first semiconductor chip 3 and the second semiconductor chip 5 are mounted on the circuit board via the sealing resins 34 and 54, the electrical connection between each semiconductor chip and each circuit board is achieved. Manufacturing of the memory card 1 can be simplified by omitting the step of separately sealing the connection portion. Also, when the cover part 7 made of molded parts covers the first semiconductor chip 3, the first circuit board 2 and the second semiconductor chip 5, etc., when the cover part is formed by sealing with a thermosetting resin or the like. In comparison, the manufacturing of the memory card 1 can be further simplified.
[0042] また、第 1の実施の形態では、第 1半導体チップ 3の下面 32の外周に沿う額縁状の 領域で第 1回路基板 2と接合するため、第 1半導体チップ 3を第 1回路基板 2に強固 に固定することができる。そして、第 1半導体チップ 3の下面 32と第 2半導体チップ 5 の上面 51とを接着剤からなる固定部材 8でさらに固定するため、第 1半導体チップ 3 を第 2回路基板 4に間接的により強固に固定することができる。  In the first embodiment, the first semiconductor chip 3 is joined to the first circuit board 2 in a frame-like region along the outer periphery of the lower surface 32 of the first semiconductor chip 3. 2 can be firmly fixed. Then, in order to further fix the lower surface 32 of the first semiconductor chip 3 and the upper surface 51 of the second semiconductor chip 5 with the fixing member 8 made of an adhesive, the first semiconductor chip 3 is indirectly and firmly fixed to the second circuit board 4. Can be fixed to.
[0043] (第 2の実施の形態)  [0043] (Second embodiment)
以下に、本発明の第 2の実施の形態に係るメモリカードについて、図 5と図 6を用い て説明する。  Hereinafter, a memory card according to a second embodiment of the present invention will be described with reference to FIGS.
[0044] 図 5は、本発明の第 2の実施の形態に係るメモリカード laの構成を示す平面図であ り、図 6は、メモリカード l aを図 5の 6— 6線の位置で切断した断面図である。図 5では 、メモリカード laの内部構造の理解を容易にするために、カバー部 7aについては輪 郭のみを破線で示している。また、図 5では、半導体チップの実装などに利用される 封止樹脂は図示していない。  FIG. 5 is a plan view showing the configuration of the memory card la according to the second embodiment of the present invention. FIG. 6 is a cross-sectional view of the memory card la taken along line 6-6 in FIG. FIG. In FIG. 5, in order to facilitate understanding of the internal structure of the memory card la, only the outline of the cover portion 7a is indicated by a broken line. In FIG. 5, the sealing resin used for mounting the semiconductor chip is not shown.
[0045] 図 5と図 6に示すように、メモリカード laは、図 1と図 2に示すメモリカード 1の第 1回 路基板 2とは形状が異なる第 1回路基板 2aを備える。また、メモリカード laは、熱可塑 性樹脂により形成されたカバー部 7aを備える。その他の構成は図 1と図 2と同様であ り、同じ符号を付して説明する。また、メモリカード laの製造方法の流れは、第 1の実 施の形態とほぼ同様であるため説明を簡略化する。  As shown in FIGS. 5 and 6, the memory card la includes a first circuit board 2a having a shape different from that of the first circuit board 2 of the memory card 1 shown in FIGS. The memory card la includes a cover portion 7a formed of a thermoplastic resin. Other configurations are the same as those in FIGS. 1 and 2, and will be described with the same reference numerals. Further, the flow of the method for manufacturing the memory card la is almost the same as that of the first embodiment, so the description will be simplified.
[0046] 図 5と図 6に示すように、第 1回路基板 2aは、図 1に示す外周と内周が矩形状の額 縁状基板からなる第 1回路基板 2の右側が開口した、いわゆるコの字型の形状を有 する。そして、メモリカード laは、第 1半導体チップ 3の下面 32の互いに対向する 1組 のエッジおよびその 1組のエッジに直交する 1つのエッジ近傍の領域力 第 1回路基 板 2aの上面 21と対向している。そのため、第 2半導体チップ 5の一部は、第 1半導体 チップ 3と重なっていなレ、。すなわち、メモリカード laは、第 2半導体チップ 5の上面 5 1の一部のみが、第 1半導体チップ 3の下面 32の第 1回路基板 2aと対向した一部の 領域以外の他の一部の領域と対向する構成を有する。 [0046] As shown in FIGS. 5 and 6, the first circuit board 2a is a so-called open circuited circuit board having a rectangular outer periphery and inner periphery shown in FIG. It has a U-shaped shape. Then, the memory card la faces a pair of edges of the lower surface 32 of the first semiconductor chip 3 facing each other and a region force in the vicinity of one edge orthogonal to the one set of edges, and faces the upper surface 21 of the first circuit board 2a. is doing. Therefore, a part of the second semiconductor chip 5 does not overlap the first semiconductor chip 3. That is, the memory card la is the upper surface 5 of the second semiconductor chip 5. Only a part of 1 has a configuration facing a part of the region other than a part of the bottom surface 32 of the first semiconductor chip 3 facing the first circuit board 2a.
[0047] 以下、本発明の第 2の実施の形態に係るメモリカード laの製造方法について、第 1 の実施の形態と同様に図 3Aと図 3Bを参照しながら説明する。 Hereinafter, a method for manufacturing a memory card la according to the second embodiment of the present invention will be described with reference to FIGS. 3A and 3B, as in the first embodiment.
[0048] まず、第 1半導体チップ 3の下面 32の電極上にバンプ 33を形成し、第 1回路基板 2 aの上面 21の電極 211に封止樹脂 34を付与する(ステップ S 11、 S 12)。 [0048] First, bumps 33 are formed on the electrodes on the lower surface 32 of the first semiconductor chip 3, and the sealing resin 34 is applied to the electrodes 211 on the upper surface 21 of the first circuit board 2a (steps S11 and S12). ).
[0049] 次に、第 1半導体チップ 3をバンプ 33を挟んで第 1回路基板 2aに電気的に接続す るとともに、封止樹脂 34を硬化して第 1半導体チップ 3を第 1回路基板 2aに接合する[0049] Next, the first semiconductor chip 3 is electrically connected to the first circuit board 2a with the bumps 33 interposed therebetween, and the sealing resin 34 is cured to attach the first semiconductor chip 3 to the first circuit board 2a. To join
(ステップ S13)。上述のステップにより、第 1半導体チップ 3が第 1回路基板 2aに実装 される。 (Step S13). Through the above-described steps, the first semiconductor chip 3 is mounted on the first circuit board 2a.
[0050] 次に、第 2半導体チップ 5の下面 52の電極上にバンプ 53を形成し、第 2回路基板 4 の上面 41の電極 412に封止樹脂 54を付与する(ステップ S 14、 S 15)。  [0050] Next, bumps 53 are formed on the electrodes on the lower surface 52 of the second semiconductor chip 5, and the sealing resin 54 is applied to the electrodes 412 on the upper surface 41 of the second circuit board 4 (steps S14 and S15). ).
[0051] 次に、第 2半導体チップ 5をバンプ 53を挟んで第 2回路基板 4に電気的に接続する とともに、封止樹脂 54を硬化して第 2半導体チップ 5を第 2回路基板 4に接合する (ス テツプ S16)。上述のステップにより、第 2半導体チップ 5が第 2回路基板 4の上面 41 に実装される。  [0051] Next, the second semiconductor chip 5 is electrically connected to the second circuit board 4 with the bumps 53 interposed therebetween, and the sealing resin 54 is cured so that the second semiconductor chip 5 is attached to the second circuit board 4. Join (Step S16). Through the above steps, the second semiconductor chip 5 is mounted on the upper surface 41 of the second circuit board 4.
[0052] 次に、第 1半導体チップ 3の第 1回路基板 2aに対する実装の良否が第 1回路基板 2 aを介して電気的に検査される (ステップ S17)。同様に、第 2半導体チップ 5の第 2回 路基板 4に対する実装の良否が第 2回路基板 4を介して電気的に検査される (ステツ プ S18)。  Next, whether or not the first semiconductor chip 3 is mounted on the first circuit board 2a is electrically inspected via the first circuit board 2a (step S17). Similarly, whether the second semiconductor chip 5 is mounted on the second circuit board 4 is electrically inspected via the second circuit board 4 (step S18).
[0053] 次に、第 2回路基板 4の上面 41の電極 411と電極 413にはんだを付与する(ステツ プ S19)。また、第 2半導体チップ 5の上面 51に接着剤からなる固定部材 8を付与す る(ステップ S20)。そして、第 1回路基板 2aとチップ部品 6を第 2回路基板 4上に搭載 してリフローすることにより、第 1回路基板 2aとチップ部品 6を第 2回路基板 4に接合 する(ステップ S21)。  Next, solder is applied to the electrodes 411 and 413 on the upper surface 41 of the second circuit board 4 (step S19). Further, the fixing member 8 made of an adhesive is applied to the upper surface 51 of the second semiconductor chip 5 (step S20). Then, the first circuit board 2a and the chip part 6 are mounted on the second circuit board 4 and reflowed to join the first circuit board 2a and the chip part 6 to the second circuit board 4 (step S21).
[0054] その後、例えばインサート成形などにより、第 2回路基板 4上に第 1半導体チップ 3、 第 1回路基板 2a、第 2半導体チップ 5とチップ部品 6を覆う熱可塑性樹脂を成形して カバー部 7aを形成する。上記各ステップにより、メモリカード laは作製される。 [0055] 以上に説明したように、第 2の実施の形態によれば、第 1の実施の形態と同様に、 第 1半導体チップ 3と第 2半導体チップ 5とを、その間に回路基板を挟むことなく重ね て配置できるため、メモリカード laの小型化と薄型化を実現することができる。このと き、メモリカード laの小型化と薄型化の観点から、第 2半導体チップ 5の少なくとも一 部が、第 1半導体チップ 3の下面 32の第 1回路基板 2aと対向する一部の領域以外の 他の一部の領域と対向してレ、ればよレ、。 [0054] Thereafter, a thermoplastic resin covering the first semiconductor chip 3, the first circuit board 2a, the second semiconductor chip 5 and the chip component 6 is formed on the second circuit board 4 by, for example, insert molding, and the cover portion. 7a is formed. The memory card la is manufactured through the above steps. [0055] As described above, according to the second embodiment, as in the first embodiment, the first semiconductor chip 3 and the second semiconductor chip 5 are sandwiched between them. Therefore, the memory card la can be reduced in size and thickness. At this time, from the viewpoint of miniaturization and thinning of the memory card la, at least a part of the second semiconductor chip 5 is other than a part of the region facing the first circuit board 2a on the lower surface 32 of the first semiconductor chip 3. The other part of the area is opposed to it.
[0056] また、第 2の実施の形態によれば、メモリモジュールとコントローラモジュールを積層 する前に検査し、第 1半導体チップ 3と第 2半導体チップ 5の実装の良否を個別に検 查できるため、生産性や生産コストを低減できる。  [0056] Further, according to the second embodiment, since the memory module and the controller module are inspected before being stacked, it is possible to individually determine whether the first semiconductor chip 3 and the second semiconductor chip 5 are mounted correctly. , Productivity and production cost can be reduced.
[0057] また、第 2の実施の形態によれば、第 1の実施の形態と同様に、第 1半導体チップ 3 と第 2半導体チップ 5をフリップチップ実装することにより、カバー部 7aの材料や形成 方法の選択の自由度を向上することができる。また、第 1半導体チップ 3と第 2半導体 チップ 5のフリップチップ実装により、ワイヤボンディング実装に比べて、実装時の信 頼性が向上する。さらに、第 1半導体チップ 3の下面 32の 3つのエッジ近傍の領域で 第 1回路基板 2aと接合するため、第 1半導体チップ 3を第 1回路基板 2aに強固に固 定すること力 Sできる。また、接着剤からなる固定部材 8で第 1半導体チップ 3を第 2回 路基板 4に間接的により強固に固定することができる。  [0057] Also, according to the second embodiment, as in the first embodiment, the first semiconductor chip 3 and the second semiconductor chip 5 are flip-chip mounted, so that the material of the cover portion 7a The degree of freedom in selecting the formation method can be improved. Also, the flip chip mounting of the first semiconductor chip 3 and the second semiconductor chip 5 improves the reliability during mounting compared to wire bonding mounting. Further, since the first semiconductor substrate 3 is bonded to the first circuit board 2a in the regions near the three edges of the lower surface 32 of the first semiconductor chip 3, the force S can be firmly fixed to the first circuit board 2a. Further, the first semiconductor chip 3 can be indirectly and firmly fixed to the second circuit board 4 by the fixing member 8 made of an adhesive.
[0058] また、第 2の実施の形態によれば、特に、カバー部 7aを熱可塑性樹脂で形成するこ とにより、カバー部 7aの硬さを低減し、安全性などの信頼性を高めることができる。  [0058] Also, according to the second embodiment, in particular, the cover portion 7a is formed of a thermoplastic resin, thereby reducing the hardness of the cover portion 7a and increasing the reliability such as safety. Can do.
[0059] 以上、本発明の各実施の形態について説明してきたが、本発明は上記実施の形態 に限定されるものではなぐ以下に示すように様々な変更が可能である。  [0059] While the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible as shown below.
[0060] すなわち、上記各実施の形態では、第 1半導体チップ 3と第 2半導体チップ 5をメモ リチップとコントロールチップを例に説明した力 S、これに限られない。例えば、 ASICな どの他のベアチップを第 1半導体チップ 3と第 2半導体チップ 5として用いてもよレ、。さ らに、第 1半導体チップ 3と第 2半導体チップ 5として 2つのメモリチップを積層して、第 2回路基板 4の他の領域に実装したコントロールチップにより 2つのメモリチップを制 御する構成としてもよレ、。また、第 2半導体チップ 5として、情報の記憶と他のメモリチ ップを制御するメモリ'コントローラ兼用チップを第 2回路基板 4に実装してもよい。こ のとき、半導体チップは、部分的に半導体機能を利用したチップであれば、全体が半 導体機能を有するチップでなくてもよい。 That is, in each of the above-described embodiments, the force S described using the first semiconductor chip 3 and the second semiconductor chip 5 as an example of the memory chip and the control chip is not limited to this. For example, other bare chips such as ASIC may be used as the first semiconductor chip 3 and the second semiconductor chip 5. Furthermore, two memory chips are stacked as the first semiconductor chip 3 and the second semiconductor chip 5, and the two memory chips are controlled by a control chip mounted on another area of the second circuit board 4. Moyore. Further, as the second semiconductor chip 5, a memory / controller combined chip for storing information and controlling other memory chips may be mounted on the second circuit board 4. This At this time, the semiconductor chip may not be a chip having a semiconductor function as a whole as long as it is a chip partially utilizing a semiconductor function.
[0061] また、上記各実施の形態では、第 1半導体チップ 3を、その下面 32の外周に沿う額 縁状の領域や下面 32の 3つのエッジ近傍の領域で第 1回路基板に接合する例で説 明したが、これに限られなレ、。例えば、図 7に示すメモリカード lbのように、互いに平 行な 2枚の基板からなる第 1回路基板 2bを第 2回路基板 4上に接合し、第 1半導体チ ップ 3の下面の互いに対向する 1組のエッジ近傍の領域で、第 1回路基板 2bと対向し て接合する構成としてもよい。  In each of the above embodiments, the first semiconductor chip 3 is bonded to the first circuit board in a frame-like region along the outer periphery of the lower surface 32 or in a region near the three edges of the lower surface 32. I explained in, but this is limited to this. For example, as in the memory card lb shown in FIG. 7, a first circuit board 2b composed of two parallel boards is bonded onto the second circuit board 4, and the lower surfaces of the first semiconductor chip 3 are connected to each other. A configuration may be adopted in which the first circuit board 2b is opposed and joined in a region in the vicinity of a pair of opposing edges.
[0062] また、上記各実施の形態では、バンプ 33、 53を第 1半導体チップ 3の電極上と第 2 半導体チップの電極上に形成した例で説明したが、それぞれを第 1回路基板 2の電 極 211上と第 2回路基板 4の電極 412上に形成してもよレ、。さらに、ノ ンプ 33、 53とし て、ボールバンプ以外に、他の種類のボールバンプゃメツキバンプ、はんだバンプな どを用いてもよい。  In each of the above embodiments, the bumps 33 and 53 are described as examples formed on the electrodes of the first semiconductor chip 3 and the electrodes of the second semiconductor chip. It may be formed on the electrode 211 and on the electrode 412 of the second circuit board 4. In addition to the ball bumps, other types of ball bumps such as solder bumps, solder bumps, and the like may be used as the bumps 33 and 53.
[0063] また、上記各実施の形態では、封止樹脂として、 NCFなどの貼付を例に説明した 力 Sこれに限られない。例えば、非導電性樹脂ペーストの塗布、異方導電性樹脂フィ ルムゃ異方導電性樹脂ペーストを用いて封止樹脂を形成してもよい。  [0063] Further, in each of the above embodiments, the force S described as an example of sticking NCF or the like as the sealing resin is not limited to this. For example, the sealing resin may be formed using a non-conductive resin paste, an anisotropic conductive resin film, or an anisotropic conductive resin paste.
[0064] また、上記各実施の形態では、第 1半導体チップ 3の第 1回路基板の実装後に、第 2半導体チップ 5の第 2回路基板 4の実装を行う例で説明したが、これに限られない。 例えば、第 2半導体チップ 5の第 2回路基板 4の実装を、第 1半導体チップ 3の第 1回 路基板の実装と並行して行ってもよぐ第 1半導体チップ 3の実装よりも前に行っても よい。同様に、第 1半導体チップ 3の第 1回路基板の実装の良否の検査を、第 2半導 体チップ 5の第 2回路基板 4の実装よりも前に行っても、第 2半導体チップ 5の実装と 並行して行ってもよレ、。  Further, in each of the above embodiments, the example in which the second circuit board 4 of the second semiconductor chip 5 is mounted after the first circuit board of the first semiconductor chip 3 is mounted has been described. I can't. For example, the mounting of the second circuit board 4 of the second semiconductor chip 5 may be performed in parallel with the mounting of the first circuit board of the first semiconductor chip 3 before the mounting of the first semiconductor chip 3. You may go. Similarly, whether the mounting of the first circuit board of the first semiconductor chip 3 is inspected before the mounting of the second circuit board 4 of the second semiconductor chip 5 is performed. You can go in parallel with the implementation.
[0065] また、上記各実施の形態では、第 1半導体チップと第 2半導体チップをフリップチッ プ実装する例で説明したが、これに限られない。必要に応じて、第 1半導体チップ 3 の第 1回路基板への実装や第 2半導体チップ 5の第 2回路基板 4への実装の少なくと も一方をワイヤボンディングにより行ってもよレ、。ただし、実装の信頼性向上やカバー 部の材料や形成方法の選択の自由度を向上させる点から、第 1半導体チップ 3と第 2 半導体チップ 5をフリップチップ実装で回路基板に実装することが好ましい。 In each of the above embodiments, the example in which the first semiconductor chip and the second semiconductor chip are flip-chip mounted has been described. However, the present invention is not limited to this. If necessary, at least one of mounting the first semiconductor chip 3 on the first circuit board and mounting the second semiconductor chip 5 on the second circuit board 4 may be performed by wire bonding. However, the first semiconductor chip 3 and the second semiconductor chip 2 are improved in terms of improving the mounting reliability and improving the degree of freedom in selecting the cover material and the forming method. The semiconductor chip 5 is preferably mounted on the circuit board by flip chip mounting.
[0066] また、上記各実施の形態では、カバー部を熱可塑性樹脂で形成する例で説明した 、これに限られない。必要に応じて、熱硬化性樹脂などの成形によりカバー部を形 成してもよレ、。ただし、メモリカードの製造をより簡素化するという点から、カバー部を 成型部品とすることが好ましい。また、カバー部の硬さを低減して安全性を高めるとい う点から、カバー部を熱可塑性樹脂で成形することが好ましい。 [0066] Further, in each of the above-described embodiments, the example in which the cover portion is formed of a thermoplastic resin has been described. However, the present invention is not limited to this. If necessary, the cover may be formed by molding a thermosetting resin. However, it is preferable to use the cover part as a molded part from the viewpoint of simplifying the production of the memory card. In addition, it is preferable to mold the cover portion with a thermoplastic resin from the viewpoint of reducing the hardness of the cover portion and increasing the safety.
[0067] なお、本発明のメモリカードは、 SDカード以外の、例えば ICカードなどの他のカー ド型記録媒体として利用してもよレ、。 [0067] It should be noted that the memory card of the present invention may be used as another card type recording medium other than an SD card, such as an IC card.
産業上の利用可能性  Industrial applicability
[0068] 本発明は、情報を記録する、特に小型化や薄型化が要望されるメモリカードなどの 技術分野に有用である。 The present invention is useful in a technical field such as a memory card that records information, and that is particularly required to be reduced in size and thickness.

Claims

請求の範囲 The scope of the claims
[1] 第 1回路基板と、  [1] a first circuit board;
前記第 1回路基板の上面に実装されるとともに下面の一部の領域のみが前記第 1回 路基板と対向する第 1半導体チップと、  A first semiconductor chip mounted on the upper surface of the first circuit board and having only a part of the lower surface facing the first circuit board;
上面に前記第 1回路基板の下面が接合された第 2回路基板と、  A second circuit board having the upper surface joined to the lower surface of the first circuit board;
前記第 2回路基板の前記上面に実装されるとともに少なくとも一部が前記第 1半導体 チップの前記下面の前記一部の領域以外の他の一部の領域と対向する第 2半導体 チップと、  A second semiconductor chip mounted on the upper surface of the second circuit board and at least a portion facing a part of the other region other than the part of the lower surface of the first semiconductor chip;
前記第 2回路基板の前記上面側において前記第 1半導体チップ、前記第 1回路基板 と前記第 2半導体チップを覆うカバー部と、  A cover portion covering the first semiconductor chip, the first circuit board and the second semiconductor chip on the upper surface side of the second circuit board;
を備えることを特徴とするメモリカード。  A memory card comprising:
[2] 前記第 1半導体チップがバンプを挟んで前記第 1回路基板に実装されており、前記 第 2半導体チップがバンプを挟んで前記第 2回路基板に実装されていることを特徴と する請求項 1に記載のメモリカード。 [2] The first semiconductor chip is mounted on the first circuit board with a bump interposed therebetween, and the second semiconductor chip is mounted on the second circuit board with a bump interposed therebetween. Item 1. A memory card according to item 1.
[3] 前記カバー部が、前記第 1半導体チップ、前記第 1回路基板と前記第 2半導体チッ プを収容する凹部を有するとともに前記凹部の開口を介して前記第 2回路基板に取 り付けられる成型部品からなることを特徴とする請求項 1に記載のメモリカード。 [3] The cover has a recess for accommodating the first semiconductor chip, the first circuit board, and the second semiconductor chip, and is attached to the second circuit board through the opening of the recess. 2. The memory card according to claim 1, comprising a molded part.
[4] 前記カバー部が、前記第 2回路基板上において前記第 1半導体チップ、前記第 1回 路基板と前記第 2半導体チップを覆うように成形された熱可塑性樹脂からなることを 特徴とする請求項 1に記載のメモリカード。 [4] The cover portion is made of a thermoplastic resin formed on the second circuit board so as to cover the first semiconductor chip, the first circuit board, and the second semiconductor chip. The memory card according to claim 1.
[5] 前記第 1半導体チップの前記下面と前記第 2半導体チップの上面との間に設けられ[5] Provided between the lower surface of the first semiconductor chip and the upper surface of the second semiconductor chip.
、前記第 1半導体チップと前記第 2半導体チップとを互いに固定する固定部材をさら に備えることを特徴とする請求項 1に記載のメモリカード。 2. The memory card according to claim 1, further comprising a fixing member that fixes the first semiconductor chip and the second semiconductor chip to each other.
[6] 前記第 1半導体チップの前記下面が矩形であり、前記下面において少なくとも互い に対向する 1組のエッジ近傍の領域が、前記第 1回路基板と対向することを特徴とす る請求項 1に記載のメモリカード。 [6] The lower surface of the first semiconductor chip is rectangular, and at least one pair of edges in the vicinity of the edges facing each other on the lower surface is opposed to the first circuit board. Memory card as described in
[7] 前記第 1半導体チップの前記下面の外周に沿う額縁状の領域が前記第 1回路基板と 対向することを特徴とする請求項 6に記載のメモリカード。 7. The memory card according to claim 6, wherein a frame-like region along the outer periphery of the lower surface of the first semiconductor chip faces the first circuit board.
[8] 前記第 1半導体チップが情報を記憶するメモリチップであり、 [8] The first semiconductor chip is a memory chip for storing information,
前記第 2半導体チップが前記第 1半導体チップを制御するコントロールチップである ことを特徴とする請求項 1に記載のメモリカード。  2. The memory card according to claim 1, wherein the second semiconductor chip is a control chip that controls the first semiconductor chip.
[9] a)第 1半導体チップの下面の一部の領域のみを第 1回路基板と対向させて前記第 1 回路基板の上面に実装するステップと、 [9] a) mounting only a part of the lower surface of the first semiconductor chip on the upper surface of the first circuit board so as to face the first circuit board;
b)第 2回路基板の上面に第 2半導体チップを実装するステップと、  b) mounting a second semiconductor chip on the upper surface of the second circuit board;
c)前記第 2半導体チップの少なくとも一部を前記第 1半導体チップの前記下面の前 記一部の領域以外の他の一部の領域と対向させて前記第 2回路基板の前記上面に 接合するステップと、  c) At least a part of the second semiconductor chip is bonded to the upper surface of the second circuit board so as to face a part of the other area other than the partial area of the lower surface of the first semiconductor chip. Steps,
d)前記第 2回路基板の前記上面側において前記第 1半導体チップ、前記第 1回路 基板と前記第 2半導体チップをカバー部で覆うステップと、  d) covering the first semiconductor chip, the first circuit board and the second semiconductor chip with a cover portion on the upper surface side of the second circuit board;
を含むことを特徴とするメモリカードの製造方法。  A method for manufacturing a memory card, comprising:
[10] 前記 a)ステップが、 [10] The step a)
al)前記第 1半導体チップの電極または前記第 1回路基板の電極にバンプを形成す るステップと、  al) forming bumps on the electrodes of the first semiconductor chip or the electrodes of the first circuit board;
a2)前記第 1回路基板の前記電極に封止樹脂を付与するステップと、  a2) applying a sealing resin to the electrode of the first circuit board;
a3)前記バンプを挟んで前記第 1半導体チップを前記第 1回路基板に電気的に接続 するステップと、  a3) electrically connecting the first semiconductor chip to the first circuit board across the bump; and
を備え、  With
前記 b)ステップが、  Step b)
bl)前記第 2半導体チップの電極または前記第 2回路基板の電極にバンプを形成す るステップと、  bl) forming bumps on the electrodes of the second semiconductor chip or the electrodes of the second circuit board;
b2)前記第 2回路基板の前記電極に封止樹脂を付与するステップと、  b2) applying a sealing resin to the electrode of the second circuit board;
b3)前記バンプを挟んで前記第 2半導体チップを前記第 2回路基板に電気的に接続 するステップと、  b3) electrically connecting the second semiconductor chip to the second circuit board across the bump;
を含むことを特徴とする請求項 9に記載のメモリカードの製造方法。  10. The method for manufacturing a memory card according to claim 9, further comprising:
[11] 前記 a)ステップと前記 c)ステップとの間におレ、て前記第 1半導体チップの前記第 1回 路基板に対する実装の良否を前記第 1回路基板を介して電気的に検査するステップ と、 [11] Between the steps a) and c), it is electrically inspected through the first circuit board whether the first semiconductor chip is mounted on the first circuit board. Step When,
前記 b)ステップと前記 c)ステップとの間におレ、て前記第 2半導体チップの前記第 2回 路基板に対する実装の良否を前記第 2回路基板を介して電気的に検査するステップ と、 Electrically inspecting whether the second semiconductor chip is mounted on the second circuit board through the second circuit board between the step b) and the step c);
をさらに含むことを特徴とする請求項 9に記載のメモリカードの製造方法。 The method of manufacturing a memory card according to claim 9, further comprising:
PCT/JP2007/051055 2006-02-02 2007-01-24 Memory card and memory card manufacturing method WO2007088757A1 (en)

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