WO2007088757A1 - Carte mémoire et procédé de fabrication de carte mémoire - Google Patents

Carte mémoire et procédé de fabrication de carte mémoire Download PDF

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Publication number
WO2007088757A1
WO2007088757A1 PCT/JP2007/051055 JP2007051055W WO2007088757A1 WO 2007088757 A1 WO2007088757 A1 WO 2007088757A1 JP 2007051055 W JP2007051055 W JP 2007051055W WO 2007088757 A1 WO2007088757 A1 WO 2007088757A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
semiconductor chip
memory card
chip
card according
Prior art date
Application number
PCT/JP2007/051055
Other languages
English (en)
Japanese (ja)
Inventor
Hidenobu Nishikawa
Hiroyuki Yamada
Shuichi Takeda
Atsunobu Iwamoto
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to JP2007556823A priority Critical patent/JP4946872B2/ja
Priority to US12/160,960 priority patent/US7933127B2/en
Priority to CN2007800031807A priority patent/CN101375299B/zh
Publication of WO2007088757A1 publication Critical patent/WO2007088757A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip

Definitions

  • the present invention relates to a memory card and a manufacturing method thereof.
  • a memory card incorporating a memory chip is known as one of recording media for recording information. Since memory cards are excellent in portability, they are widely used as recording media for portable electronic devices such as portable information terminals and mobile phones. These portable electronic devices have the viewpoint of improving portability, etc. The miniaturization and large capacity have been promoted year by year, and accordingly, further miniaturization of memory cards and large capacity have been required. Usually, memory cards are required to have a large capacity while satisfying the standards because their shape, size, thickness, etc. are defined by the standards.
  • a plurality of memory substrates on which memory chips are mounted are stacked and mounted on one surface of the base substrate, and a control chip for controlling the operation of the memory chip is mounted on the other surface, thereby providing a memory.
  • a technique for increasing the capacity of a card is disclosed (for example, see Patent Document 1).
  • the memory chip and the control chip are mounted on the lead frame by wire bonding. Therefore, it is necessary to seal each chip carrier, lead frame, etc. with a thermosetting resin after mounting. At this time, since a thick sealing layer that sufficiently covers the memory chip and wires is required, the memory card can be downsized. There is a limit to thinning. In addition, since a sealing step is required separately from the mounting step, there is a limit to reducing the manufacturing cost. In addition, the quality of each chip can be checked only after it has been mounted on the S lead frame with full chip strength. For this reason, when mounting defects occur in some chips, the defects cannot be detected until the mounting of the remaining chips is completed, increasing the production cost.
  • Patent Document 1 Japanese Patent Laid-Open No. 2003-108963
  • Patent Document 2 JP 2004-13738 A
  • a memory card of the present invention includes a first circuit board, a first semiconductor chip mounted on the upper surface of the first circuit board, and a partial region of the lower surface facing the first circuit board; A second circuit board in which the lower surface of the first circuit board is bonded to the upper surface; and a second circuit board that is mounted on the upper surface of the second circuit board and at least a part other than a partial region of the lower surface of the first semiconductor chip.
  • the first and second semiconductor chips can be stacked without being sandwiched between the first and second semiconductor chips, so that the memory card can be reduced in size and thickness.
  • the method of manufacturing a memory card of the present invention includes: a) a step of mounting only a partial region of the lower surface of the first semiconductor chip on the upper surface of the first circuit board so as to face the first circuit board; B) mounting the second semiconductor chip on the upper surface of the second circuit board; and c) at least a part of the second semiconductor chip other than a part of the lower surface of the first semiconductor chip. And d) covering the first semiconductor chip and the first circuit board and the second semiconductor chip with a cover on the upper surface side of the second circuit board. Includes steps and.
  • a memory card can be manufactured with high productivity by a simple method as well as downsizing and thinning.
  • FIG. 1 is a plan view showing a configuration of a memory card according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along the line 2-2 in FIG.
  • FIG. 3A is a flowchart of the method for manufacturing the memory card according to the first embodiment of the present invention.
  • FIG. 3B is a flowchart of the method for manufacturing the memory card according to the first embodiment of the present invention.
  • FIG. 4A is a diagram showing a state in the middle of the method for manufacturing the memory card according to the first embodiment of the present invention.
  • FIG. 4B is a diagram showing a state in the middle of the method of manufacturing the memory card according to the first embodiment of the present invention.
  • FIG. 4C is a diagram showing a state in the middle of the method for manufacturing the memory card according to the first embodiment of the present invention.
  • FIG. 5 is a plan view showing a configuration of a memory card according to the second embodiment of the present invention.
  • FIG. 6 is a cross-sectional view taken along the line 6-6 in FIG.
  • FIG. 7 is a plan view showing a configuration of another example of the memory card according to the second embodiment of the present invention.
  • FIG. 1 is a plan view showing the configuration of the memory card 1 according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the memory card 1 taken along the line 2-2 in FIG.
  • FIG. 1 in order to facilitate understanding of the internal structure of the memory card 1, only the outline of the cover portion 7 is indicated by a broken line.
  • the sealing resin used for mounting a semiconductor chip is not shown.
  • an SD memory card (Secure Digital memory card) will be described as an example of the memory card 1.
  • the length and width of the memory card 1 size in the horizontal and vertical directions in Fig. 1) and thickness (size in the vertical direction in Fig. 2) are 14.9 mm and 15.1 mm, respectively. 10.9 mm to 11.1 mm and 0.9 mm to 1.1 mm.
  • the respective sizes are 15 mm, 11 mm, and lm m.
  • the upper side and the lower side in FIG. 2 will be described as the upper side and the lower side of the memory card 1, respectively, but the same applies to the second embodiment described below.
  • the memory card 1 includes a first circuit board 2 and a first circuit board 2 each having an outer periphery and an inner periphery formed of a so-called square-shaped frame-shaped substrate.
  • the first semiconductor chip 3 mounted with a ball bump (so-called “stud bump”, hereinafter simply referred to as “bump”) 33 on the upper surface 21 which is the upper main surface in FIG.
  • the second circuit board 4 in which the lower surface 22 of the first circuit board 2 is bonded to the upper surface 41, the second semiconductor chip 5 mounted with the bumps 53 on the upper surface 41 of the second circuit board 4, and the second It is mounted on the upper surface 41 of the circuit board 4 using solder.
  • the thickness of the memory card 1 at the position where the first semiconductor chip 3 and the second semiconductor chip 5 are mounted is 0.6 mm or more and 0.8 mm or less (0.7 mm in the present embodiment).
  • the second circuit board 4 is a glass epoxy board equivalent to FR-4.5 and has a thickness of 0.1 mm or more and 0.4 mm or less (0.16 mm in the present embodiment). As shown in FIG. 2, the second circuit board 4 has an electrode 411 to which the first circuit board 2 is bonded, an electrode 412 to which the second semiconductor chip 5 is bonded, and an electrode 413 to which the chip component 6 is bonded. Prepare for 41. Further, the second circuit board 4 includes a plurality of external electrodes 421 on the lower surface 42 for connection with external electronic devices. The external electrode 421 is electrically connected to the wiring provided on the upper surface 41 via a through hole (not shown) communicating from the lower surface 42 of the second circuit board 4 to the upper surface 41.
  • the thickness of the first circuit board 2 is 0.1 mm or more and 0.4 mm or less (0.12 mm in the present embodiment).
  • a plurality of electrodes 211 to which the first semiconductor chip 3 is bonded are provided on the upper surface 21 of the first circuit board 2 along the inner periphery of the first circuit board 2.
  • An electrode 221 is provided on the lower surface 22 of the first circuit board 2, and the electrode 221 is joined to the electrode 411 on the upper surface 41 of the second circuit board 4 via solder.
  • the first semiconductor chip 3 and the second semiconductor chip 5 are bare chips, and the thicknesses are 0.05 mm or more and 0.3 mm or less, respectively.
  • the first semiconductor chip 3 is a memory chip for storing information
  • the second semiconductor chip 5 is a control chip for controlling the first semiconductor chip 3.
  • the first semiconductor chip 3 includes bumps 33 formed on the electrodes on the lower surface 32, and the bumps 33 are bonded to the electrodes 211 of the first circuit board 2 by the sealing resin 34 (the contact is maintained and is in a state of being removed). Included).
  • the second semiconductor chip 5 includes bumps 53 formed on the electrodes on the lower surface 52, and the bumps 53 are bonded to the electrodes 412 of the second circuit board 4 by the sealing resin 54 (the state in which the contact is maintained and is maintained). Including).
  • the sealing resins 34 and 54 a non-conductive resin film such as a film-like resin material attached to the upper surface 21 of the first circuit board 2 and the upper surface 41 of the second circuit board 4 (NCF (Non-Conductive Film)) is used.
  • NCF Non-Conductive Film
  • the bump 33 is surrounded by the sealing resin 34 interposed between the first semiconductor chip 3 and the first circuit board 2.
  • the enclosure is covered.
  • the periphery of the bump 53 is covered with a sealing resin 54 interposed between the second semiconductor chip 5 and the second circuit board 4.
  • the lower surface 32 of the first semiconductor chip 3 is rectangular, and only the frame-shaped region along the outer periphery of the lower surface 32 (the region near the two sets of edges facing each other on the lower surface 32) is the first circuit board 2. Opposite. That is, in the memory card 1, only a part of the lower surface 32 of the first semiconductor chip 3 faces the upper surface 21 of the first circuit board 2.
  • the second semiconductor chip 5 is spaced apart from the inner periphery of the first circuit board 2 and inside the first circuit board 2 (rectangular opening 20 of the first circuit board 2 (see FIG. 1)). Has been placed.
  • the upper surface 51 of the second semiconductor chip 5 is a region in the vicinity of the center of the lower surface 32 of the first semiconductor chip 3 (other than the partial region of the lower surface 32 facing the first circuit board 2). Part area).
  • the memory card 1 is provided between the lower surface 32 of the first semiconductor chip 3 and the upper surface 51 of the second semiconductor chip 5, and the first semiconductor chip 3 and the first semiconductor chip 3 2
  • a fixing member 8 such as an adhesive for fixing the semiconductor chip 5 to each other is further provided.
  • the cover portion 7 is made of a molded part made of resin, and includes a first semiconductor chip 3, a first circuit board 2, a second semiconductor chip 5, and a recess 71 that accommodates the chip part 6.
  • the force bar portion 7 is attached to the second circuit board 4 through the opening of the recess 71.
  • FIGS. 3A and 3B are flowcharts of the manufacturing method of the memory card 1
  • FIGS. 4A to 4C are diagrams showing states in the middle of the manufacturing method of the memory card 1.
  • FIG. 4A to 4C, as in FIG. 2 the memory card 1 is shown in a cross-sectional view taken along the line 2-2 in FIG.
  • bumps 33 are formed on the electrodes on the lower surface 32 of the first semiconductor chip 3 (step S 11).
  • a sealing resin 34 such as NCF is attached to the electrode 211 on the upper surface 21 of the first circuit board 2. Thereby, the sealing resin 34 is applied to the electrode 211 (step S12).
  • the lower surface 32 of the first semiconductor chip 3 is held facing the upper surface 21 of the first circuit board 2 by a mounting apparatus (not shown). Then, the bump 33 is connected to the electrode 211 through the sealing resin 34. After the position of the first semiconductor chip 3 is adjusted so as to face the first semiconductor chip 3, the first semiconductor chip 3 is pressed against the first circuit board 2. At this time, only a part of the lower surface 32 of the first semiconductor chip 3 (a frame-shaped region along the outer periphery of the lower surface 32) faces the upper surface 21 of the first circuit board 2. Further, in a state where the first semiconductor chip 3 is pressed against the first circuit board 2, the first semiconductor chip 3 is heated, and the first semiconductor chip 3 is electrically connected to the first circuit board 2 with the bumps 33 interposed therebetween.
  • the sealing resin 34 is cured by heat, and the first semiconductor chip 3 is bonded to the first circuit board 2 and mounted (step S13).
  • the first circuit board 2 and the first semiconductor chip 3 mounted on the first circuit board 2 are collectively referred to as a “memory module”.
  • step S14 bumps 53 are formed on the electrodes on the lower surface 52 of the second semiconductor chip 5 (step S14).
  • a sealing resin 54 such as NCF is attached to the electrode 412 on the upper surface 41 of the second circuit board 4. Thereby, the sealing resin 54 is applied to the electrode 412 (step S15).
  • Step S16 the second circuit board 4 and the second semiconductor chip 5 mounted on the second circuit board 4 are collectively referred to as “controller module”.
  • the second semiconductor chip 5 is mounted on the upper surface 41 of the second circuit board 4 by the above-described Step 14 to Step 16.
  • an electrical inspection of the memory module and the controller module is performed by a inspection device (not shown). That is, by passing electricity through the first circuit board 2 to the memory module, whether the first semiconductor chip 3 is mounted on the first circuit board 2 is good or bad, for example, the first semiconductor chip 3 and the first circuit board 2 The electrical connection of the first semiconductor chip 3 It is electrically inspected whether or not it moves (step S17). In addition, by passing electricity through the second circuit board 4 to the controller module, whether the second semiconductor chip 5 is mounted on the second circuit board 4 is electrically inspected (step S18).
  • cream solder is applied to the upper surface 41 of the second circuit board 4 through a mask as shown in FIG. 4C. It is applied on the electrode 411 and the electrode 413 (step S19). Further, a fixing member 8 such as an adhesive is applied to the upper surface 51 of the second semiconductor chip 5 (step S20).
  • the position of the first circuit board 2 is adjusted so that the electrode 221 on the lower surface 22 of the first circuit board 2 faces the electrode 411 of the second circuit board 4 via solder.
  • the first circuit board 2 is mounted on the second circuit board 4.
  • the chip component 6 is mounted on the electrode 413 of the second circuit board 4 via solder.
  • the fixing member 8 on the upper surface 51 of the second semiconductor chip 5 is pressed by the lower surface 32 of the first semiconductor chip 3.
  • the fixing member 8 extends from the space between the first semiconductor chip 3 and the second semiconductor chip 5 to the space around the second semiconductor chip 5, and is cured in this state. .
  • an area near the center of the lower surface 32 of the first semiconductor chip 3 (a part of the lower surface 32 of the first semiconductor chip 3 other than a part of the area facing the first circuit board 2).
  • the electrode 221 on the lower surface 22 of the first circuit board 2 is joined to the electrode 411 on the upper surface 41 of the second circuit board 4 with the upper surface 51 facing the second semiconductor chip 5.
  • the electrode of the chip component 6 is bonded to the electrode 413 of the second circuit board 4 (step S21).
  • the cover portion 7 is attached to the second circuit board 4 to which the memory module and the chip component 6 are joined through the opening of the recess 71.
  • the first semiconductor chip 3, the first circuit board 2, the second semiconductor chip 5, and the chip component 6 are covered with the force bar portion 7 on the upper surface 41 side of the second circuit board 4, and the memory card 1 is manufactured. (Step S22).
  • step S17 when a mounting failure of the first semiconductor chip 3 to the first circuit board 2 is detected in step S17, other normal memory modules are prepared and the normal modules are connected to each other. Be joined. Similarly, if a mounting failure of the second semiconductor chip 5 to the second circuit board 4 is detected in step S18, another normal component is detected. Troller modules are prepared and normal modules are joined together. In addition, repair work (for example, semiconductor chip unbonding or re-mounting) is performed on modules for which defective mounting has been detected.
  • repair work for example, semiconductor chip unbonding or re-mounting
  • the memory card 1 can be reduced in size and thickness. .
  • the first semiconductor chip 3 is mounted on the first circuit board
  • the second semiconductor chip 5 is mounted on the second circuit board 4
  • each is modularized. Laminate in state. Therefore, before stacking both modules, each module can be electrically inspected, and the mounting quality of the first semiconductor chip 3 and the second semiconductor chip 5 can be individually inspected. As a result, mounting defects can be detected before the memory module and controller module are stacked, reducing production costs.
  • thermosetting resin having a low viscosity there is a case where a cover portion of a memory card is usually formed by forming a thermosetting resin by covering a semiconductor chip or the like on the upper surface side of the circuit board.
  • the first semiconductor chip 3 and the second semiconductor chip 5 are flip-chip connected to the first circuit board 2 and the second circuit board 4 with the bumps 33 and 53 interposed therebetween.
  • the first semiconductor chip 3 and the second semiconductor chip 5 are flip-chip connected to the first circuit board 2 and the second circuit board 4 with the bumps 33 and 53 interposed therebetween.
  • it is not always necessary to seal the first semiconductor chip 3, the second semiconductor chip 5, and the first circuit board 2 with a thermosetting resin or the like or to form a cover portion.
  • the degree of freedom in selecting the material and formation method of the cover part 7 is improved.
  • the flip chip mounting of the first semiconductor chip 3 and the second semiconductor chip 5 improves the reliability during mounting compared to the wire bonding mounting.
  • the electrical connection between each semiconductor chip and each circuit board is achieved.
  • Manufacturing of the memory card 1 can be simplified by omitting the step of separately sealing the connection portion.
  • the cover part 7 made of molded parts covers the first semiconductor chip 3, the first circuit board 2 and the second semiconductor chip 5, etc., when the cover part is formed by sealing with a thermosetting resin or the like. In comparison, the manufacturing of the memory card 1 can be further simplified.
  • the first semiconductor chip 3 is joined to the first circuit board 2 in a frame-like region along the outer periphery of the lower surface 32 of the first semiconductor chip 3. 2 can be firmly fixed. Then, in order to further fix the lower surface 32 of the first semiconductor chip 3 and the upper surface 51 of the second semiconductor chip 5 with the fixing member 8 made of an adhesive, the first semiconductor chip 3 is indirectly and firmly fixed to the second circuit board 4. Can be fixed to.
  • FIG. 5 is a plan view showing the configuration of the memory card la according to the second embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of the memory card la taken along line 6-6 in FIG. FIG.
  • FIG. 5 in order to facilitate understanding of the internal structure of the memory card la, only the outline of the cover portion 7a is indicated by a broken line.
  • the sealing resin used for mounting the semiconductor chip is not shown.
  • the memory card la includes a first circuit board 2a having a shape different from that of the first circuit board 2 of the memory card 1 shown in FIGS.
  • the memory card la includes a cover portion 7a formed of a thermoplastic resin.
  • Other configurations are the same as those in FIGS. 1 and 2, and will be described with the same reference numerals. Further, the flow of the method for manufacturing the memory card la is almost the same as that of the first embodiment, so the description will be simplified.
  • the first circuit board 2a is a so-called open circuited circuit board having a rectangular outer periphery and inner periphery shown in FIG. It has a U-shaped shape.
  • the memory card la faces a pair of edges of the lower surface 32 of the first semiconductor chip 3 facing each other and a region force in the vicinity of one edge orthogonal to the one set of edges, and faces the upper surface 21 of the first circuit board 2a. is doing. Therefore, a part of the second semiconductor chip 5 does not overlap the first semiconductor chip 3. That is, the memory card la is the upper surface 5 of the second semiconductor chip 5. Only a part of 1 has a configuration facing a part of the region other than a part of the bottom surface 32 of the first semiconductor chip 3 facing the first circuit board 2a.
  • bumps 33 are formed on the electrodes on the lower surface 32 of the first semiconductor chip 3, and the sealing resin 34 is applied to the electrodes 211 on the upper surface 21 of the first circuit board 2a (steps S11 and S12). ).
  • the first semiconductor chip 3 is electrically connected to the first circuit board 2a with the bumps 33 interposed therebetween, and the sealing resin 34 is cured to attach the first semiconductor chip 3 to the first circuit board 2a.
  • Step S13 Through the above-described steps, the first semiconductor chip 3 is mounted on the first circuit board 2a.
  • bumps 53 are formed on the electrodes on the lower surface 52 of the second semiconductor chip 5, and the sealing resin 54 is applied to the electrodes 412 on the upper surface 41 of the second circuit board 4 (steps S14 and S15). ).
  • the second semiconductor chip 5 is electrically connected to the second circuit board 4 with the bumps 53 interposed therebetween, and the sealing resin 54 is cured so that the second semiconductor chip 5 is attached to the second circuit board 4.
  • Join Step S16.
  • the second semiconductor chip 5 is mounted on the upper surface 41 of the second circuit board 4.
  • step S17 whether or not the first semiconductor chip 3 is mounted on the first circuit board 2a is electrically inspected via the first circuit board 2a.
  • step S18 whether the second semiconductor chip 5 is mounted on the second circuit board 4 is electrically inspected via the second circuit board 4.
  • solder is applied to the electrodes 411 and 413 on the upper surface 41 of the second circuit board 4 (step S19). Further, the fixing member 8 made of an adhesive is applied to the upper surface 51 of the second semiconductor chip 5 (step S20). Then, the first circuit board 2a and the chip part 6 are mounted on the second circuit board 4 and reflowed to join the first circuit board 2a and the chip part 6 to the second circuit board 4 (step S21).
  • thermoplastic resin covering the first semiconductor chip 3, the first circuit board 2a, the second semiconductor chip 5 and the chip component 6 is formed on the second circuit board 4 by, for example, insert molding, and the cover portion. 7a is formed.
  • the memory card la is manufactured through the above steps.
  • the first semiconductor chip 3 and the second semiconductor chip 5 are sandwiched between them. Therefore, the memory card la can be reduced in size and thickness.
  • at least a part of the second semiconductor chip 5 is other than a part of the region facing the first circuit board 2a on the lower surface 32 of the first semiconductor chip 3. The other part of the area is opposed to it.
  • the memory module and the controller module are inspected before being stacked, it is possible to individually determine whether the first semiconductor chip 3 and the second semiconductor chip 5 are mounted correctly. , Productivity and production cost can be reduced.
  • the first semiconductor chip 3 and the second semiconductor chip 5 are flip-chip mounted, so that the material of the cover portion 7a
  • the degree of freedom in selecting the formation method can be improved.
  • the flip chip mounting of the first semiconductor chip 3 and the second semiconductor chip 5 improves the reliability during mounting compared to wire bonding mounting.
  • the force S can be firmly fixed to the first circuit board 2a.
  • the first semiconductor chip 3 can be indirectly and firmly fixed to the second circuit board 4 by the fixing member 8 made of an adhesive.
  • the cover portion 7a is formed of a thermoplastic resin, thereby reducing the hardness of the cover portion 7a and increasing the reliability such as safety. Can do.
  • the force S described using the first semiconductor chip 3 and the second semiconductor chip 5 as an example of the memory chip and the control chip is not limited to this.
  • other bare chips such as ASIC may be used as the first semiconductor chip 3 and the second semiconductor chip 5.
  • two memory chips are stacked as the first semiconductor chip 3 and the second semiconductor chip 5, and the two memory chips are controlled by a control chip mounted on another area of the second circuit board 4.
  • a memory / controller combined chip for storing information and controlling other memory chips may be mounted on the second circuit board 4. This At this time, the semiconductor chip may not be a chip having a semiconductor function as a whole as long as it is a chip partially utilizing a semiconductor function.
  • the first semiconductor chip 3 is bonded to the first circuit board in a frame-like region along the outer periphery of the lower surface 32 or in a region near the three edges of the lower surface 32. I explained in, but this is limited to this.
  • a first circuit board 2b composed of two parallel boards is bonded onto the second circuit board 4, and the lower surfaces of the first semiconductor chip 3 are connected to each other.
  • a configuration may be adopted in which the first circuit board 2b is opposed and joined in a region in the vicinity of a pair of opposing edges.
  • the bumps 33 and 53 are described as examples formed on the electrodes of the first semiconductor chip 3 and the electrodes of the second semiconductor chip. It may be formed on the electrode 211 and on the electrode 412 of the second circuit board 4. In addition to the ball bumps, other types of ball bumps such as solder bumps, solder bumps, and the like may be used as the bumps 33 and 53.
  • the force S described as an example of sticking NCF or the like as the sealing resin is not limited to this.
  • the sealing resin may be formed using a non-conductive resin paste, an anisotropic conductive resin film, or an anisotropic conductive resin paste.
  • the example in which the second circuit board 4 of the second semiconductor chip 5 is mounted after the first circuit board of the first semiconductor chip 3 is mounted has been described. I can't.
  • the mounting of the second circuit board 4 of the second semiconductor chip 5 may be performed in parallel with the mounting of the first circuit board of the first semiconductor chip 3 before the mounting of the first semiconductor chip 3. You may go. Similarly, whether the mounting of the first circuit board of the first semiconductor chip 3 is inspected before the mounting of the second circuit board 4 of the second semiconductor chip 5 is performed. You can go in parallel with the implementation.
  • the present invention is not limited to this. If necessary, at least one of mounting the first semiconductor chip 3 on the first circuit board and mounting the second semiconductor chip 5 on the second circuit board 4 may be performed by wire bonding. However, the first semiconductor chip 3 and the second semiconductor chip 2 are improved in terms of improving the mounting reliability and improving the degree of freedom in selecting the cover material and the forming method.
  • the semiconductor chip 5 is preferably mounted on the circuit board by flip chip mounting.
  • the cover portion is formed of a thermoplastic resin.
  • the cover may be formed by molding a thermosetting resin.
  • the memory card of the present invention may be used as another card type recording medium other than an SD card, such as an IC card.
  • the present invention is useful in a technical field such as a memory card that records information, and that is particularly required to be reduced in size and thickness.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Credit Cards Or The Like (AREA)
  • Semiconductor Memories (AREA)

Abstract

La carte mémoire (1) selon l'invention comporte une première carte de circuit imprimé (2); une première puce à semi-conducteur (3) montée sur un plan supérieur (21) de la première carte de circuit imprimé (2) et dont seule une zone partielle d'un plan inférieur (32) fait face à la première carte de circuit imprimé (2); une deuxième carte de circuit imprimé (4) dans laquelle un plan inférieur (22) de la première carte de circuit imprimé (2) est lié sur un plan supérieur (41); une deuxième puce à semi-conducteur (5) montée sur le plan supérieur (41) de la deuxième carte de circuit imprimé (4) et faisant au moins partiellement face à une zone partielle différente de la zone partielle du plan inférieur (32) de la première puce à semi-conducteur (3); et une section de couverture (7) pour couvrir la première puce à semi-conducteur (3), la première carte de circuit imprimé (2) et la deuxième puce à semi-conducteur (5),côté plan supérieur (41) de la deuxième carte de circuit imprimé (4).
PCT/JP2007/051055 2006-02-02 2007-01-24 Carte mémoire et procédé de fabrication de carte mémoire WO2007088757A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007556823A JP4946872B2 (ja) 2006-02-02 2007-01-24 メモリカードの製造方法
US12/160,960 US7933127B2 (en) 2006-02-02 2007-01-24 Memory card and memory card manufacturing method
CN2007800031807A CN101375299B (zh) 2006-02-02 2007-01-24 存储卡及存储卡的制造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006025445 2006-02-02
JP2006-025445 2006-02-02

Publications (1)

Publication Number Publication Date
WO2007088757A1 true WO2007088757A1 (fr) 2007-08-09

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PCT/JP2007/051055 WO2007088757A1 (fr) 2006-02-02 2007-01-24 Carte mémoire et procédé de fabrication de carte mémoire

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JP (1) JP4946872B2 (fr)
CN (1) CN101375299B (fr)
TW (1) TW200805619A (fr)
WO (1) WO2007088757A1 (fr)

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JP2008204462A (ja) * 2007-02-21 2008-09-04 Samsung Electronics Co Ltd 半導体パッケージ、半導体パッケージを備える集積回路カード及びその製造方法
JP2012502476A (ja) * 2008-09-08 2012-01-26 インテル・コーポレーション メインボードに直接取着されたダイをパッケージが被覆しているメインボード構造
JP2012094800A (ja) * 2010-02-15 2012-05-17 Toshiba Corp 半導体記憶装置およびその製造方法
WO2012145115A1 (fr) * 2011-04-21 2012-10-26 Tessera, Inc. Module de puce sur plaque empilé à connecteur latéral
US8299925B2 (en) 2007-10-26 2012-10-30 Fujitsu Limited RFID tag and manufacturing method thereof
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8941999B2 (en) 2010-10-19 2015-01-27 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US9093291B2 (en) 2011-04-21 2015-07-28 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package

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JP5337110B2 (ja) * 2010-06-29 2013-11-06 株式会社東芝 半導体記憶装置

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Cited By (26)

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JP2008204462A (ja) * 2007-02-21 2008-09-04 Samsung Electronics Co Ltd 半導体パッケージ、半導体パッケージを備える集積回路カード及びその製造方法
US8329507B2 (en) 2007-02-21 2012-12-11 Samsung Electronics Co., Ltd. Semiconductor package, integrated circuit cards incorporating the semiconductor package, and method of manufacturing the same
US8299925B2 (en) 2007-10-26 2012-10-30 Fujitsu Limited RFID tag and manufacturing method thereof
JP2012502476A (ja) * 2008-09-08 2012-01-26 インテル・コーポレーション メインボードに直接取着されたダイをパッケージが被覆しているメインボード構造
US8603865B2 (en) 2010-02-15 2013-12-10 Kabushiki Kaisha Toshiba Semiconductor storage device and manufacturing method thereof
JP2012094800A (ja) * 2010-02-15 2012-05-17 Toshiba Corp 半導体記憶装置およびその製造方法
US8269325B2 (en) 2010-02-15 2012-09-18 Kabushiki Kaisha Toshiba Semiconductor storage device and manufacturing method thereof
US8492885B2 (en) 2010-02-15 2013-07-23 Kabushiki Kaisha Toshiba Semiconductor storage device and manufacturing method thereof
US8941999B2 (en) 2010-10-19 2015-01-27 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US9312239B2 (en) 2010-10-19 2016-04-12 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US9281295B2 (en) 2011-04-21 2016-03-08 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection
US9093291B2 (en) 2011-04-21 2015-07-28 Tessera, Inc. Flip-chip, face-up and face-down wirebond combination package
WO2012145115A1 (fr) * 2011-04-21 2012-10-26 Tessera, Inc. Module de puce sur plaque empilé à connecteur latéral
US8952516B2 (en) 2011-04-21 2015-02-10 Tessera, Inc. Multiple die stacking for two or more die
US9281266B2 (en) 2011-04-21 2016-03-08 Tessera, Inc. Stacked chip-on-board module with edge connector
US9013033B2 (en) 2011-04-21 2015-04-21 Tessera, Inc. Multiple die face-down stacking for two or more die
US8928153B2 (en) 2011-04-21 2015-01-06 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8633576B2 (en) 2011-04-21 2014-01-21 Tessera, Inc. Stacked chip-on-board module with edge connector
US10622289B2 (en) 2011-04-21 2020-04-14 Tessera, Inc. Stacked chip-on-board module with edge connector
CN103620775A (zh) * 2011-04-21 2014-03-05 泰塞拉公司 具有边缘连接器的堆叠板上芯片模块
US9312244B2 (en) 2011-04-21 2016-04-12 Tessera, Inc. Multiple die stacking for two or more die
US9437579B2 (en) 2011-04-21 2016-09-06 Tessera, Inc. Multiple die face-down stacking for two or more die
US9640515B2 (en) 2011-04-21 2017-05-02 Tessera, Inc. Multiple die stacking for two or more die
US9735093B2 (en) 2011-04-21 2017-08-15 Tessera, Inc. Stacked chip-on-board module with edge connector
US9806017B2 (en) 2011-04-21 2017-10-31 Tessera, Inc. Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US8970028B2 (en) 2011-12-29 2015-03-03 Invensas Corporation Embedded heat spreader for package with multiple microelectronic elements and face-down connection

Also Published As

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JPWO2007088757A1 (ja) 2009-06-25
JP4946872B2 (ja) 2012-06-06
CN101375299B (zh) 2012-08-08
CN101375299A (zh) 2009-02-25
TW200805619A (en) 2008-01-16

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