JP2012094800A - 半導体記憶装置およびその製造方法 - Google Patents
半導体記憶装置およびその製造方法 Download PDFInfo
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- JP2012094800A JP2012094800A JP2010279877A JP2010279877A JP2012094800A JP 2012094800 A JP2012094800 A JP 2012094800A JP 2010279877 A JP2010279877 A JP 2010279877A JP 2010279877 A JP2010279877 A JP 2010279877A JP 2012094800 A JP2012094800 A JP 2012094800A
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】半導体記憶装置10は、一方の面に外部接続端子が設けられ、外部接続端子が設けられる領域と略同じ平面形状に個片化された有機基板11と、有機基板11に対して相対的に位置決めされた載置領域21を有するリードフレーム13と、載置領域21に接着された半導体メモリチップ15と、を備えることを特徴とする。
【選択図】図3
Description
図1は、第1の実施の形態にかかる半導体記憶装置の外観を示す平面図である。図2は、図1に示す半導体記憶装置の外観を示す底面図である。図3は、図1に示す半導体記憶装置の内部構成を模式的に示す図である。図4は、図1に示す半導体記憶装置のA−A線に沿った断面構造を示す横断面図。半導体記憶装置10は、例えば、マイクロSDカード(登録商標)である。
図16は、第2の実施の形態にかかる半導体記憶装置の内部構成を模式的に示す平面図である。図17は、図16に示す半導体記憶装置のB−B線に沿った断面構造を示す横断面図である。なお、上記実施の形態と同様の構成については同様の符号を付して詳細な説明を省略する。また、第2の実施の形態にかかる半導体記憶装置150の外観は、上記第1の実施の形態と略同様であるため、外観図も省略する。すなわち、図16では、図3と同様に、樹脂モールド部18を省略して図示している。
Claims (11)
- 一方の面に外部接続端子が設けられ、前記外部接続端子が設けられる領域と略同じ平面形状に個片化された有機基板と、
前記有機基板に対して相対的に位置決めされた載置領域を有するリードフレームと、
前記載置領域に接着された半導体メモリチップと、を備える半導体記憶装置。 - 前記リードフレームは、前記有機基板の前記外部接続端子が設けられた面の反対側の面となる他方の面に接着される請求項1に記載の半導体記憶装置。
- 前記半導体メモリチップへのデータの書込みや読出しを行うコントローラチップをさらに備え、
前記コントローラチップは、前記有機基板の前記他方の面上に実装される請求項2に記載の半導体記憶装置。 - 前記外部接続端子を露出させて、前記有機基板、前記リードフレーム、および前記半導体メモリチップを封止する樹脂モールド部をさらに備える請求項1〜3のいずれか1つに記載の半導体記憶装置。
- 前記リードフレームは非導電性である請求項1〜4のいずれか1つに記載の半導体記憶装置。
- 外部接続端子が形成された有機基板を、前記外部接続端子が形成された領域と略同じ平面形状に個片化し、
載置領域を有するリードフレームの一部分を、前記有機基板に対して相対的に位置決めし、
前記載置領域に半導体メモリチップを配置する半導体記憶装置の製造方法。 - 配線層が形成されるとともに一方の面に外部接続端子が設けられ、前記外部接続端子が設けられる領域と略同じ平面形状に個片化された有機基板と、
前記配線層と電気的に接続された半導体メモリチップと、
前記有機基板が接着される接着領域が第1面側に設けられ、前記半導体メモリチップが載置される載置領域が前記第1面の反対の第2面側に設けられ、前記接着領域に開口が形成された支持基板と、を備える半導体記憶装置。 - 前記有機基板は、前記外部接続端子が設けられた面の反対側の面が前記支持基板に接着される請求項7に記載の半導体記憶装置。
- 前記半導体メモリチップへのデータの書込みや読出しを行うコントローラチップをさらに備え、
前記コントローラチップは、前記有機基板の他方の面上であって、前記接着領域に形成された開口からの露出部分に実装される請求項8に記載の半導体記憶装置。 - 前記外部接続端子を露出させて、前記有機基板、前記支持基板、および前記半導体メモリチップを封止する樹脂モールド部をさらに備える請求項7〜9のいずれか1つに記載の半導体記憶装置。
- 前記支持基板は絶縁膜材料であることを特徴とする請求項7〜10のいずれか1つに記載の半導体記憶装置。
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US13/599,575 US8492885B2 (en) | 2010-02-15 | 2012-08-30 | Semiconductor storage device and manufacturing method thereof |
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JP2011205013A (ja) * | 2010-03-26 | 2011-10-13 | Toshiba Corp | 半導体記憶装置 |
JP2013062470A (ja) * | 2011-09-15 | 2013-04-04 | Powertech Technology Inc | 半導体装置 |
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JP2013025540A (ja) | 2011-07-20 | 2013-02-04 | Toshiba Corp | 半導体記憶装置 |
JP2015005141A (ja) * | 2013-06-20 | 2015-01-08 | 株式会社東芝 | 半導体記憶装置及び製造方法 |
US10121767B2 (en) * | 2015-09-10 | 2018-11-06 | Toshiba Memory Corporation | Semiconductor storage device and manufacturing method thereof |
KR20210146165A (ko) | 2020-05-26 | 2021-12-03 | 삼성전자주식회사 | 반도체 패키지 |
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