TWI481001B - 晶片封裝結構及其製造方法 - Google Patents

晶片封裝結構及其製造方法 Download PDF

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Publication number
TWI481001B
TWI481001B TW100132669A TW100132669A TWI481001B TW I481001 B TWI481001 B TW I481001B TW 100132669 A TW100132669 A TW 100132669A TW 100132669 A TW100132669 A TW 100132669A TW I481001 B TWI481001 B TW I481001B
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Taiwan
Prior art keywords
wafer
package structure
chip package
pads
electrically connected
Prior art date
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TW100132669A
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English (en)
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TW201312723A (zh
Inventor
Diann Fang Lin
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Dawning Leading Technology Inc
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Application filed by Dawning Leading Technology Inc filed Critical Dawning Leading Technology Inc
Priority to TW100132669A priority Critical patent/TWI481001B/zh
Priority to CN201210331064.0A priority patent/CN103000588B/zh
Priority to US13/606,147 priority patent/US10651146B2/en
Publication of TW201312723A publication Critical patent/TW201312723A/zh
Application granted granted Critical
Publication of TWI481001B publication Critical patent/TWI481001B/zh

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    • H—ELECTRICITY
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Description

晶片封裝結構及其製造方法
本發明係關於一種封裝結構及該封裝結構之製造方法，更詳細而言，本發明關於一種晶片封裝結構及其製造方法。
多晶片封裝結構(Multi-chip package,MCP)是將兩個或兩個以上之晶片整合在單一封裝結構中，以達成晶片間緊密堆疊互連的封裝，進而使系統運作速度極大化，為半導體封裝業者積極發展之結構。
習知多晶片封裝結構大多是將多個晶片垂直對齊堆疊、交錯堆疊或是階梯狀堆疊等等，然後每一晶片藉由打線方式(Wire bonding)與基板電性連接。日本專利公開號「特開平11-265975」所揭露者，即為此種習知的晶片封裝結構。
然而，由於晶片是垂直地堆疊，晶片封裝結構的整體厚度勢必會較厚。且當晶片堆疊的數目增加時，晶片與基板連接的銲線(金屬引線)之數量便越多。為避免兩銲線間有電性連接，銲線的弧度亦需增大，此舉會增加了銲線打線的困難，且銲線較容易因為振動而產生應力集中現象而斷裂。不僅如此，基板為了能與多條銲線及最底層之晶片連接，基板上表面之尺寸需增大，造成多晶片封裝結構之整體寬度或長度也增加。
有鑑於此，提供一種可改善至少一種上述缺失的晶片封裝結構及其製造方法，便為此業界亟需努力之目標。
本發明之目的在於提供一種晶片封裝結構及其製造方法，該晶片封裝結構可具有較小之尺寸。
為達上述目的，本發明所提供的晶片封裝結構包含：一第一晶片、一第二晶片及一轉接元件。第一晶片具有複數個第一銲墊，第一銲墊形成於第一晶片的一上表面；第二晶片具有複數個第二銲墊，第二銲墊形成於第二晶片的一上表面，第一晶片與第二晶片並排，且第二晶片與第一晶片電性連接；轉接元件設置於第一晶片的上表面上，並與第一晶片電性連接。
為達上述目的，本發明所提供的晶片封裝結構之製造方法包含：提供一第一晶片，第一晶片具有複數個第一銲墊，該等第一銲墊形成於第一晶片的一上表面；提供一第二晶片，第二晶片具有複數個第二銲墊，該等第二銲墊形成於第二晶片的一上表面；將第一晶片與第二晶片並排，並電性連接第一晶片與第二晶片；以及放置一轉接元件於第一晶片的上表面上，並電性連接轉接元件與第一晶片及/或第二晶片。
在參閱圖式及隨後描述之實施方式後，此技術領域具有通常知識者便可瞭解本發明之其他目的，以及本發明之技術手段及實施態樣。
請參閱第1A圖所示，為本發明之晶片封裝結構之第一實施例的側視圖。晶片封裝結構1包含一第一晶片11、一第二晶片12及一轉接元件13，以下將依序說明各元件的技術內容。
第一晶片11具有複數個第一銲墊111，該等第一銲墊111形成 於第一晶片11的一上表面112。
第二晶片12具有複數個第二銲墊121，該等第二銲墊121形成於第二晶片12的一上表面122。第一晶片11與第二晶片12沿一第一方向X並排，且第一晶片11與第二晶片12之間可包含一間距，以避免兩者直接相接觸。於其它實施例中，第一晶片11與第二晶片12也可相接觸，使得兩者之間無間距。
第一晶片11更進一步電性連接第二晶片12，使得第一晶片11可與第二晶片12相互傳遞電能(訊號或資料)。
本實施例中，第一晶片11與第二晶片12的電性連接是透過打線(wire bonding)方式來達成。詳言之，晶片封裝結構1另包含多個金屬引線14，金屬引線14的一端會焊接於第一晶片11的其中一個第一銲墊111上，而金屬引線14的另一端則會焊接於其中一個第二銲墊121，藉此導通第一晶片11與第二晶片12。為了節省金屬引線14之長度，會選擇最相接近的第一銲墊111及第二銲墊121，作為第一晶片11與第二晶片12電性連接的媒介。
於其它實施例中，第一晶片11也可透過後述的轉接元件13，間接地與第二晶片12電性連接。
第一晶片11及第二晶片12可為相同或不相同之晶片，於本實施例中，第一晶片11為一記憶體，而第二晶片12為控制該記憶體的一控制晶片，且第一晶片11之一下表面之面積可大於第二晶片12之一下表面之面積。
轉接元件13具有複數個第三銲墊131，該等第三銲墊131形成於轉接元件13的一上表面132。轉接元件13沿著一第二方向Y設置(堆疊)於第一晶片11的上表面112上，該第二方向Y與第一方向X相交錯，且較佳地為相垂直。轉接元件13可為一電路板(例如陶瓷電路板、軟性印刷電路板等)、晶片等可傳導電能之元件，且轉接元件13之中或之上還可形成有天線、電容器、電感器等電子元件，以增加轉接元件13的功能。
轉接元件13的長度(或寬度)可小於第一晶片11的長度(或寬度)，以使得轉接元件13設置於第一晶片11上時，第一晶片11的部分之第一銲墊111不會被轉接元件13遮蓋。
轉接元件13更可電性連接第一晶片11及第二晶片12。轉接元件13與第一晶片11及第二晶片12的電性連接也可透過打線方式來達成。詳言之，該等第一銲墊111的其中一個利用一條金屬引線14來與轉接元件13的該等第三銲墊131的其中一個電性連接，而該等第二銲墊121的其中一個亦可利用另一條金屬引線14來與該等第三銲墊131的其中一個電性連接。
需說明的是，轉接元件13與第一晶片11之間的電性連接方式亦可藉由其它方式來達成，例如藉由覆晶(Flip chip)方式。詳言之，請參閱第1B圖所示，轉接元件13的第三銲墊131更可形成於轉接元件13的一下表面133上，且朝向第一晶片11的其中一個第一銲墊111。如此，轉接元件13的其中一個第三銲墊131即可藉由覆晶方式電性連接第一晶片11的其中一個第一銲墊111，使轉接元件13與第一晶片11電性連接，再經由轉接元件13的上 表面132之第三銲墊131與第二晶片12之第二銲墊121形成電性連接。
在此一結構條件下，轉接元件13將不須因為第一晶片11之第一銲墊111的位置而限制其尺寸，故可更加靈活的利用此轉接元件13的特性，以減少打線的應用，並可大幅增加此結構在電性傳遞上的效率。
本實施例之晶片封裝結構1與習知的相較，第一晶片11與第二晶片12並非堆疊設置，故晶片封裝結構1的整體厚度可較小，以利於應用於薄型化的電子產品。再者，由於晶片封裝結構1厚度減小，使得「第一晶片11與轉接元件13之間」、「第二晶片12與轉接元件13之間」或「第一晶片11與第二晶片12之間」的金屬引線14之弧度可因彼此間之打線距離縮短而進一步減少其打線的弧高。此外，晶片封裝結構1可不需像習知般具有一個大於第一晶片11之底面積的基板，因此晶片封裝結構1相較於習知技術而言，可具有較小之尺寸(長度或寬度)。
轉接元件13還可作為第一晶片11與第二晶片12的電能傳輸的中繼站。詳言之，若第一晶片11的最左邊的第一銲墊111欲傳遞電能至第二晶片12的最左邊的第二銲墊121時，該第一銲墊111可先將電能傳輸至轉接元件13的最左邊的第三銲墊131，使得電能可透過轉接元件13的導電線路，傳遞至最右邊的第三銲墊131；爾後，最右邊的第三銲墊131再將電能傳輸至最左邊的第二銲墊121。如此，最左邊的第一銲墊111與最左邊的第二銲墊121之間可不需一個很長的金屬引線14來傳遞電能。此外，與金屬引 線14相比，透過轉接元件13傳遞的電能較不會損耗。
以上為第一實施例的晶片封裝結構1之說明，接著說明本發明的晶片封裝結構的其它實施例。為了簡潔說明之目的，其他實施例與第一實施例相似之處，以及其他實施例之間的相似之處，皆將不再敘述之。
請參閱第2圖所示，為本發明的晶片封裝結構的第二實施例的一側視圖。於此態樣中，晶片封裝結構2同樣包含一第一晶片21、一第二晶片22、一轉接元件23及複數個金屬引線24。第二實施例的晶片封裝結構2與前述晶片封裝結構1之差異在於：更包含一黏著層25。
黏著層25設置於第一晶片21的上表面212與轉接元件23之間，以使轉接元件23黏於第一晶片21的上表面212上，不易相對第一晶片21移動。此外，黏著層25可為黏性膠帶、可固化的黏膠等具有黏性且不會導通電能的物體，以使被黏著層25覆蓋的第一晶片21與轉接元件23不會有短路之問題。而本實施例中，黏著層25具體為一晶片接合膜(Die Attach Film)。
請參閱第3圖所示，為本發明的晶片封裝結構的第三實施例的一側視圖。於此態樣中，晶片封裝結構3同樣包含一第一晶片31、一第二晶片32、一轉接元件33、複數個金屬引線34及一黏著層35，而晶片封裝結構3與前述晶片封裝結構1或2之差異在於：轉接元件33更設置於第二晶片32之上表面322上，並與第二晶片32電性連接。
詳言之，轉接元件33同時設置於第一晶片31之上表面312及第二晶片之上表面322，橫跨第一晶片31及第二晶片32之間的間 距，且黏著層35亦設置於第二晶片之上表面322。
當轉接元件33同時設置於第一晶片31及第二晶片32上時，轉接元件33的長度(或寬度)可大於第一晶片31的長度(或寬度)。換言之，轉接元件33的尺寸會比第一實施例的轉接元件11的尺寸大，使得轉接元件33上可安排更複雜之線路或更多的電子元件，以使晶片封裝結構3能處理更複雜的資訊或有更多之功能。此外，第一晶片31及第二晶片32之間的電性連接可透過轉接元件33來達成，以節省金屬引線34之數目。
請參閱第4A圖及第4B圖，分別為本發明之晶片封裝結構之第四實施例的上視圖及側視圖。晶片封裝結構4同樣包含一第一晶片41、一第二晶片42、一轉接元件43、複數個金屬引線44及一黏著層45，而與前述第三實施例的晶片封裝結構3的差異在於：晶片封裝結構4更包含複數個金屬接腳46(或稱金手指)及一封裝膠體47。
該等金屬接腳46可與第一晶片41或第二晶片42並排，亦可設置於第一晶片41或第二晶片42的下方，且該等金屬接腳46可透過金屬引線44來與第一晶片41或第二晶片42電性連接。本實施例中，該等金屬接腳46係與第二晶片42間隔地並排，即第二晶片42設置於該等金屬接腳46與第一晶片41之間，且金屬接腳46透過金屬引線44與第二晶片42電性連接。
封裝膠體47包覆第一晶片41、第二晶片42、轉接元件43、該等金屬接腳46及金屬引線44。該等金屬接腳46各具有一從封裝膠體47中暴露出的表面461，即該等金屬接腳46之下表面 未受到封裝膠體47包覆。如此，該等金屬接腳46的表面461可作為晶片封裝結構4與外部電子元件或電路板(圖未示出)連接的媒介。
請參閱第5A圖及第5B圖，分別為本發明之晶片封裝結構5之第五實施例的上視圖及側視圖。晶片封裝結構5包含一第一晶片51、一第二晶片52、一轉接元件53、複數個金屬引線54及一黏著層55，晶片封裝結構5類似第二實施例的晶片封裝結構2，而差異在於：本實施例之晶片封裝結構5更包含一基板56。
第一晶片51及第二晶片52設置於基板56上，而基板56具有一電源銲墊(power bar)561及一接地銲墊(ground bar)562；電源銲墊561及接地銲墊562設置於基板56的一上表面563，並位於第一晶片51及第二晶片52之間。
第一晶片51及第二晶片52更進一步電性連接基板56。詳細地說，該些第二銲墊521的其中一個藉由打線方式(金屬引線54)電性連接電源銲墊561，而該些第二銲墊521的另一個藉由打線方式電性連接接地銲墊562。該些第一銲墊511的其中一個亦可藉由打線方式來電性連接電源銲墊561或接地銲墊562。
由於電源銲墊561及接地銲墊562位於第一晶片51及第二晶片52之間，「用以連接第一晶片51及第二晶片52至電源銲墊561及接地銲墊562」的金屬引線54之長度可簡短，而金屬引線54之配置亦可簡化。
需說明的是，於本實施例中，第一晶片51與基板56之間及第 二晶片52與基板56之間更可分別設置有一黏著層55，以使第一晶片51及第二晶片52黏固於基板56的上表面563上。
請參閱第5C圖，於本實施例中，晶片封裝結構5亦可加入具有其它功能的一第三晶片57及一第四晶片58。第三晶片57可設置於轉接元件53上，並與轉接元件53電性連接；而第四晶片58可設置於第一晶片51上，並與第一晶片51電性連接。
以上為本發明的晶片封裝結構的各實施例之說明。接著說明本發明的晶片封裝結構之製造方法，該製造方法至少可製作出上述該等晶片封裝結構1至5。然而需說明的是，本發明的晶片封裝結構並不侷限由本發明的晶片封裝結構之製造方法來製作。
請參閱第6圖所示，為本發明之晶片封裝結構之製造方法之一流程圖。首先，如步驟601所示，提供一第一晶片，該第一晶片具有複數個第一銲墊，該等第一銲墊形成於第一晶片的一上表面。接著如步驟602所示，提供一第二晶片，第二晶片具有複數個第二銲墊，該等第二銲墊形成於第二晶片的一上表面；如步驟603所示，並排第一晶片與第二晶片，並電性連接第一晶片與第二晶片；如步驟604所示，放置一轉接元件於第一晶片的上表面上，並電性連接轉接元件與第一晶片及/或第二晶片。藉由以上步驟即可製造出如第一實施例所示之晶片封裝結構(如第1圖所示)。
或者，在步驟603後，可如步驟605所示，設置一黏著層於第一晶片的上表面，再如步驟606所示，放置轉接元件於黏著層上，使得轉接元件黏於第一晶片的上表面上，便可製造出如第二實施 例所示之晶片封裝結構(如第2圖所示)。
又或者，在步驟603後，可如步驟607所示，將轉接元件同時放置於第一晶片之上表面上及第二晶片之上表面上，並電性連接轉接元件、第一晶片與第二晶片，藉此可製造出如第三實施例所示之晶片封裝結構(如第3圖所示)。
放置轉接元件於第一晶片上後，可如步驟608所示，將複數個金屬接腳與第一晶片或第二晶片並排，或者如步驟609所示，將複數個金屬接腳設置於第一晶片或第二晶片下方，接著電性連接該等金屬接腳與第一晶片或第二晶片。再如步驟610所示，使用一封裝膠體包覆第一晶片、第二晶片、轉接元件及該等金屬接腳，並使得該等金屬接腳的每一個的一表面從封裝膠體中暴露出，藉此便可製造出如第四實施例所示之晶片封裝結構(如第4A圖及第4B圖所示)。
或者，於放置轉接元件於第一晶片上後，接著可如步驟611所示，將第一晶片及第二晶片設置於一基板上。基板可具有一電源銲墊及一接地銲墊，電源銲墊及接地銲墊設置於基板的一上表面，並位於第一晶片及第二晶片之間；然後藉由打線方式電性連接該些第一銲墊的其中一個與電源銲墊或接地銲墊，並藉由打線方式電性連接該些第二銲墊的其中一個與電源銲墊或接地銲墊，即可製造如第五實施例之晶片封裝結構(如第5A圖及第5B圖所示)。
於步驟611後，可如步驟612所示，再設置另一晶片於第一晶片上，且與轉接元件並排；也可將該另一晶片設置於轉接元件上， 再將該另一晶片與轉接元件、第一晶片或第二晶片電性連接(如第5C圖所示)。
藉由上述晶片封裝結構之製造方法，各種晶片封裝結構可被製造出。
綜上所述，本發明的晶片封裝結構及其製造方法至少可具有下列特點：
1、晶片封裝結構可不需像習知般具有一個大於晶片之底面積的基板，因此相較於習知技術而言，晶片封裝結構可具有較小之尺寸
2、因為第一晶片與第二晶片為並排，而非堆疊，故晶片封裝結構之整體厚度可較少，以利於應用於厚度較薄的電子產品中。
3、晶片封裝結構的轉接元件可使晶片之間的打線距離及打線高度減少，且轉接元件本身可包含天線、電容器、電感器等元件，以擴充晶片封裝結構的功能。
上述之實施例僅用來例舉本發明之實施態樣，以及闡釋本發明之技術特徵，並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍，本發明之權利保護範圍應以申請專利範圍為準。
1‧‧‧晶片封裝結構
11‧‧‧第一晶片
111‧‧‧第一銲墊
112‧‧‧上表面
12‧‧‧第二晶片
121‧‧‧第二銲墊
122‧‧‧上表面
13‧‧‧轉接元件
131‧‧‧第三銲墊
132‧‧‧上表面
133‧‧‧下表面
14‧‧‧金屬引線
2‧‧‧晶片封裝結構
21‧‧‧第一晶片
212‧‧‧上表面
22‧‧‧第二晶片
23‧‧‧轉接元件
24‧‧‧金屬引線
25‧‧‧黏著層
3‧‧‧晶片封裝結構
31‧‧‧第一晶片
312‧‧‧上表面
32‧‧‧第二晶片
322‧‧‧上表面
33‧‧‧轉接元件
34‧‧‧金屬引線
35‧‧‧黏著層
4‧‧‧晶片封裝結構
41‧‧‧第一晶片
42‧‧‧第二晶片
43‧‧‧轉接元件
44‧‧‧金屬引線
45‧‧‧黏著層
46‧‧‧金屬接腳
461‧‧‧表面
47‧‧‧封裝膠體
5‧‧‧晶片封裝結構
51‧‧‧第一晶片
52‧‧‧第二晶片
521‧‧‧第二銲墊
53‧‧‧轉接元件
54‧‧‧金屬引線
55‧‧‧黏著層
56‧‧‧基板
561‧‧‧電源銲墊
562‧‧‧接地銲墊
563‧‧‧上表面
57‧‧‧第三晶片
58‧‧‧第四晶片
601~612‧‧‧步驟
X‧‧‧第一方向
Y‧‧‧第二方向
第1A圖係本發明之晶片封裝結構之第一實施例之側視圖；第1B圖係本發明之晶片封裝結構之第一實施例之另一態樣之 側視圖；第2圖係本發明之晶片封裝結構之第二實施例之側視圖；第3圖係本發明之晶片封裝結構之第三實施例之側視圖；第4A圖係本發明之晶片封裝結構之第四實施例之側視圖；第4B圖係本發明之晶片封裝結構之第四實施例之上視圖；第5A圖係本發明之晶片封裝結構之第五實施例之側視圖；第5B圖係本發明之晶片封裝結構之第五實施例之上視圖；第5C圖係本發明之晶片封裝結構之第五實施例之另一態樣之側視圖；及第6圖係本發明之晶片封裝結構之製造方法之流程圖。
1‧‧‧晶片封裝結構
11‧‧‧第一晶片
111‧‧‧第一銲墊
112‧‧‧上表面
12‧‧‧第二晶片
121‧‧‧第二銲墊
122‧‧‧上表面
13‧‧‧轉接元件
131‧‧‧第三銲墊
132‧‧‧上表面
133‧‧‧下表面
14‧‧‧金屬引線
X‧‧‧第一方向
Y‧‧‧第二方向

Claims (14)

  1. 一種晶片封裝結構，包含：一第一晶片，具有複數個第一銲墊，該等第一銲墊形成於該第一晶片的一上表面；一第二晶片，具有複數個第二銲墊，該等第二銲墊形成於該第二晶片的一上表面，該第一晶片與該第二晶片並排，且該第二晶片與該第一晶片電性連接；以及一轉接元件，設置於該第一晶片的該上表面上，並與該第一晶片電性連接；其中該第一晶片及該第二晶片之下未堆疊有一基板或另一晶片。
  2. 如請求項1所述之晶片封裝結構，其中該等第一銲墊的其中一個藉由打線方式電性連接該等第二銲墊的其中一個。
  3. 如請求項1所述之晶片封裝結構，其中該轉接元件具有複數個第三銲墊，該等第三銲墊形成於該轉接元件的一上表面，該等第一銲墊的其中一個藉由打線方式電性連接該等第三銲墊的其中一個。
  4. 如請求項3所述之晶片封裝結構，其中該等第二銲墊的其中一個藉由打線方式電性連接該等第三銲墊的其中一個。
  5. 如請求項1所述之晶片封裝結構，更包含一黏著層，設置於該第一晶片的該上表面與該轉接元件之間，以使該轉接元件黏於該第一晶片的該上表面上。
  6. 如請求項1所述之晶片封裝結構，其中該轉接元件具有複數 個第三銲墊，該等第三銲墊形成於該轉接元件的一下表面，該等第一銲墊的其中一個藉由覆晶方式電性連接該等第三銲墊的其中一個。
  7. 如請求項1所述之晶片封裝結構，其中該轉接元件更設置於該第二晶片之該上表面上，並與該第二晶片電性連接。
  8. 如請求項1所述之晶片封裝結構，更包含複數個金屬接腳，與該第一晶片或該第二晶片並排，或設置於該第一晶片或該第二晶片的下方，且與該第一晶片或該第二晶片電性連接。
  9. 如請求項8所述之晶片封裝結構，更包含：一封裝膠體，包覆該第一晶片、該第二晶片、該轉接元件及該等金屬接腳，該等金屬接腳各具有一從該封裝膠體中暴露出的表面。
  10. 一種晶片封裝結構之製造方法，包含：提供一第一晶片，該第一晶片具有複數個第一銲墊，該等第一銲墊形成於該第一晶片的一上表面；提供一第二晶片，該第二晶片具有複數個第二銲墊，該等第二銲墊形成於該第二晶片的一上表面；將該第一晶片與該第二晶片並排，並電性連接該第一晶片與該第二晶片；以及放置一轉接元件於該第一晶片的該上表面上，並電性連接該轉接元件與該第一晶片及/或第二晶片；其中該第一晶片及該第二晶片之下未堆疊有一基板或另一晶片。
  11. 如請求項10所述之晶片封裝結構之製造方法，更包含：設置一黏著層於該第一晶片的該上表面； 放置該轉接元件於該黏著層上，使得該轉接元件黏於該第一晶片的該上表面上。
  12. 如請求項10所述之晶片封裝結構之製造方法，更包含：放置該轉接元件於該第二晶片之該上表面上，並電性連接該轉接元件與該第二晶片。
  13. 如請求項10所述之晶片封裝結構之製造方法，更包含：將複數個金屬接腳與該第一晶片或該第二晶片並排，或置於該第一晶片或該第二晶片的下方，並電性連接該等金屬接腳與該第一晶片或該第二晶片。
  14. 如請求項13所述之晶片封裝結構之製造方法，更包含：使用一封裝膠體包覆該第一晶片、該第二晶片、該轉接元件及該等金屬接腳，並使得該等金屬接腳的每一個的一表面從該封裝膠體中暴露出。
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