CN103000588A - 芯片封装结构及其制造方法 - Google Patents

芯片封装结构及其制造方法 Download PDF

Info

Publication number
CN103000588A
CN103000588A CN2012103310640A CN201210331064A CN103000588A CN 103000588 A CN103000588 A CN 103000588A CN 2012103310640 A CN2012103310640 A CN 2012103310640A CN 201210331064 A CN201210331064 A CN 201210331064A CN 103000588 A CN103000588 A CN 103000588A
Authority
CN
China
Prior art keywords
chip
packaging structure
weld pad
switching element
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012103310640A
Other languages
English (en)
Other versions
CN103000588B (zh
Inventor
林殿方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
King Yuan Electronics Co Ltd
Original Assignee
Dawning Leading Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dawning Leading Technology Inc filed Critical Dawning Leading Technology Inc
Publication of CN103000588A publication Critical patent/CN103000588A/zh
Application granted granted Critical
Publication of CN103000588B publication Critical patent/CN103000588B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49565—Side rails of the lead frame, e.g. with perforations, sprocket holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

本发明为关于一种芯片封装结构及其制造方法。芯片封装结构包含：一第一芯片、一第二芯片及一转接元件。第一芯片具有复数个第一焊垫，第一焊垫形成于第一芯片的上表面；第二芯片具有复数个第二焊垫，第二焊垫形成于第二芯片的上表面，第一芯片与第二芯片并排，且第二芯片与第一芯片电性连接；转接元件设置于第一芯片的上表面上，并与第一芯片电性连接。借此，该芯片封装结构可具有较小的尺寸。

Description

芯片封装结构及其制造方法
技术领域
本发明是关于一种封装结构及该封装结构的制造方法，更详细而言，本发明关于一种芯片封装结构及其制造方法。
背景技术
多芯片封装结构（Multi-chip package，MCP）是将两个或两个以上的芯片整合在单一封装结构中，以实现芯片间紧密堆叠互连的封装，进而使系统运作速度极大化，为半导体封装业者积极发展的结构。
公知的多芯片封装结构大多是将多个芯片垂直对齐堆叠、交错堆叠或是阶梯状堆叠等等，然后每一芯片借由引线键合方式（Wire bonding）与基板电性连接。日本专利公开号「特开平11-265975」所揭示的，即为此种公知的芯片封装结构。
然而，由于芯片是垂直地堆叠，芯片封装结构的整体厚度势必会较厚。且当芯片堆叠的数目增加时，芯片与基板连接的焊线(金属引线)的数量便越多。为避免两焊线间有电性连接，焊线的弧度亦需增大，此举会增加了焊线引线键合的困难，且焊线较容易因为振动而产生应力集中现象而断裂。不仅如此，基板为了能与多条焊线及最底层的芯片连接，基板上表面的尺寸需增大，造成多芯片封装结构的整体宽度或长度也增加。
有鉴于此，提供一种可改善至少一种上述缺失的芯片封装结构及其制造方法，便成为业界亟需努力的目标。
发明内容
本发明的目的在于提供一种芯片封装结构及其制造方法，该芯片封装结构可具有较小的尺寸。
为达到上述目的，本发明所提供的芯片封装结构包含：一第一芯片、一第二芯片及一转接元件。第一芯片具有复数个第一焊垫，第一焊垫形成于第一芯片的一上表面；第二芯片具有复数个第二焊垫，第二焊垫形成于第二芯片的一上表面，第一芯片与第二芯片并排，且第二芯片与第一芯片电性连接；转接元件设置于第一芯片的上表面上，并与第一芯片电性连接。
为达到上述目的，本发明所提供的芯片封装结构的制造方法包含：提供一第一芯片，第一芯片具有复数个第一焊垫，这些第一焊垫形成于第一芯片的一上表面；提供一第二芯片，第二芯片具有复数个第二焊垫，这些第二焊垫形成于第二芯片的一上表面；将第一芯片与第二芯片并排，并电性连接第一芯片与第二芯片；以及放置一转接元件于第一芯片的上表面上，并电性连接转接元件与第一芯片及/或第二芯片。
在参阅附图及随后描述的实施方式后，此技术领域具有通常知识的技术人员便可了解本发明的其他目的，以及本发明的技术手段及实施方式。
附图说明
图1A为本发明的芯片封装结构的第一实施例的侧视图；
图1B为本发明的芯片封装结构的第一实施例的另一方式的侧视图；
图2为本发明的芯片封装结构的第二实施例的侧视图；
图3为本发明的芯片封装结构的第三实施例的侧视图；
图4A为本发明的芯片封装结构的第四实施例的侧视图；
图4B为本发明的芯片封装结构的第四实施例的俯视图；
图5A为本发明的芯片封装结构的第五实施例的侧视图；
图5B为本发明的芯片封装结构的第五实施例的俯视图；
图5C为本发明的芯片封装结构的第五实施例的另一方式的侧视图；及
图6为本发明的芯片封装结构的制造方法的流程图。
具体实施方式
请参阅图1A所示，为本发明的芯片封装结构的第一实施例的侧视图。芯片封装结构1包含一第一芯片11、一第二芯片12及一转接元件13，以下将依序说明各元件的技术内容。
第一芯片11具有复数个第一焊垫111，这些第一焊垫111形成于第一芯片11的一上表面112。
第二芯片12具有复数个第二焊垫121，这些第二焊垫121形成于第二芯片12的一上表面122。第一芯片11与第二芯片12沿一第一方向X并排，且第一芯片11与第二芯片12之间可包含一间距，以避免两者直接相接触。于其它实施例中，第一芯片11与第二芯片12也可相接触，使得两者之间无间距。
第一芯片11还进一步电性连接第二芯片12，使得第一芯片11可与第二芯片12相互传递电能(讯号或资料)。
本实施例中，第一芯片11与第二芯片12的电性连接是通过引线键合(wire bonding)方式来实现。具体地说，芯片封装结构1另包含多个金属引线14，金属引线14的一端会焊接于第一芯片11的其中一个第一焊垫111上，而金属引线14的另一端则会焊接于其中一个第二焊垫121，借此导通第一芯片11与第二芯片12。为了节省金属引线14的长度，会选择最相接近的第一焊垫111及第二焊垫121，作为第一芯片11与第二芯片12电性连接的媒介。
在其它实施例中，第一芯片11也可通过后述的转接元件13，间接地与第二芯片12电性连接。
第一芯片11及第二芯片12可为相同或不相同的芯片，在本实施例中，第一芯片11为一存储器，而第二芯片12为控制该存储器的一控制芯片，且第一芯片11的一下表面的面积可大于第二芯片12的一下表面的面积。
转接元件13具有复数个第三焊垫131，这些第三焊垫131形成于转接元件13的一上表面132。转接元件13沿着一第二方向Y设置(堆叠)于第一芯片11的上表面112上，该第二方向Y与第一方向X相交错，且较优地为相垂直。转接元件13可为一电路板(例如陶瓷电路板、软性印刷电路板等)、芯片等可传导电能的元件，且转接元件13之中或之上还可形成有天线、电容器、电感器等电子元件，以增加转接元件13的功能。
转接元件13的长度(或宽度)可小于第一芯片11的长度(或宽度)，以使得转接元件13设置于第一芯片11上时，第一芯片11的部分的第一焊垫111不会被转接元件13遮盖。
转接元件13还可电性连接第一芯片11及第二芯片12。转接元件13与第一芯片11及第二芯片12的电性连接也可通过引线键合方式来实现。具体地说，上述第一焊垫111的其中一个利用一条金属引线14来与转接元件13的上述第三焊垫131的其中一个电性连接，而上述第二焊垫121的其中一个也可利用另一条金属引线14来与上述第三焊垫131的其中一个电性连接。
需说明的是，转接元件13与第一芯片11之间的电性连接方式也可借由其它方式来实现，例如借由倒晶（Flip chip）方式。具体地说，请参阅图1B所示，转接元件13的第三焊垫131还可形成于转接元件13的一下表面133上，且朝向第一芯片11的其中一个第一焊垫111。如此，转接元件13的其中一个第三焊垫131即可借由倒晶方式电性连接第一芯片11的其中一个第一焊垫111，使转接元件13与第一芯片11电性连接，再经由转接元件13的上表面132的第三焊垫131与第二芯片12的第二焊垫121形成电性连接。
在此一结构条件下，转接元件13将不须因为第一芯片11的第一焊垫111的位置而限制其尺寸，故可更加灵活的利用此转接元件13的特性，以减少引线键合的应用，并可大幅增加此结构在电性传递上的效率。
本实施例的芯片封装结构1与公知的相比较，第一芯片11与第二芯片12并非堆叠设置，故芯片封装结构1的整体厚度可较小，以利于应用于薄型化的电子产品。再者，由于芯片封装结构1厚度减小，使得「第一芯片11与转接元件13之间」、「第二芯片12与转接元件13之间」或「第一芯片11与第二芯片12之间」的金属引线14的弧度可因彼此间的引线键合距离缩短而进一步减少其引线键合的弧高。此外，芯片封装结构1可不需像公知般具有一个大于第一芯片11的底面积的基板，因此芯片封装结构1相较于公知技术而言，可具有较小的尺寸(长度或宽度)。
转接元件13还可作为第一芯片11与第二芯片12的电能传输的中继站。具体地说，若第一芯片11的最左边的第一焊垫111欲传递电能至第二芯片12的最左边的第二焊垫121时，该第一焊垫111可先将电能传输至转接元件13的最左边的第三焊垫131，使得电能可通过转接元件13的导电线路，传递至最右边的第三焊垫131；尔后，最右边的第三焊垫131再将电能传输至最左边的第二焊垫121。如此，最左边的第一焊垫111与最左边的第二焊垫121之间可不需一个很长的金属引线14来传递电能。此外，与金属引线14相比，通过转接元件13传递的电能较不会损耗。
以上为第一实施例的芯片封装结构1的说明，接着说明本发明的芯片封装结构的其它实施例。为了简洁说明的目的，其他实施例与第一实施例相似之处，以及其他实施例之间的相似之处，皆将不再叙述。
请参阅图2所示，为本发明的芯片封装结构的第二实施例的一侧视图。在此方式中，芯片封装结构2同样包含一第一芯片21、一第二芯片22、一转接元件23及复数个金属引线24。第二实施例的芯片封装结构2与前述芯片封装结构1的差异在于：还包含一粘着层25。
粘着层25设置于第一芯片21的上表面212与转接元件23之间，以使转接元件23粘于第一芯片21的上表面212上，不易相对第一芯片21移动。此外，粘着层25可为粘性胶带、可固化的粘胶等具有粘性且不会导通电能的物体，以使被粘着层25覆盖的第一芯片21与转接元件23不会有短路的问题。而本实施例中，粘着层25具体为一芯片接合膜(Die Attach Film)。
请参阅图3所示，为本发明的芯片封装结构的第三实施例的一侧视图。在此方式中，芯片封装结构3同样包含一第一芯片31、一第二芯片32、一转接元件33、复数个金属引线34及一粘着层35，而芯片封装结构3与前述芯片封装结构1或2的差异在于：转接元件33还设置于第二芯片32的上表面322上，并与第二芯片32电性连接。
具体地说，转接元件33同时设置于第一芯片31的上表面312及第二芯片的上表面322，横跨第一芯片31及第二芯片32之间的间距，且粘着层35也设置于第二芯片的上表面322。
当转接元件33同时设置于第一芯片31及第二芯片32上时，转接元件33的长度(或宽度)可大于第一芯片31的长度(或宽度)。换言之，转接元件33的尺寸会比第一实施例的转接元件11的尺寸大，使得转接元件33上可安排更复杂的线路或更多的电子元件，以使芯片封装结构3能处理更复杂的资讯或有更多的功能。此外，第一芯片31及第二芯片32之间的电性连接可通过转接元件33来实现，以节省金属引线34的数目。
请参阅图4A及图4B，分别为本发明的芯片封装结构的第四实施例的俯视图及侧视图。芯片封装结构4同样包含一第一芯片41、一第二芯片42、一转接元件43、复数个金属引线44及一粘着层45，而与前述第三实施例的芯片封装结构3的差异在于：芯片封装结构4还包含复数个金属引脚46(或称金手指)及一封装胶体47。
上述金属引脚46可与第一芯片41或第二芯片42并排，亦可设置于第一芯片41或第二芯片42的下方，且上述金属引脚46可通过金属引线44来与第一芯片41或第二芯片42电性连接。本实施例中，上述金属引脚46为与第二芯片42间隔地并排，即第二芯片42设置于上述金属引脚46与第一芯片41之间，且金属引脚46通过金属引线44与第二芯片42电性连接。
封装胶体47包覆第一芯片41、第二芯片42、转接元件43、上述金属引脚46及金属引线44。上述金属引脚46各具有一从封装胶体47中暴露出的表面461，即上述金属引脚46的下表面未受到封装胶体47包覆。如此，上述金属引脚46的表面461可作为芯片封装结构4与外部电子元件或电路板（图未示出）连接的媒介。
请参阅图5A及图5B，分别为本发明的芯片封装结构5的第五实施例的俯视图及侧视图。芯片封装结构5包含一第一芯片51、一第二芯片52、一转接元件53、复数个金属引线54及一粘着层55，芯片封装结构5类似第二实施例的芯片封装结构2，而差异在于：本实施例的芯片封装结构5还包含一基板56。
第一芯片51及第二芯片52设置于基板56上，而基板56具有一电源焊垫(power bar)561及一接地焊垫(ground bar)562；电源焊垫561及接地焊垫562设置于基板56的一上表面563，并位于第一芯片51及第二芯片52之间。
第一芯片51及第二芯片52还进一步电性连接基板56。详细地说，第二焊垫521的其中一个借由引线键合方式(金属引线54)电性连接电源焊垫561，而上述第二焊垫521的另一个借由引线键合方式电性连接接地焊垫562。第一焊垫511的其中一个也可借由引线键合方式来电性连接电源焊垫561或接地焊垫562。
由于电源焊垫561及接地焊垫562位于第一芯片51及第二芯片52之间，「用以连接第一芯片51及第二芯片52至电源焊垫561及接地焊垫562」的金属引线54的长度可减短，而金属引线54的配置亦可简化。
需说明的是，在本实施例中，第一芯片51与基板56之间及第二芯片52与基板56之间还可分别设置有一粘着层55，以使第一芯片51及第二芯片52粘固于基板56的上表面563上。
请参阅图5C，在本实施例中，芯片封装结构5亦可加入具有其它功能的一第三芯片57及一第四芯片58。第三芯片57可设置于转接元件53上，并与转接元件53电性连接；而第四芯片58可设置于第一芯片51上，并与第一芯片51电性连接。
以上为本发明的芯片封装结构的各实施例的说明。接着说明本发明的芯片封装结构的制造方法，该制造方法至少可制作出上述这些芯片封装结构1至5。然而需说明的是，本发明的芯片封装结构并不局限由本发明的芯片封装结构的制造方法来制作。
请参阅图6所示，为本发明的芯片封装结构的制造方法的一流程图。首先，如步骤601所示，提供一第一芯片，该第一芯片具有复数个第一焊垫，这些第一焊垫形成于第一芯片的一上表面。接着如步骤602所示，提供一第二芯片，第二芯片具有复数个第二焊垫，这些第二焊垫形成于第二芯片的一上表面；如步骤603所示，并排第一芯片与第二芯片，并电性连接第一芯片与第二芯片；如步骤604所示，放置一转接元件于第一芯片的上表面上，并电性连接转接元件与第一芯片及/或第二芯片。借由以上步骤即可制造出如第一实施例所示的芯片封装结构（如图1所示）。
或者，在步骤603后，可如步骤605所示，设置一粘着层于第一芯片的上表面，再如步骤606所示，放置转接元件于粘着层上，使得转接元件粘于第一芯片的上表面上，便可制造出如第二实施例所示的芯片封装结构（如图2所示）。
又或者，在步骤603后，可如步骤607所示，将转接元件同时放置于第一芯片的上表面上及第二芯片的上表面上，并电性连接转接元件、第一芯片与第二芯片，借此可制造出如第三实施例所示的芯片封装结构（如图3所示）。
放置转接元件于第一芯片上后，可如步骤608所示，将复数个金属引脚与第一芯片或第二芯片并排，或者如步骤609所示，将复数个金属引脚设置于第一芯片或第二芯片下方，接着电性连接上述金属引脚与第一芯片或第二芯片。再如步骤610所示，使用一封装胶体包覆第一芯片、第二芯片、转接元件及上述金属引脚，并使得上述金属引脚的每一个的一表面从封装胶体中暴露出，借此便可制造出如第四实施例所示的芯片封装结构（如图4A及图4B所示）。
或者，在放置转接元件于第一芯片上后，接着可如步骤611所示，将第一芯片及第二芯片设置于一基板上。基板可具有一电源焊垫及一接地焊垫，电源焊垫及接地焊垫设置于基板的一上表面，并位于第一芯片及第二芯片之间；然后借由引线键合方式电性连接上述第一焊垫的其中一个与电源焊垫或接地焊垫，并借由引线键合方式电性连接上述第二焊垫的其中一个与电源焊垫或接地焊垫，即可制造如第五实施例的芯片封装结构（如图5A及图5B所示）。
在步骤611后，可如步骤612所示，再设置另一芯片于第一芯片上，且与转接元件并排；也可将该另一芯片设置于转接元件上，再将该另一芯片与转接元件、第一芯片或第二芯片电性连接（如图5C所示）。
借由上述芯片封装结构的制造方法，各种芯片封装结构可被制造出。
综上所述，本发明的芯片封装结构及其制造方法至少可具有下列特点：
1.芯片封装结构可不需像公知般具有一个大于芯片的底面积的基板，因此相较于公知技术而言，芯片封装结构可具有较小的尺寸。
2.因为第一芯片与第二芯片为并排，而非堆叠，故芯片封装结构的整体厚度可较小，以利于应用于厚度较薄的电子产品中。
3.芯片封装结构的转接元件可使芯片之间的引线键合距离及引线键合高度减少，且转接元件本身可包含天线、电容器、电感器等元件，以扩充芯片封装结构的功能。
上述的实施例仅用来例举本发明的实施方式，以及阐释本发明的技术特征，并非用来限制本发明的保护范畴。任何熟悉此技术者可轻易完成的改变或均等性的安排均属于本发明所主张的范围，本发明的权利保护范围应以申请专利范围为准。

Claims (17)

1.一种芯片封装结构，包含：
一第一芯片，具有复数个第一焊垫，所述第一焊垫形成于该第一芯片的一上表面；
一第二芯片，具有复数个第二焊垫，所述第二焊垫形成于该第二芯片的一上表面，该第一芯片与该第二芯片并排，且该第二芯片与该第一芯片电性连接；以及
一转接元件，设置于该第一芯片的该上表面上，并与该第一芯片电性连接。
2.如权利要求1所述的芯片封装结构，其中所述第一焊垫的其中一个借由引线键合方式电性连接所述第二焊垫的其中一个。
3.如权利要求1所述的芯片封装结构，其中该转接元件具有复数个第三焊垫，所述第三焊垫形成于该转接元件的一上表面，所述第一焊垫的其中一个借由引线键合方式电性连接所述第三焊垫的其中一个。
4.如权利要求3所述的芯片封装结构，其中所述第二焊垫的其中一个借由引线键合方式电性连接所述第三焊垫的其中一个。
5.如权利要求1所述的芯片封装结构，还包含一粘着层，设置于该第一芯片的该上表面与该转接元件之间，以使该转接元件粘于该第一芯片的该上表面上。
6.如权利要求1所述的芯片封装结构，其中该转接元件具有复数个第三焊垫，所述第三焊垫形成于该转接元件的一下表面，所述第一焊垫的其中一个借由倒晶方式电性连接所述第三焊垫的其中一个。
7.如权利要求1所述的芯片封装结构，其中该转接元件还设置于该第二芯片的该上表面上，并与该第二芯片电性连接。
8.如权利要求1所述的芯片封装结构，还包含复数个金属引脚，与该第一芯片或该第二芯片并排，或设置于该第一芯片或该第二芯片的下方，且与该第一芯片或该第二芯片电性连接。
9.如权利要求8所述的芯片封装结构，还包含：一封装胶体，包覆该第一芯片、该第二芯片、该转接元件及所述金属引脚，所述金属引脚各具有一从该封装胶体中暴露出的表面。
10.如权利要求1所述的芯片封装结构，还包含一基板，该第一芯片及该第二芯片设置于该基板上，该基板具有一电源焊垫及一接地焊垫，该电源焊垫及该接地焊垫设置于该基板的一上表面，并位于该第一芯片及该第二芯片之间。
11.如权利要求10所述的芯片封装结构，其中所述第一焊垫的其中一个借由引线键合方式电性连接该电源焊垫或该接地焊垫，而所述第二焊垫的其中一个借由引线键合方式电性连接该电源焊垫或该接地焊垫。
12.一种芯片封装结构的制造方法，包含：
提供一第一芯片，该第一芯片具有复数个第一焊垫，所述第一焊垫形成于该第一芯片的一上表面；
提供一第二芯片，该第二芯片具有复数个第二焊垫，所述第二焊垫形成于该第二芯片的一上表面；
将该第一芯片与该第二芯片并排，并电性连接该第一芯片与该第二芯片；以及
放置一转接元件于该第一芯片的该上表面上，并电性连接该转接元件与该第一芯片及/或第二芯片。
13.如权利要求12所述的芯片封装结构的制造方法，还包含：
设置一粘着层于该第一芯片的该上表面；
放置该转接元件于该粘着层上，使得该转接元件粘于该第一芯片的该上表面上。
14.如权利要求12所述的芯片封装结构的制造方法，还包含：放置该转接元件于该第二芯片的该上表面上，并电性连接该转接元件与该第二芯片。
15.如权利要求12所述的芯片封装结构的制造方法，还包含：将复数个金属引脚与该第一芯片或该第二芯片并排，或置于该第一芯片或该第二芯片的下方，并电性连接所述金属引脚与该第一芯片或该第二芯片。
16.如权利要求15所述的芯片封装结构的制造方法，还包含：使用一封装胶体包覆该第一芯片、该第二芯片、该转接元件及所述金属引脚，并使得所述金属引脚的每一个的一表面从该封装胶体中暴露出。
17.如权利要求12所述的芯片封装结构的制造方法，还包含：
将该第一芯片及该第二芯片设置于一基板上，其中，该基板具有一电源焊垫及一接地焊垫，该电源焊垫及该接地焊垫设置于该基板的一上表面，并位于该第一芯片及该第二芯片之间；
借由引线键合方式电性连接所述第一焊垫的其中一个与该电源焊垫或该接地焊垫；以及
借由引线键合方式电性连接所述第二焊垫的其中一个与该电源焊垫或该接地焊垫。
CN201210331064.0A 2011-09-09 2012-09-07 芯片封装结构及其制造方法 Active CN103000588B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW100132669A TWI481001B (zh) 2011-09-09 2011-09-09 晶片封裝結構及其製造方法
TW100132669 2011-09-09

Publications (2)

Publication Number Publication Date
CN103000588A true CN103000588A (zh) 2013-03-27
CN103000588B CN103000588B (zh) 2015-09-16

Family

ID=47829130

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210331064.0A Active CN103000588B (zh) 2011-09-09 2012-09-07 芯片封装结构及其制造方法

Country Status (3)

Country Link
US (1) US10651146B2 (zh)
CN (1) CN103000588B (zh)
TW (1) TWI481001B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786339A (zh) * 2016-11-13 2019-05-21 南亚科技股份有限公司 半导体封装与其制造方法
CN110518003A (zh) * 2019-08-30 2019-11-29 甬矽电子(宁波)股份有限公司 芯片封装结构和芯片封装方法
CN111492476A (zh) * 2017-10-10 2020-08-04 Z格鲁公司 具有引线框架的灵活且集成的模块封装的组装
CN112713130A (zh) * 2019-10-24 2021-04-27 瑞昱半导体股份有限公司 半导体封装
WO2024082345A1 (zh) * 2022-10-17 2024-04-25 长鑫存储技术有限公司 半导体封装结构

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9418974B2 (en) 2014-04-29 2016-08-16 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods
US9379032B2 (en) * 2014-09-15 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packaging having warpage control and methods of forming same
US10049953B2 (en) * 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
TWI713186B (zh) * 2019-10-21 2020-12-11 瑞昱半導體股份有限公司 半導體封裝
KR20230004147A (ko) * 2021-06-30 2023-01-06 삼성전자주식회사 반도체 패키지
CN115064488B (zh) * 2022-08-18 2022-11-01 成都复锦功率半导体技术发展有限公司 一种芯片互连封装结构及其制备方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5552966A (en) * 1990-12-20 1996-09-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board and method for manufacturing same
US5723906A (en) * 1996-06-07 1998-03-03 Hewlett-Packard Company High-density wirebond chip interconnect for multi-chip modules
CN1241032A (zh) * 1998-06-26 2000-01-12 国际商业机器公司 高集成度芯片上芯片封装
CN1485914A (zh) * 2002-09-29 2004-03-31 矽品精密工业股份有限公司 开窗型多芯片半导体封装件
CN1561545A (zh) * 2001-09-28 2005-01-05 摩托罗拉公司 带多行焊接焊盘的半导体芯片
CN1572024A (zh) * 2001-08-17 2005-01-26 高通股份有限公司 晶片堆叠的方法和装置
CN101355040A (zh) * 2007-07-23 2009-01-28 矽品精密工业股份有限公司 多芯片堆叠结构及其制法
US20090079066A1 (en) * 2007-09-21 2009-03-26 Ki Youn Jang Integrated circuit packaging system with passive components
US20090309237A1 (en) * 2006-03-09 2009-12-17 Seng Guan Chow Semiconductor package system with substrate having different bondable heights at lead finger tips
US20100019391A1 (en) * 2008-07-22 2010-01-28 Infineon Technologies Ag Semiconductor Device
CN102110678A (zh) * 2009-12-31 2011-06-29 日月光半导体制造股份有限公司 半导体封装件及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
JPH0878605A (ja) * 1994-09-01 1996-03-22 Hitachi Ltd リードフレームおよびそれを用いた半導体集積回路装置
US6682954B1 (en) * 1996-05-29 2004-01-27 Micron Technology, Inc. Method for employing piggyback multiple die #3
JPH11265975A (ja) 1998-03-17 1999-09-28 Mitsubishi Electric Corp 多層化集積回路装置
JP4091838B2 (ja) * 2001-03-30 2008-05-28 富士通株式会社 半導体装置
TWI245429B (en) * 2003-12-23 2005-12-11 Siliconware Precision Industries Co Ltd Photosensitive semiconductor device, method for fabricating the same and lead frame thereof
US7786572B2 (en) * 2005-09-13 2010-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. System in package (SIP) structure
US8310060B1 (en) * 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US7518226B2 (en) * 2007-02-06 2009-04-14 Stats Chippac Ltd. Integrated circuit packaging system with interposer
US7911053B2 (en) * 2007-04-19 2011-03-22 Marvell World Trade Ltd. Semiconductor packaging with internal wiring bus

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5552966A (en) * 1990-12-20 1996-09-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board and method for manufacturing same
US5723906A (en) * 1996-06-07 1998-03-03 Hewlett-Packard Company High-density wirebond chip interconnect for multi-chip modules
CN1241032A (zh) * 1998-06-26 2000-01-12 国际商业机器公司 高集成度芯片上芯片封装
CN1572024A (zh) * 2001-08-17 2005-01-26 高通股份有限公司 晶片堆叠的方法和装置
CN1561545A (zh) * 2001-09-28 2005-01-05 摩托罗拉公司 带多行焊接焊盘的半导体芯片
CN1485914A (zh) * 2002-09-29 2004-03-31 矽品精密工业股份有限公司 开窗型多芯片半导体封装件
US20090309237A1 (en) * 2006-03-09 2009-12-17 Seng Guan Chow Semiconductor package system with substrate having different bondable heights at lead finger tips
CN101355040A (zh) * 2007-07-23 2009-01-28 矽品精密工业股份有限公司 多芯片堆叠结构及其制法
US20090079066A1 (en) * 2007-09-21 2009-03-26 Ki Youn Jang Integrated circuit packaging system with passive components
US20100019391A1 (en) * 2008-07-22 2010-01-28 Infineon Technologies Ag Semiconductor Device
CN102110678A (zh) * 2009-12-31 2011-06-29 日月光半导体制造股份有限公司 半导体封装件及其制造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786339A (zh) * 2016-11-13 2019-05-21 南亚科技股份有限公司 半导体封装与其制造方法
CN111492476A (zh) * 2017-10-10 2020-08-04 Z格鲁公司 具有引线框架的灵活且集成的模块封装的组装
CN110518003A (zh) * 2019-08-30 2019-11-29 甬矽电子(宁波)股份有限公司 芯片封装结构和芯片封装方法
CN112713130A (zh) * 2019-10-24 2021-04-27 瑞昱半导体股份有限公司 半导体封装
WO2024082345A1 (zh) * 2022-10-17 2024-04-25 长鑫存储技术有限公司 半导体封装结构

Also Published As

Publication number Publication date
CN103000588B (zh) 2015-09-16
US10651146B2 (en) 2020-05-12
TWI481001B (zh) 2015-04-11
TW201312723A (zh) 2013-03-16
US20130062783A1 (en) 2013-03-14

Similar Documents

Publication Publication Date Title
CN103000588B (zh) 芯片封装结构及其制造方法
CN104769714B (zh) 包括交替形成台阶的半导体裸芯堆叠的半导体器件
TWI570853B (zh) 具有包含交錯晶粒及有效線接合之晶粒堆疊配置的半導體裝置
US9240393B2 (en) High yield semiconductor device
CN101414603B (zh) 层叠半导体封装及其制造方法
KR20100022930A (ko) 옵셋 다이 적층에서의 반도체 다이 지지
CN102110672B (zh) 芯片堆叠封装结构及其制造方法
US20130015589A1 (en) Chip-on-package structure for multiple die stacks
CN103250246A (zh) 具有线上膜及铜线的薄型多晶片堆迭封装件的方法及系统
US8736075B2 (en) Semiconductor chip module, semiconductor package having the same and package module
CN104183555B (zh) 半导体封装件及其制法
US8143707B2 (en) Semiconductor device
CN100559582C (zh) 芯片堆栈封装结构及其制造方法
KR20040069392A (ko) 적층형 반도체 멀티 칩 패키지
US20090206460A1 (en) Intermediate Bond Pad for Stacked Semiconductor Chip Package
CN101315921B (zh) 芯片堆栈封装结构及其制造方法
JPH10242379A (ja) 半導体モジュール
CN104103605A (zh) 半导体封装件及其制法
JPH02229461A (ja) 半導体装置
CN101853845B (zh) 多芯片堆叠封装
TW201423938A (zh) 具特性阻抗控制之導線架式半導體封裝構造
CN103928416B (zh) 具有无源器件的半导体封装件及其堆叠方法
CN101290918B (zh) 芯片封装结构
CN111063664A (zh) 一种模块化多芯片封装结构及其封装方法
CN105742283A (zh) 倒置堆叠封装件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20190201

Address after: No. 81, Section 5, Pudingli Road, East District, Xinzhu City, Taiwan, China

Patentee after: Jingyuan Electronic Co., Ltd.

Address before: 118 Zhonghua Road, Zhunan Town, Miaoli County, Taiwan, China

Patentee before: Dawning Leading Technology Inc.