TWI570853B - 具有包含交錯晶粒及有效線接合之晶粒堆疊配置的半導體裝置 - Google Patents

具有包含交錯晶粒及有效線接合之晶粒堆疊配置的半導體裝置 Download PDF

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TWI570853B
TWI570853B TW100125859A TW100125859A TWI570853B TW I570853 B TWI570853 B TW I570853B TW 100125859 A TW100125859 A TW 100125859A TW 100125859 A TW100125859 A TW 100125859A TW I570853 B TWI570853 B TW I570853B
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die
semiconductor
semiconductor die
substrate
axis
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TW100125859A
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TW201222737A (en
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廖智清
奇門 育
李雅惠
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桑迪士克科技有限責任公司
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Publication of TW201222737A publication Critical patent/TW201222737A/zh
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Description

具有包含交錯晶粒及有效線接合之晶粒堆疊配置的半導體裝置
本技術係關於半導體封裝。
對於攜帶型消費型電子器件之需求的強烈增長正推動對於高容量儲存裝置之需要。諸如快閃記憶體儲存卡之非揮發性半導體記憶體裝置被日益廣泛使用，以滿足對數位資訊儲存及交換之不斷增長之需求。該等非揮發性半導體記憶體裝置之可攜性、通用性及耐用設計連同其高可靠性及大容量已使此等記憶體裝置理想地用於包含(例如)數位相機、數位音樂播放器、視訊遊戲主機、PDA及蜂巢式電話之廣泛多種電子裝置中。
雖然已知廣泛多種封裝組態，但一般可由所謂的3-D半導體裝置製造快閃記憶體儲存卡。此等裝置包含(例如)系統級封裝(SiP)或多晶片模組(MCM)，其中複數個晶粒以堆疊組態安裝於基板上。習知3-D半導體封裝20(不具有模製化合物)之邊視圖經展示於先前技術之圖1及圖2中。典型封裝包含安裝至基板26之複數個半導體晶粒22。在所展示實例中，晶粒堆疊具有四個晶粒22a、22b、22c及22d。其他實例在堆疊中具有或多或少之晶粒。雖然未在圖1及圖2中展示，但半導體晶粒22經形成有在晶粒之上部表面上的晶粒接合襯墊。基板26可由被包夾於上部與下部導電層之間的電絕緣核心形成。可蝕刻上部及/或下部導電層以形成包含電導線及接觸襯墊之傳導圖案。以熱超音波方式將線接合30焊接於半導體晶粒22之晶粒接合襯墊與基板26之接觸襯墊之間以使半導體晶粒電耦接至該基板。基板上之電導線又在晶粒與主機裝置之間提供電路徑。一旦已進行晶粒與基板之間的電連接，接著就通常將該裝配件裝入於模製化合物中以提供保護封裝。
已知以偏移組態(先前技術之圖1)或以對準組態(先前技術之圖2)將半導體晶粒22彼此堆疊。在圖1之偏移組態中，以一偏移堆疊晶粒22，以便下一較低晶粒之接合襯墊被曝露且可由線接合裝置近接。此等組態經展示於(例如)Lin等人之題為「Multichip Module Having a Stacked Chip Arrangement」之美國專利第6,359,340號中，該專利之全部內容以引用之方式併入本文中。偏移組態提供方便地近接半導體晶粒中之每一者上之接合襯墊的優點。然而，該偏移在空間非常珍貴之基板上要求較大佔據面積。
在先前技術之圖2的對準組態中，半導體晶粒22直接彼此堆疊，藉此與偏移組態相比在基板上佔據較少佔據面積。然而，在對準組態中，必須在鄰近半導體晶粒之間提供用於接合線30之空間。除了接合線30自身之高度以外，該等接合線上方必須留有額外空間，此係因為一個晶粒之接合線30與上方之下一個晶粒的接觸可導致電短路。因此，如圖2中所示，已知提供介電間隔層34以為待接合於鄰近晶粒22之間的接合線30提供足夠空間。對間隔層之要求增加了晶粒堆疊之高度且係可包含於該堆疊中而仍在標準記憶卡外形尺寸之高度範圍內的晶粒數目的限制因子。
雖然先前技術之圖1及圖2中所展示之佈線組態可能可用於晶粒堆疊中具有較小數目之晶粒的半導體，但具有大於四個晶粒之晶粒堆疊中的晶粒的佈線變得更有問題。除了垂直線接合以外，可能需要對角地進行線接合及/或可要求額外基板接觸襯墊。先前技術之圖3及圖4為包含安裝至基板26之八個晶粒之典型NAND半導體封裝20(不具有模製化合物)的俯視圖及側視圖。圖3展示任意x-y軸線。習知地，晶粒22自晶粒0開始且順序地進行至晶粒7沿x軸線以一偏移彼此堆疊。
如所提及，基板26包含接觸襯墊，諸如先前技術之圖3中所展示之接觸襯墊38。包含大數目之晶粒的晶粒堆疊可需要兩組接觸襯墊38以實現至堆疊中之晶粒的輸入/輸出(I/O)。在圖3及圖4之實例中，各別晶粒0-3上之對應晶粒接合襯墊40彼此連接，且經由自晶粒0之接合襯墊40延伸至接觸襯墊38a的一組線接合30a連接至基板26上之第一組接觸襯墊38a。如本文中所使用，不同晶粒上之「對應」晶粒接合襯墊指代沿y軸線彼此對準之不同晶粒上的晶粒接合襯墊。因此，自圖3的角度來看，每一晶粒0-3上之第一(最底部)晶粒襯墊彼此對應，且線接合在一起，晶粒0-3中之每一者上的第二最底部晶粒襯墊彼此對應且線接合在一起，等等。
類似地，各別晶粒4-7上之對應晶粒接合襯墊40彼此連接，且經由自晶粒4之接合襯墊40延伸至接觸襯墊38b的一組線接合30b連接至基板26上之第二組接觸襯墊38b。在所展示之實施例中，接觸襯墊38a可與基板上之接觸襯墊38b交替。透過此類佈線組態，用於線接合之線長度將很長，且堆疊中之晶粒之間的線間間隔可變小至在線之間發生電短路的程度。此情況導致封裝失效及對裝配件良率的不利影響。
為了最小化上文所描述之問題，使用晶粒堆疊旋轉，如先前技術之圖5及圖6之俯視圖及側視圖中所展示。在圖5及圖6之實例中，第一組晶粒0-3在第一方向上偏移堆疊，且經由線接合30a連接至基板26之第一側上的一組接觸襯墊38a。第二組晶粒4-7在與該第一方向相反之第二方向上偏移堆疊，且經由線接合30b連接至基板26之與該第一側相反之第二側上的一組接觸襯墊38b。
晶粒堆疊旋轉之一個缺點為附接且線接合第一組晶粒0-3且接著附接且線接合第二組晶粒4-7。多個晶粒附接及線接合程序增加循環時間，且歸因於在製造期間對半導體封裝之較多處置而造成較低裝配件良率。需要允許兩個晶粒組線接合至基板上之兩個接觸襯墊組的晶粒堆疊設計，而同時避免上文所描述之問題。
習知堆疊封裝之另一缺點為接合線曝露於最終囊封之封裝之外。此問題為具有不規則封裝輪廓的記憶體封裝(諸如，microSD及MsMicro)所特有。先前技術之圖7至圖9展示microSD記憶體封裝20中之堆疊晶粒的一實例。圖7及圖9進一步展示晶粒堆疊上方之控制器晶粒50。如上文所描述且如圖9中所展示，可使用晶粒堆疊旋轉來裝配晶粒堆疊。在此等實施例中，基板可具有沿封裝之第一邊緣之接觸襯墊38a，該等接觸襯墊38a與圖7中沿邊緣40所展示之第一晶粒組之鄰近晶粒接合襯墊對準。然而，假定封裝的不規則形狀，例如沿封裝20之邊緣42，則一些晶粒接合襯墊連接至自所連接之晶粒接合襯墊對角地間隔開的接觸襯墊38b。圖8展示圖7中之區域8-8的放大圖。當以封裝之最終形狀囊封並單切基板時，沿形狀不規則之邊緣42之一或多個線接合(諸如，線接合30a)可位於該囊封之外，或以其他方式不被容許地接近封裝邊緣。需要允許沿封裝之形狀不規則之邊緣的有效線接合而不使線曝露於已完成、經囊封之封裝之外的晶粒堆疊設計。
現參考圖10至圖24描述實施例，其係關於具有包含交錯晶粒及/或有效線接合之晶粒堆疊配置的半導體裝置。應理解，本發明可以許多不同形式體現，且不應解釋為限於本文中所闡述之實施例。實情為，提供此等實施例以便本發明將為詳盡且完整的且將本發明完全地傳達給熟習此項技術者。實際上，本發明意欲涵蓋此等實施之替代例、修改及等效物，該等替代例、修改及等效物包含於由所附申請專利範圍所定義之本發明之範疇及精神內。此外，在本發明之以下詳細描述中，闡述眾多特定細節以便提供對本發明之透徹理解。然而，一般熟習此項技術者將清楚瞭解，可在無此等特定細節之情況下實踐本發明。
本文所使用之術語「頂部」、「底部」、「上部」、「下部」、「垂直」及/或「水平」僅出於方便及說明性之目的，且不意謂限制本發明之描述，此係因為所參考之項目的位置可交換。
現將參考圖10之流程圖及展示製造之不同階段中之封裝100的圖11至圖19之不同視圖來描述根據本系統之一實施例之用於形成半導體封裝100的程序。最初參看圖11及圖12之俯視及透視圖，可在步驟210中將第一半導體晶粒102a安裝於基板120上。可在已知黏接或共晶晶粒接合程序中經由晶粒附接黏著劑將晶粒102a安裝至基板120。
晶粒102a可包含沿晶粒102a之邊緣106形成之晶粒接合襯墊104。應理解，所展示之晶粒接合襯墊104的數目係作為實例，且在其他實施例中晶粒102a中可存在或多或少之晶粒接合襯墊104。在實施例中，晶粒102a可為記憶體晶粒，諸如NAND快閃記憶體晶粒。然而，在其他實施例中晶粒102a可為其他類型之半導體晶粒，諸如NOR、DRAM及各種其他記憶體晶粒。
雖然未圖示，但基板120可為基板面板之部分以便根據本技術之半導體封裝可經分批處理以實現規模經濟性。雖然下文描述了單一半導體封裝之製造，但應理解以下描述可應用於形成於基板面板上的所有封裝。基板120可為多種不同晶片載體媒體，包含印刷電路板(PCB)、引線框或捲帶式自動接合(TAB)膠帶。在基板120為PCB之情況下，基板可由其上形成有頂部及/或底部導電層的核心形成。該核心可為各種介電材料，諸如聚醯亞胺積層、包含FR4及FR5之環氧樹脂、雙順丁烯二醯亞胺三嗪(BT)及其類似者。
導電層可由銅或銅合金、電鍍銅或電鍍銅合金、合金42(42FE/58NI)、鍍銅鋼或已知用於基板上的其他金屬或材料形成。導電層可經蝕刻成如已知用於在半導體晶粒102與外部裝置(未圖示)之間傳達信號的傳導圖案。基板120可額外包含在基板120之上部表面上形成接觸襯墊122的曝露之金屬部分。所展示之接觸襯墊122的數目僅作為實例，且在其他實施例中可存在或多或少之接觸襯墊。在半導體封裝為平台柵格陣列(LGA)封裝之情況下，接觸指(未圖示)亦可經界定於基板120之下部表面上。接觸襯墊122及/或接觸指可鍍有一或多個金層，例如在此項技術中已知之電鍍程序中。
可在兩個群組中提供沿基板120之邊緣124的接觸襯墊122：接觸襯墊122a及接觸襯墊122b。在實施例中，接觸襯墊122a與接觸襯墊122b交替。如下文所解釋，接觸襯墊122a與第一半導體晶粒群組連接，且接觸襯墊122b與第二半導體晶粒群組連接。
在步驟214中，第二晶粒102b可如圖11及圖12之俯視及透視圖中所展示地堆疊於晶粒102a上。晶粒102b可為與晶粒102a相同之記憶體晶粒，且可包含相似數目之晶粒接合襯墊104(但為了清晰且區別於諸圖中之晶粒102a起見而以輕微陰影展示晶粒102b)。據預期，在其他實施例中晶粒102a及102b無需具有相同組態。可以相對於晶粒102a之交錯且偏移之定向貼附晶粒102b。亦即，晶粒102b可沿y軸線相對於晶粒102a交錯，且沿x軸線相對於晶粒102a偏移。
晶粒102b可為交錯的，以便晶粒102b之晶粒接合襯墊104對準於晶粒102a之晶粒接合襯墊104之間(且反之亦然)。在一實施例中，晶粒102b可相對於晶粒102a向下移位達鄰近晶粒接合襯墊104之間(中心間)之距離的一半(沿y軸線)，以提供交錯位置。晶粒102b亦可相對於晶粒102a偏移達一距離(沿x軸線)，以便習知線接合裝置可近接接合線且將接合線附接至晶粒102a之晶粒接合襯墊104。
雖然晶粒102b經展示為相對於晶粒102a在負y方向(在圖11中向下)上交錯，但在其他實施例中在晶粒102a之接合襯墊104位於晶粒102b之晶粒接合襯墊104之間的前提下晶粒可在正y方向上交錯。
晶粒102a及102b一起形成晶粒堆疊132。在不同實施例中，晶粒堆疊132可具有不同數目之晶粒。再次參看圖10之流程圖，在步驟216處，若存在待添加至堆疊132之額外晶粒，則在步驟220中添加該額外晶粒。舉例而言，圖13及圖14展示包含八個半導體晶粒102a至102h的晶粒堆疊132之俯視及透視圖。應理解，在其他實施例中晶粒堆疊132可包含更少或更多數目之晶粒。
在將新的晶粒添加至該堆疊時，該新的晶粒相對於其安裝於的晶粒交錯且偏移。如上文所指出，在此實施例中晶粒102b相對於晶粒102a沿y軸線向下交錯。因此，晶粒102c可經添加至晶粒102b之頂部而沿y軸線向上交錯，以便晶粒102b之晶粒接合襯墊經定位於晶粒102c之晶粒接合襯墊104之間(且反之亦然)。在實施例中，晶粒102c可沿y軸線對準於晶粒102a之正上方(但沿x軸線偏移)。可類似地以相對於經添加至晶粒堆疊的所有剩餘晶粒安裝於的晶粒交錯且偏移的方式添加該等所有剩餘晶粒。
晶粒102b至102h中之每一者可相對於其安裝於的晶粒沿x軸線偏移一恆定量。另外，晶粒102b至102h中之每一者可相對於其安裝於的晶粒沿y軸線交替地向上及向下交錯。此交錯圖案可導致向上交錯且沿y軸線彼此對準之第一晶粒群組(102a、102c、102e、102g)。此交錯圖案亦可導致向下交錯且沿y軸線彼此對準之第二晶粒群組(102b、102d、102f、102h)。
如上文所論述，例如關於先前技術之圖3及圖4所論述，習知堆疊中之晶粒可以開始於晶粒0且順序進行至晶粒7(在八晶粒堆疊中)之偏移的方式安裝於彼此之上。如已知，為了唯一地定址堆疊中之每一晶粒，將每一晶粒上之某些晶粒接合襯墊用作晶片定址接腳。對於堆疊中之給定晶粒而言，至定址接腳中之一者的低電壓表示邏輯零且至定址接腳中之一者的高電壓表示邏輯一。因此，透過在每一晶粒上使用(例如)三個定址接腳，可順序地自堆疊底部之000(晶粒0)至該堆疊頂部之111(晶粒7)唯一地定址習知八晶粒堆疊中的每一晶粒。
根據本系統之一實施例，第一及第二晶粒群組可彼此穿插以便堆疊132中之晶粒的編號為如以下表1中所示。
如上文所說明，晶粒交替地交錯，以便在使用上述堆疊中之晶粒的次序的情況下，y軸線對準晶粒102a、102c、102e及102g之第一群組順序地包含晶粒0至晶粒3。類似地，y軸線對準晶粒102b、102d、102f及102h之第二群組順序地包含晶粒4至晶粒7。
應理解，在本技術之其他實施例中晶粒堆疊中之晶粒可以不同方式排序。舉例而言，表2展示在晶粒堆疊132中具有八個晶粒之實施例中之晶粒之次序的其他實例。
預期晶粒堆疊132中之晶粒的其他序列。
現參看圖15及圖16之俯視及透視圖，在步驟224中可使用線接合136將晶粒堆疊132中之晶粒線接合至基板120。詳言之，可線接合第一群組中之晶粒102a、102c、102e及102g使得群組中之每一晶粒上的對應晶粒接合襯墊104(沿y軸線)可線接合在一起。第一群組中之底部晶粒(晶粒102a)可線接合至基板120上之接觸襯墊122a之第一群組。類似地，第二群組中之晶粒102b、102d、102f及102h可線接合在一起使得該群組中之每一晶粒上的對應晶粒接合襯墊104(沿y軸線)可線接合在一起。第一群組中之底部晶粒(晶粒102b)可線接合至基板120上之接觸襯墊122b之第二群組。
可跨過晶粒堆疊之y軸線單遍執行線接合程序以便線接合第一晶粒群組上之第一組對應接合襯墊，線接合第二晶粒群組上之第一組對應接合襯墊，線接合第一晶粒群組上之第二組接合襯墊，線接合第二晶粒群組上之第二組接合襯墊，等等，直至形成圖15及圖16中所展示之所有線接合。或者，可形成用於第一晶粒群組之所有線接合，且接著可形成用於第二晶粒群組之所有線接合(或反之亦然)。可以前向或相反線接合程序形成線接合136。
因為第一及第二晶粒群組沿y軸線交錯，所以在該兩個群組之間無接合線之電短路的情況下該第一群組可彼此線接合且該第二群組可彼此線接合。因此，在(例如)圖15及圖16中所展示之本技術之實施例允許兩個獨立的晶粒群組線接合至彼此及基板，同時避免在先前技術中發現之問題。亦即，第一群組及第二群組可分別地線接合至基板而同時最小化線長度且防止電短路。此外，在所有晶粒安裝於堆疊中之後，可單遍執行該堆疊中之所有晶粒的線接合程序。此避免了在執行多晶粒附接及線接合程序之晶粒堆疊旋轉中存在的增加之循環時間及減少之良率。
在上文所描述之實施例中，線接合136可為未經塗覆的金，但其可替代地為銅、鋁或其他金屬。在本系統之另一實施例中，可用使線之表面不導電的聚合絕緣物預先使線接合絕緣。適用於本系統中之預先絕緣之線接合的兩個實例經揭示於題為「Resin Coated Bonding Wire,Method Of Manufacturing The Same,And Semiconductor Device」的美國專利第5,396,104號及題為「High Density Integrated Circuits And The Method Of Packaging the Same」之美國公開專利申請案第2004/0124545號中，該兩案之全部內容皆以引用之方式併入本文中。
現參看圖17及圖18之俯視及透視圖，一旦已在晶粒堆疊中提供所有晶粒102，則可在步驟228中將控制器晶粒140貼附於該堆疊之頂上。控制器晶粒140可為(例如)ASIC，但在其他實施例中可為其他控制器晶粒。在步驟232中，控制器晶粒140可線接合至基板120上之接觸襯墊122(為了清晰而僅在圖17及圖18中展示一些線接合)。在所展示之實例中，控制器晶粒140可具有遠離該晶粒之兩個鄰近邊緣的晶粒接合襯墊，該等晶粒接合襯墊接合至基板120之鄰近邊緣上的接觸襯墊122。在其他實施例中控制器晶粒140可具有沿單一邊緣或兩個以上邊緣的晶粒接合襯墊。
現參看圖19之邊視圖，在晶粒堆疊形成且線接合至基板120上之接合襯墊之後，可在步驟236中將該晶粒堆疊裝入於模製化合物146內。接著在步驟240中可自基板面板單切經囊封之封裝以形成已完成之半導體晶粒封裝100。模製化合物146可為已知之環氧樹脂，諸如可自皆在日本設有總部之Sumitomo公司及Nitto Denko公司購得的環氧樹脂。在一些實施例中，可在步驟242中視情況將已完成之封裝100封入於蓋狀物內。
如在先前技術部分中所闡述，對於形狀不規則之封裝而言，可發生沿封裝之形狀不規則之部分的一些線被模製於該封裝之外或過於靠近該封裝之邊緣。圖20為用於解決此問題之本技術之另一實施例的流程圖。在步驟310、314、316及320中，晶粒可堆疊於基板上。舉例而言，圖21及圖24展示包含附接至基板120之許多晶粒102a-102h的晶粒堆疊132的俯視及端視圖。如在圖21之俯視圖中所展示，基板120可具有不規則形狀，諸如microSD記憶體封裝之形狀。基板可在晶粒102安裝於該基板120上時具有不規則形狀，或基板可在晶粒安裝於該基板上之後被形成為不規則形狀。
在當前實施例中，可使用沿x軸線之晶粒堆疊旋轉來安裝晶粒，如圖24中所展示。然而，應理解，可使用沿x軸線之筆直偏移(諸如，圖13及圖14中所展示的)來堆疊晶粒。在當前實施例中，晶粒無需沿y軸線交錯，但可想到在其他實施例中晶粒為y軸線交錯的。
在步驟324中，晶粒可線接合至彼此且線接合至基板120上之接觸襯墊122。底部晶粒102a具有晶粒接合襯墊104a，晶粒102b具有接合襯墊104b，晶粒102c具有接合襯墊104c，等等。如上文所說明，各別晶粒上的沿y軸線彼此對應之晶粒接合襯墊104a、104b、104c等等可彼此線接合。
根據當前實施例，可自堆疊132中較高處之晶粒上的接合襯墊形成至基板120之一或多個線接合136，而非自底部晶粒102a之晶粒接合襯墊104a線接合至基板120。因此，舉例而言，可自晶粒102b上之晶粒接合襯墊104b形成至基板120之線接合136。如圖21及圖22之放大圖中所展示，藉由自較高接合襯墊(例如，接合襯墊104b)接合至基板120，線接合皆位於封裝輪廓內，自封裝之邊緣間隔開。在其他實施例中，可自晶粒102b上方之晶粒形成至基板之線接合。
在實施例中，可自最低晶粒的一或多個接合襯墊形成至基板120之線接合，其允許所有線被囊封於封裝內、自該封裝之邊緣間隔開。在先前技術之圖8中所展示之實例中，僅最上部之線接合(自圖9的角度來看)有問題。因此，在此類實例中，可僅將最上部之線接合移動至堆疊中之較高晶粒(如圖23之放大圖中所展示)。在圖23中，自晶粒102c上之接合襯墊104c形成最上部之線接合(自圖23的角度來看)。自最下部晶粒102a之接合襯墊104a形成至基板之剩餘線接合。預期其他線接合組態，其中自底部晶粒102a上方之晶粒形成至基板之線接合中的一或多者。
一旦針對此實施例在步驟324中執行線接合，則可如上文所描述進行剩餘步驟。在步驟332中，控制器晶粒140可線接合至基板120上之接觸襯墊122，如圖21及圖24之端視圖中所展示。此後，可在步驟336中將晶粒堆疊裝入於模製化合物146內，且接著可在步驟340中自基板面板單切經囊封之封裝，以形成已完成之半導體晶粒封裝100。在一些實施例中，可在步驟342中視情況將該已完成之封裝100封入於蓋狀物內。
在上文所描述之實施例中之任一者中，半導體晶粒102可為一或多個快閃記憶體晶片，以便與控制器晶粒140一起，封裝100可用作快閃記憶體裝置。應理解，在本系統之其他實施例中，封裝100可包含經組態以執行其他功能的半導體晶粒。上文所描述之實施例中之至少一些實施例中的封裝100可用於複數個標準記憶卡中，包含(不限制)緊密快閃卡、智慧媒體卡、記憶卡、安全數位卡、miniSD卡、microSD卡、USB記憶卡及其他標準記憶卡。
在實施例中，本技術係關於一種半導體裝置，其包含：一基板；一第一半導體晶粒，其安裝於該基板上且具有第一組晶粒接合襯墊，一x軸線及一y軸線平行於該第一半導體晶粒之正交邊緣；一第二半導體晶粒，其安裝於該第一半導體晶粒之頂部上且具有第二組晶粒接合襯墊，該第二半導體晶粒相對於該第一半導體晶粒沿該x軸線偏移，且該第二半導體晶粒相對於該第一半導體晶粒沿該y軸線交錯；第一組線接合，其在該第一組晶粒接合襯墊與該基板之間；及第二組線接合，其在該第二組晶粒接合襯墊與該基板之間，該第一及第二組線接合彼此穿插。
在其他實施例中，本技術係關於一種半導體裝置，其包含：一基板；一第一半導體晶粒，其安裝於該基板上，一x軸線及一y軸線經定義為平行於該第一半導體晶粒之正交邊緣；一第二半導體晶粒，其安裝於該第一半導體晶粒之頂部上，該第二半導體晶粒相對於該第一半導體晶粒沿該x軸線偏移，且該第二半導體晶粒相對於該第一半導體晶粒沿該y軸線交錯；及一第三半導體晶粒，其安裝於該第二半導體晶粒之頂部上，該第三半導體晶粒相對於該第二半導體晶粒沿該x軸線偏移，且該第三半導體晶粒沿該y軸線交錯以沿該y軸線與該第一半導體晶粒對準。
本技術之另一實施例係關於一種半導體裝置，其包括：一基板；一第一半導體晶粒群組，其安裝於該基板上，該第一半導體晶粒群組中之每一半導體晶粒具有第一組晶粒接合襯墊，一x軸線及一y軸線經定義為平行於該第一半導體晶粒群組中之該半導體晶粒的正交邊緣；一第二半導體晶粒群組，其安裝於該基板上，該第二半導體晶粒群組中之每一半導體晶粒具有第二組晶粒接合襯墊，來自安裝於該基板上之該第一及第二群組的半導體晶粒彼此穿插，其中來自該第一及第二群組之半導體晶粒相對於彼此沿該x軸線偏移，且其中來自該第一群組之半導體晶粒相對於來自該第二群組之半導體晶粒沿該y軸線交錯；第一組線接合，其電耦接該第一晶粒群組之該第一組晶粒接合襯墊中的對應晶粒接合襯墊；及第二組線接合，其電耦接該第二晶粒群組之該第二組晶粒接合襯墊中的對應晶粒接合襯墊，該第一及第二組線接合彼此穿插。
本技術之又一實施例係關於一種包含一形狀不規則之邊緣的半導體裝置，其包含：一基板，其具有一鄰近於該形狀不規則之邊緣的接觸襯墊；複數個半導體晶粒，其形成一附接至該基板之晶粒堆疊，一最下部半導體晶粒直接附接至該基板且該晶粒堆疊中之剩餘半導體晶粒附接至該最下部半導體晶粒；複數個對應晶粒接合襯墊，在該複數個半導體晶粒中之每一者上有一對應晶粒接合襯墊，該複數個對應晶粒接合襯墊在該複數個半導體晶粒上彼此對應；一組線接合，其使該複數個對應晶粒接合襯墊彼此電耦接，該組線接合包含自該最下部半導體晶粒上方之一半導體晶粒之一晶粒接合襯墊至該基板接觸襯墊的一線接合，其中該最下部半導體晶粒之該晶粒接合襯墊與該等基板接觸襯墊之間的一直線包含在該半導體裝置之該形狀不規則之邊緣之外的一部分。
已出於說明及描述之目的而呈現本發明之前述實施方式。其不欲為詳盡的或將本發明限於所揭示之精確形式。依據以上教示，許多修改及變更係可能的。選擇所描述之實施例，以便最好地解釋本發明之原理及其實務應用，藉此使得其他熟習此項技術者能夠在各種實施例中且以適於所預期特定用途之各種修改來最好地利用本發明。意欲由附加至此之申請專利範圍來界定本發明之範疇。
8-8．．．區域
20．．．3-D半導體封裝/NAND半導體封裝/microSD記憶體封裝
22．．．半導體晶粒
22a．．．晶粒
22b．．．晶粒
22c．．．晶粒
22d．．．晶粒
26．．．基板
30．．．線接合/接合線
30a．．．線接合
30b．．．線接合
34．．．介電間隔層
38．．．接觸襯墊
38a．．．接觸襯墊
38b．．．接觸襯墊
40．．．晶粒接合襯墊
42．．．邊緣
50．．．控制器晶粒
100．．．半導體晶粒封裝
102．．．半導體晶粒
102a．．．半導體晶粒
102b．．．晶粒
102c．．．晶粒
102d．．．晶粒
102e．．．晶粒
102f．．．晶粒
102g．．．晶粒
102h．．．晶粒
104．．．晶粒接合襯墊
104a．．．晶粒接合襯墊
104b．．．晶粒接合襯墊
104c．．．晶粒接合襯墊
104d．．．晶粒接合襯墊
106．．．邊緣
120．．．基板
122．．．接觸襯墊
122a．．．接觸襯墊
122b．．．接觸襯墊
124．．．邊緣
132．．．晶粒堆疊
136．．．線接合
140．．．控制器晶粒
146．．．模製化合物
圖1為包含以偏移關係堆疊之半導體晶粒的習知半導體裝置之先前技術之邊視圖。
圖2為包含以對準關係堆疊且由間隔層分離之半導體晶粒的習知半導體裝置之先前技術之邊視圖。
圖3為包含線接合至基板之八個半導體晶粒的半導體晶粒堆疊之先前技術之俯視圖。
圖4為圖3中所展示之半導體晶粒堆疊的先前技術之側視圖。
圖5為包含八個半導體晶粒之旋轉晶粒堆疊的先前技術之俯視圖。
圖6為圖5中所展示之旋轉晶粒堆疊的先前技術之側視圖。
圖7為形狀不規則之半導體晶粒封裝的先前技術之俯視圖。
圖8為展示線接合在經囊封之封裝之外之一部分的圖7之一部分的先前技術之放大圖。
圖9為圖7中所展示之半導體封裝的先前技術之側視圖。
圖10為用於裝配根據本發明之一實施例的半導體封裝的流程圖。
圖11為根據本技術之在製造之第一階段期間之半導體封裝的俯視圖。
圖12為根據本技術之在製造之第一階段期間之半導體封裝的透視圖。
圖13為根據本技術之在製造之第二階段期間之半導體封裝的俯視圖。
圖14為根據本技術之在製造之第二階段期間之半導體封裝的透視圖。
圖15為根據本技術之在製造之第三階段期間之半導體封裝的俯視圖。
圖16為根據本技術之在製造之第三階段期間之半導體封裝的透視圖。
圖17為根據本技術之在製造之第四階段期間之半導體封裝的俯視圖。
圖18為根據本技術之在製造之第四階段期間之半導體封裝的透視圖。
圖19為以模製化合物囊封之根據本技術之已完成半導體封裝的邊視圖。
圖20為用於裝配根據本發明之一替代實施例的半導體封裝的流程圖。
圖21為根據本技術之另一實施例線接合之形狀不規則之半導體晶粒封裝的俯視圖。
圖22為說明根據本技術之一實施例之線接合的圖21之半導體封裝之一部分的放大圖。
圖23說明根據本技術之另一實施例的如圖22中之半導體封裝之一部分。
圖24為囊封於模製化合物內的根據本技術之一實施例之已完成半導體封裝的側視圖。
100．．．半導體晶粒封裝
102a．．．半導體晶粒
102b．．．半導體晶粒
102c．．．半導體晶粒
102d．．．半導體晶粒
102e．．．半導體晶粒
102f．．．半導體晶粒
102g．．．半導體晶粒
102h．．．半導體晶粒
120．．．基板
122．．．接觸襯墊
136．．．線接合
140．．．控制器晶粒

Claims (20)

  1. 一種半導體裝置，其包括：一基板，其包括一單一行之對準的接觸襯墊；一第一半導體晶粒，其安裝於該基板上且具有一第一組晶粒接合襯墊，一x軸線及一y軸線平行於該第一半導體晶粒之正交邊緣；一第二半導體晶粒，其安裝於該第一半導體晶粒之頂部上且具有一第二組晶粒接合襯墊，該第二半導體晶粒相對於該第一半導體晶粒沿該x軸線偏移，且該第二半導體晶粒相對於該第一半導體晶粒沿該y軸線交錯；一第一組線接合(wire bonds)，其在該第一組晶粒接合襯墊與該基板上之該單一行之對準的接觸襯墊中之接觸襯墊之間；及一第二組線接合，其在該第二組晶粒接合襯墊與該基板上之該單一行之對準的接觸襯墊中之接觸襯墊之間，該第一組線接合及該第二組線接合彼此穿插。
  2. 如請求項1之半導體裝置，其中該第一半導體晶粒及該第二半導體晶粒為快閃記憶體半導體晶粒。
  3. 如請求項1之半導體裝置，其中該第一半導體晶粒及該第二半導體晶粒為NAND半導體晶粒。
  4. 如請求項1之半導體裝置，其進一步包括一控制器晶粒，該控制器晶粒安裝於該第二半導體晶粒上且電連接至該基板。
  5. 如請求項4之半導體裝置，其進一步包括模製化合物， 該模製化合物至少圍繞該第一及第二半導體晶粒、該第一及第二組線接合及該控制器晶粒。
  6. 如請求項1之半導體裝置，其中該基板為一印刷電路板、一引線框及一捲帶式自動接合膠帶中之一者。
  7. 如請求項1之半導體裝置，該封裝包括一緊密快閃(CompactFlash)卡、一智慧媒體(SmartMedia)卡、一記憶卡(Memory Stick)、一安全數位(Secure Digital)卡、一迷你安全數位(miniSD)卡、一微安全數位(microSD)卡及一通用串列匯流排(USB)記憶卡中之一者。
  8. 如請求項1之半導體裝置，其中該第一及第二組線接合中之至少一者為電絕緣的。
  9. 一種半導體裝置，其包括：一基板；一第一半導體晶粒，其安裝於該基板上，一x軸線及一y軸線經定義為平行於該第一半導體晶粒之正交邊緣；一第二半導體晶粒，其安裝於該第一半導體晶粒之頂部上，該第二半導體晶粒相對於該第一半導體晶粒沿該x軸線偏移，且該第二半導體晶粒相對於該第一半導體晶粒沿該y軸線交錯；及一第三半導體晶粒，其安裝於該第二半導體晶粒之頂部上，該第三半導體晶粒相對於該第二半導體晶粒沿該x軸線偏移，且該第三半導體晶粒沿該y軸線交錯以沿該y軸線與該第一半導體晶粒對準。
  10. 如請求項9之半導體裝置，其進一步包括一第四半導體晶粒，其安裝於該第三半導體晶粒之頂部上，該第四半導體晶粒相對於該第三半導體晶粒沿該x軸線偏移，且該第四半導體晶粒沿該y軸線交錯以沿該y軸線與該第二半導體晶粒對準。
  11. 如請求項10之半導體裝置，其進一步包括：晶粒接合襯墊，其在該第一、第二、第三及第四半導體晶粒中之每一者上；一第一組接合線，其將該第一半導體晶粒及該第三半導體晶粒上之對應晶粒接合襯墊與該基板連接；及一第二組接合線，其將該第二半導體晶粒及該第四半導體晶粒上之對應晶粒接合襯墊與該基板連接。
  12. 如請求項11之半導體裝置，其中該第一及第二組接合線彼此穿插。
  13. 如請求項11之半導體裝置，其中該第一及第二組接合線中之至少一者為電絕緣的。
  14. 如請求項9之半導體裝置，其進一步包括一控制器晶粒。
  15. 如請求項9之半導體裝置，其進一步包括模製化合物，該模製化合物用於囊封該第一、第二及第三半導體晶粒。
  16. 一種半導體裝置，其包括：一基板；一第一半導體晶粒群組，其安裝於該基板上，該第一 半導體晶粒群組中之每一半導體晶粒具有一第一組晶粒接合襯墊，一x軸線及一y軸線經定義為平行於該第一半導體晶粒群組中之該半導體晶粒的正交邊緣；一第二半導體晶粒群組，其安裝於該基板上，該第二半導體晶粒群組中之每一半導體晶粒具有一第二組晶粒接合襯墊，來自安裝於該基板上之該第一群組及該第二群組的半導體晶粒彼此穿插，其中來自該第一群組及該第二群組之半導體晶粒沿該x軸線相對於彼此偏移，且其中來自該第一群組之半導體晶粒相對於來自該第二群組之半導體晶粒沿該y軸線交錯；一第一組線接合，其電耦接該第一晶粒群組之該第一組晶粒接合襯墊中的對應晶粒接合襯墊；及一第二組線接合，其電耦接該第二晶粒群組之該第二組晶粒接合襯墊中的對應晶粒接合襯墊，該第一組線接合及該第二組線接合彼此穿插。
  17. 如請求項16之半導體裝置，其中該第一半導體晶粒群組沿該y軸線彼此對準。
  18. 如請求項17之半導體裝置，其中該第二半導體晶粒群組沿該y軸線彼此對準。
  19. 如請求項16之半導體裝置，其中該第一半導體晶粒群組包含四個半導體晶粒，且該第二半導體晶粒群組包含四個半導體晶粒。
  20. 如請求項19之半導體裝置，其中出於定址之目的彼此堆疊的晶粒的次序為晶粒0、晶粒4、晶粒1、晶粒5、晶粒 2、晶粒6、晶粒3、晶粒7，其中晶粒0、晶粒1、晶粒2及晶粒3屬於該第一半導體晶粒群組，且晶粒4、晶粒5、晶粒6及晶粒7屬於該第二半導體晶粒群組。
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US20130207280A1 (en) 2013-08-15
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