TWI713186B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TWI713186B
TWI713186B TW108137819A TW108137819A TWI713186B TW I713186 B TWI713186 B TW I713186B TW 108137819 A TW108137819 A TW 108137819A TW 108137819 A TW108137819 A TW 108137819A TW I713186 B TWI713186 B TW I713186B
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Taiwan
Prior art keywords
chip
pads
semiconductor package
carrier substrate
present
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TW108137819A
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English (en)
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TW202117984A (zh
Inventor
羅欽元
莊南卿
張智豪
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瑞昱半導體股份有限公司
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Priority to TW108137819A priority Critical patent/TWI713186B/zh
Priority to US15/930,418 priority patent/US11227854B2/en
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Publication of TWI713186B publication Critical patent/TWI713186B/zh
Publication of TW202117984A publication Critical patent/TW202117984A/zh

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Abstract

一種半導體封裝，包含一載體基板，包含相對的一第一表面和一第二表面；一第一晶片和一第二晶片，以並排方式安裝在該載體基板的該第一表面上，其中該第一晶片在鄰近該第二晶片的一第一側邊上設置有複數個高速訊號接墊，該第二晶片在鄰近該第一晶片的一第二側邊上設置有複數個數據(DQ)接墊；以及複數條第一打線，直接電連接該複數個高速訊號接墊至該複數個數據(DQ)接墊。

Description

半導體封裝
本發明係有關於半導體封裝技術領域，更具體地說，本發明係有關於一種系統級封裝(System-in-Package，SiP)。
隨著便攜式電子設備變得更小，電子設備中的半導體封裝的尺寸也必須減小。為了實現這一點，系統級封裝(SiP)技術被廣泛使用，因為它可以增加半導體封裝的容量。第1圖繪示的是習知SiP封裝的剖面結構示意圖。如第1圖所示，習知SiP封裝1p係將複數個晶片C1、C2設置在一封裝基板S上，其中晶片C1、C2可以分別通過打線打線W1、W2接合至封裝基板S上的金手指F1、F2，再經由封裝基板S內的繞線T構成晶片C1、C2之間的訊號連結。
然而，晶片C1、C2之間的高速訊號連結，須經過打線W1、封裝基板S上的金手指F1、封裝基板S內的繞線T、封裝基板S上的金手指F2、打線W2構成的電連接路徑，而使用上述打線接合技術形成的訊號互連會有訊號完整性問題，例如由於電感阻抗不連續(impedance discontinuity)和打線之間的高串擾引起的高插入(high insertion)損失、高返回損失(high return loss)、裕度損失(margin loss)和通道諧振(channel resonance)。
本發明的主要目的即在提供一種改良的半導體封裝，可以改善上述先前技藝的不足與缺點。
根據本發明實施例，其係公開一種半導體封裝，包含一載體基板，包含相對的一第一表面和一第二表面；一第一晶片和一第二晶片，以並排方式安裝在該載體基板的該第一表面上，其中該第一晶片在鄰近該第二晶片的一第一側邊上設置有複數個高速訊號接墊，該第二晶片在鄰近該第一晶片的一第二側邊上設置有複數個數據(DQ)接墊；以及複數條第一打線，直接電連接該複數個高速訊號接墊至該複數個數據(DQ)接墊。
根據本發明實施例，其中該第一晶片和該第二晶片係以黏著層固定在該載體基板的該第一表面上。
根據本發明實施例，其中該載體基板的該第二表面上設置有複數個焊球。
根據本發明實施例，其中該複數個焊球為球型格柵陣列錫球。
根據本發明實施例，其中該第一晶片包含系統單晶片，該第二晶片包含晶粒堆疊或記憶體封裝。
根據本發明實施例，其中該記憶體封裝包含動態隨機存取記憶體封裝。
根據本發明實施例，其中該動態隨機存取記憶體封裝包含雙倍數據速率3(DDR3)晶粒或雙倍數據速率4(DDR4)晶粒。
根據本發明實施例，其中該第一晶片和該第二晶片的距離介於0.5mm至4.0mm之間。
根據本發明實施例，其中在該載體基板的該第一表面上，另設置有複數個被動元件。
根據本發明實施例，其中該被動元件包含電容、電感或電阻。
根據本發明實施例，其中該複數個數據(DQ)接墊係形成在一重佈線層上。
根據本發明實施例，其中該第二晶片在遠離該第一晶片的一第三側邊上設置有複數個指令/位址(CA)接墊。
根據本發明實施例，其中另包含複數條第二打線，直接電連接該複數個指令/位址(CA)接墊至該載體基板的該第一表面上相應的金手指。
根據本發明實施例，其中另包含一模封塑料，包覆該第一晶片和該第二晶片。
根據本發明實施例，其中該複數個高速訊號接墊係在2133MT/s、2400MT/s或2666MT/s的速率下進行資料傳輸。
根據本發明實施例，其中該第二晶片在該第二側邊和第三側邊之間的第四側邊上設置有複數個電源或接地(P/G)接墊。
根據本發明實施例，其中另包含複數條第三打線，直接電連接該複數個電源或接地(P/G)接墊至該載體基板的該第一表面上相應的金手指。
為讓本發明上述目的及特徵能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而，如下文中的較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制。
1:半導體封裝
1p:SiP封裝
10:載體基板
10a:第一表面
10b:第二表面
20:第一晶片
30:第二晶片
60:模封塑料
102、103、104、106、107、108:金手指
110:錫球焊墊
122:導通孔
140:被動元件
150:焊球
201、202:高速訊號接墊
222、223、224:輸入/輸出(I/O)接墊
301~306:接墊
210、310:黏著層
320:絕緣膜
d:距離
C1、C2:晶片
D1、D2:DRAM晶粒
E1~E8:側邊
F1、F2:金手指
h1、h2:線弧高
P0、P1:接墊位置
RDL1、RDL2:重佈線層
S:封裝基板
T:繞線
W1~W4:打線
WB2、WB3、WB4、WB7、WB8:打線
第1圖繪示的是習知SiP封裝的剖面結構示意圖。
第2圖為依據本發明一實施例所繪示的半導體封裝的上視透視圖。
第3圖為第2圖中沿著切線I-I’所示的剖面結構示意圖。
在下文中，將參照附圖說明細節，該些附圖中之內容亦構成說明書細節描述的一部份，並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述不應被視為是限制，反之，其 中所包含的實施例將由隨附的申請專利範圍來加以界定。
應當理解，儘管這裡可以使用術語“第一”、“第二”等描述各元件、區域、層和/或部分，但是這些元件、區域、層和/或部分不應受限於這些術語。這些術語僅用於將一個元件、區域、層或部分與另一元件、區域、層或部分區別開。因此，以下討論的第一元件、區域、層或部分可以被稱為第二元件、區域、層或部分而不背離示例性實施例的教導。
為便於描述此處可以使用諸如“在...之下”、“在...下面”、“下(lower)”、“在...之上”、“上(upper)”等空間相對性術語以描述如附圖所示的一個元件或特徵與另一個(些)元件或特徵之間的關係。應當理解，空間相對性術語是用來概括除附圖所示取向之外的器件在使用或操作中的不同取向的。 例如，如果把附圖中的器件翻轉過來，被描述為“在”其他元件或特徵“之下”或“下面”的元件將會在其它元件或特徵的“上方”。因此，示例性術語“在...下面”就能夠涵蓋之上和之下兩種取向。器件可以採取其他取向(如旋轉90度)，此處所用的空間相對性描述符則做相應解釋。
此中使用的術語“水平面(horizontal)”定義為平行於半導體晶片或晶片基板的主平面或主表面的平面，而不論其方向。術語“垂直”是指垂直於剛才定義的“水平面”的方向。當使用諸如“在......上”、“在......下”、“底部”、“頂部”、“側面(如“側壁(sidewall))”、“更高的”、“更低的”等術語時，均是指相對於水 平面的定義。
本發明涉及一種改良的半導體封裝，特別是打線接合系統級封裝(Wire-bonding System-in-Package，WBSiP)。如前所述，由於系統級封裝(SiP)技術能夠增加半導體封裝的容量，因此受到了廣泛應用。然而，SiP內的晶片之間的高速訊號連結，須經過打線、封裝基板上的金手指和封裝基板內的繞線所構成的電連接路徑，導致訊號失真問題。本發明可以改善這樣的問題。
下文中，用語“系統級封裝”或“SiP”係指複數個具有不同功能的IC晶片或晶粒模封在單一封裝體內。用語“打線接合系統級封裝”或“WBSiP”涉及將複數個晶片封裝在一起，且通過打線接合的方式彼此連接。用語“系統單晶片”或“SoC”係指將電腦或其他電子系統的各種元件整合在單一顆晶片中的積體電路。用語“known-good-die”或“kgd”係指已知合格晶粒。
請參閱第2圖及第3圖，其中，第2圖為依據本發明一實施例所繪示的半導體封裝的上視透視圖，第3圖為第2圖中沿著切線I-I’所示的剖面結構示意圖。如第2圖及第3圖所示，半導體封裝1包含一載體基板(carrier substrate)10，具有相對的一第一表面10a和一第二表面10b。半導體封裝1可以是系統級封裝。 根據本發明一實施例，於載體基板10的第一表面10a上至少設置有一第一晶片20和一第二晶片30。例如，第一晶片20和第二晶片30可以分別以黏著層210和310固定在載體基板10的第一表面10a上。在載體基板10的第二表面10b上設置有複數個焊球150，例如，球型格柵陣列(BGA)錫球。後續可以對焊球150進行回焊，以將半導體封裝1附著至PCB(Printed Circuit Board，印刷電路板)或母板(未示出)上。根據本發明一實施例，載體基板10可以是多層電路板或封裝基板。例如，載體基板10可以是兩層，三層或四層電路板，但不限於此。
舉例而言，載體基板10可以為有機封裝基板，包含金屬導線和樹脂，例如BT(bismalemide triazene)環氧樹脂等。熟習該項技藝者應能理解，可以使 用其他材料來形成載體基板10，例如，陶瓷或塑料。為簡化說明，第3圖中載體基板10的內部佈線(routing)僅示意的顯示出部分的金手指102、106和部分連通至錫球焊墊110的導通孔122，其中內部佈線可以將半導體晶粒的訊號電性耦接至第二表面10b上的焊球150。
根據本發明一實施例，例如，第一晶片20可以是系統單晶片(SoC)，而第二晶片30可以是晶粒堆疊或記憶體封裝，例如動態隨機存取記憶體(DRAM)封裝，具有一個以上的DRAM晶粒或DRAM kdg，例如，雙倍數據速率3(double data rate 3，DDR3)晶粒或雙倍數據速率4(double data rate 4，DDR4)晶粒等。第3圖中，為簡化說明，僅以兩個上下堆疊的DRAM晶粒D1和D2例示說明。根據本發明一實施例，DRAM晶粒D1和D2之間可以設置一絕緣膜320，例如，以膜包線(Film Over Wire，FOW)技術形成的絕緣層。當然，在其他實施例中，DRAM晶粒D1和D2也可以採用階梯形式堆疊。
熟習該項技藝者應能理解，第二晶片30可以是包含多個(例如，4個或4個以上)DRAM晶粒的記憶體封裝。根據本發明一實施例，第一晶片20和第二晶片30係以並排方式安裝在載體基板10的上表面10a上。根據本發明一實施例，第一晶片20和第二晶片30彼此的距離d可以介於約0.5mm至4.0mm之間。在其他實施例中，第一晶片20和第二晶片30彼此的距離d可以超過4.0mm。
根據本發明一實施例，在載體基板10的第一表面10a上，可以另設置複數個被動元件140，例如電容(capacitor)、電感(inductor)或電阻(resistor)等。根據本發明一實施例，例如，被動元件140可以是01005尺寸(0.4mm×0.2mm)的去耦電容(decoupling capacitor)，但不限於此。此外，第一晶片20和第二晶片30可以被模封塑料(encapsulant)60包覆而與外界隔離。
根據本發明一實施例，例如，第一晶片20包含四個側邊E1~E4，第一晶片20在側邊E1上設置有複數個高速訊號接墊(high-speed signal pad)201和 202。例如，高速訊號接墊201和202可以是數據(DQ)接墊，用來傳輸第一晶片20和第二晶片30之間的高速數據訊號，例如，2133MT/s、2400MT/s或2666MT/s的資料傳輸速率，但不限於此。
根據本發明一實施例，例如，第二晶片30包含四個側邊E5~E8。根據本發明一實施例，在DRAM晶粒D1和D2上，可以分別設置有重佈線層RDL1和RDL2將原本位於DRAM晶粒D1和D2主動面上的接墊位置P0分別扇出至重佈線層RDL1和RDL2上靠近側邊E5，形成接墊301和302。根據本發明一實施例，重佈線層RDL1和RDL2上靠近側邊E5形成的接墊301和302主要是對應於高速訊號接墊201和202的數據(DQ)接墊。重佈線層RDL1和RDL2的結構及材料均屬該領域周知技藝，因此其細節不另贅述。
根據本發明一實施例，例如，重佈線層RDL1和RDL2將原本位於DRAM晶粒D1和D2主動面上的接墊位置P1分別扇出至重佈線層RDL1和RDL2上靠近側邊E6，形成的接墊303和304。根據本發明一實施例，側邊E6和側邊E5是相對的兩邊。根據本發明一實施例，例如，重佈線層RDL1和RDL2上靠近側邊E5形成的接墊303和304可以是用於傳輸指令/位址(Command/Address，CA)訊號的接墊(以下又稱CA接墊)。此外，在重佈線層RDL1和RDL2上靠近側邊E7和E8處，可以分別形成有電源或接地(Power/Ground，P/G)接墊305和306。
根據本發明一實施例，在沿著第一晶片20的側邊E2、E3、E4上的載體基板10的第一表面10a上分別設置有金手指102、103、104，而在沿著第二晶片30的側邊E6、E7、E8上的載體基板10的第一表面10a上分別設置有金手指106、107、108。第一晶片20上沿著側邊E2、E3、E4設置的輸入/輸出(input/output，I/O)接墊222、223、224係分別透過打線WB2、WB3和WB4電連接至金手指102、103、104。根據本發明一實施例，打線WB2、WB3和WB4可以是金線或銅線，但不限於此。
根據本發明一實施例，第一晶片20在側邊E1上設置的複數個高速訊號接墊201和202係分別透過打線W1和W2電連接至第二晶片30的重佈線層RDL1和RDL2上靠近側邊E5所設置的DQ接墊301和302。根據本發明一實施例，例如，打線W1和W2的線弧高(loop height)h1和h2分別約為0.07mm和0.13mm左右，但不限於此。第二晶片20上沿著側邊E6設置的CA接墊303和304係分別透過打線W3和W4電連接至相對應的金手指106。第二晶片20上沿著側邊E7和E8設置的P/G接墊305和306係分別透過打線WB7和WB8電連接至相對應的金手指107和108。
由於第一晶片20的高速訊號接墊201和202與第二晶片30的重佈線層RDL1和RDL2上的DQ接墊301和302係以打線W1和W2直接連接，而不再需要經過載體基板10上的金手指和繞線，因此可以改善過去因為高速訊號連結須經過打線、基板上金手指和封裝基板內的繞線所構成的電連接路徑，所導致的訊號失真問題。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1:半導體封裝
10:載體基板
10a:第一表面
10b:第二表面
20:第一晶片
30:第二晶片
60:模封塑料
102、106:金手指
110:錫球焊墊
122:導通孔
140:被動元件
150:焊球
201、202:高速訊號接墊
222:輸入/輸出(I/O)接墊
301~304:接墊
210、310:黏著層
320:絕緣膜
d:距離
D1、D2:DRAM晶粒
E1、E2、E5、E6:側邊
h1、h2:線弧高
P0、P1:接墊位置
RDL1、RDL2:重佈線層
W1~W4:打線
WB2:打線

Claims (9)

  1. 一種半導體封裝，包含：一載體基板，包含相對的一第一表面和一第二表面；一第一晶片和一第二晶片，以並排方式安裝在該載體基板的該第一表面上，其中該第一晶片在鄰近該第二晶片的一第一側邊上設置有複數個高速訊號接墊，該第二晶片在鄰近該第一晶片的一第二側邊上設置有複數個數據(DQ)接墊，其中該第一晶片和該第二晶片係以黏著層固定在該載體基板的該第一表面上；以及複數條第一打線，直接電連接該複數個高速訊號接墊至該複數個數據(DQ)接墊。
  2. 如請求項1所述的半導體封裝，其中該載體基板的該第二表面上設置有複數個焊球，其中該複數個焊球為球型格柵陣列錫球。
  3. 如請求項1所述的半導體封裝，其中該第一晶片包含系統單晶片，該第二晶片包含晶粒堆疊或記憶體封裝。
  4. 如請求項1所述的半導體封裝，其中在該載體基板的該第一表面上，另設置有複數個被動元件。
  5. 如請求項1所述的半導體封裝，其中該複數個數據(DQ)接墊係形成在一重佈線層上。
  6. 如請求項1所述的半導體封裝，其中該第二晶片在遠離該第一晶片的一第三側邊上設置有複數個指令/位址(CA)接墊，其中該半導體封裝另包含複數條第二打線，直接電連接該複數個指令/位址(CA)接墊至該載體基板的該第一表面上相應的金手指。
  7. 如請求項1所述的半導體封裝，其中另包含一模封塑料，包覆該第一晶片和該第二晶片。
  8. 如請求項1所述的半導體封裝，其中該第二晶片在該第二側邊和第三側邊之間的第四側邊上設置有複數個電源或接地(P/G)接墊。
  9. 如請求項8所述的半導體封裝，其中另包含複數條第三打線，直接電連接該複數個電源或接地(P/G)接墊至該載體基板的該第一表面上相應的金手指。
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Publication number Priority date Publication date Assignee Title
TW200631148A (en) * 2005-02-21 2006-09-01 Touch Micro System Tech Chip type micro connector and method of packaging the sane
TW201810600A (zh) * 2016-06-15 2018-03-16 聯發科技股份有限公司 半導體封裝
US20190259695A1 (en) * 2018-02-22 2019-08-22 Xilinx, Inc. High density routing for heterogeneous package integration

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TWI481001B (zh) * 2011-09-09 2015-04-11 Dawning Leading Technology Inc 晶片封裝結構及其製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200631148A (en) * 2005-02-21 2006-09-01 Touch Micro System Tech Chip type micro connector and method of packaging the sane
TW201810600A (zh) * 2016-06-15 2018-03-16 聯發科技股份有限公司 半導體封裝
US20190259695A1 (en) * 2018-02-22 2019-08-22 Xilinx, Inc. High density routing for heterogeneous package integration

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