TW201810600A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW201810600A
TW201810600A TW106119915A TW106119915A TW201810600A TW 201810600 A TW201810600 A TW 201810600A TW 106119915 A TW106119915 A TW 106119915A TW 106119915 A TW106119915 A TW 106119915A TW 201810600 A TW201810600 A TW 201810600A
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Taiwan
Prior art keywords
semiconductor die
bonding
semiconductor
pad
interposer
Prior art date
Application number
TW106119915A
Other languages
English (en)
Inventor
周哲雅
洪坤廷
楊家豪
陳南誠
Original Assignee
聯發科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/182,613 external-priority patent/US10074628B2/en
Priority claimed from US15/588,690 external-priority patent/US10103128B2/en
Application filed by 聯發科技股份有限公司 filed Critical 聯發科技股份有限公司
Publication of TW201810600A publication Critical patent/TW201810600A/zh

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

本發明提供了一種半導體封裝，包含：一載體基板，具有相對的一第一表面以及一第二表面；以及一晶片堆疊，設置於該載體基板的該第一表面上，其中該晶片堆疊包含：一第一半導體晶粒，一第二半導體晶粒，以及一位於該第一和第二半導體晶粒之間的中介層，其中該中介層傳送該第一和第二半導體晶粒之間的信號。

Description

半導體封裝
本發明涉及封裝技術，特別係涉及一種半導體封裝。
如本領域所習知者，目前已有各式各樣的晶片封裝技術，例如，球柵陣列（ball grid array，BGA）、線接合（wire-bonding）、覆晶（flip chip）等等，用於經由晶粒和基板兩者上的接合點來將晶粒安裝到基板上。為了確保電子產品或通信裝置的小型化和多功能性，要求半導體封裝尺寸小、多管腳（pin）連接、高速和高功能性。
由於線接合系統級封裝（Wire-bonding System-in-Package，WBSiP）技術能夠增大半導體封裝的容量，因此WBSiP技術受到了廣泛應用。WBSiP涉及將複數個晶片堆疊在一起，且通過線接合的方式彼此連接。然而，傳統的WBSiP會遇到一些問題，舉例來說，封裝厚度、支撐微間距焊墊的能力以及低電阻值/電感值的效果。
輸入輸出（Input-Output，I/O）管腳數的增加以及對於高性能積體電路的需求增加促進了覆晶封裝技術的開發。覆晶技術係利用在晶片接合墊（bonding pad）上的凸塊（bump）來直接互連至封裝媒介，該晶片通過最短路徑面朝下地接合至封裝媒介。覆晶技術不僅可應用於單晶片封裝，同時也可應用至更高水準或集成度更高的封裝，以及可應用至能容納複數個晶片的複雜基板，以形成更大的功能單元。覆晶技術採用面矩陣式（area array）的設計，實現了與裝置的最高互連密度以及與封裝的電感互連非常低是其優點所在。
但是，習知的覆晶技術面臨著基板上的凸塊節距限制的挑戰。除此之外，因為昂貴的晶片載體基板一般包含1+2+1或者更多的層疊，因此高性能FCBGA（覆晶球柵陣列）係昂貴的。由於基板的凸塊節距的發展和微縮（shrinkage）明顯慢於晶粒微縮（die shrinking）以及管腳數量的增加，因此基板的凸塊節距係覆晶發展路線的瓶頸所在。甚至在未來，晶粒微縮將超過基板載體上的凸塊節距分辯率的微縮。
為了攻克此技術差距的問題，矽中介層（silicon interposer）與TSV（Through Silicon Via，矽穿孔）技術，以及微小間距凸塊技術係優選的解決方案。但是，上述提及的基於TSV的技術係昂貴的並且涉及複雜的製造製程。
因此，本發明之主要目的即在於提供一種半導體封裝，其結合了一中介層。
根據本發明至少一個實施例的一種半導體封裝，包含：一載體基板，具有相對的一第一表面以及一第二表面；以及一晶片堆疊，設置於該載體基板的該第一表面上，其中該晶片堆疊包含：一第一半導體晶粒，一第二半導體晶粒，以及一位於該第一和第二半導體晶粒之間的中介層，其中該中介層傳送該第一和第二半導體晶粒之間的信號。
本發明實施例之半導體封裝，其在第一和第二半導體晶粒之間設置一中介層來傳送該第一和第二半導體晶粒之間的信號，從而在半導體封裝中結合了一中介層。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解，電子裝置製造商可能會用不同的名詞來稱呼同一個元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接到一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
應當理解，儘管這裡可以使用術語“第一”、“第二”等描述各元件、區域、層和/或部分，但是這些元件、區域、層和/或部分不應受限於這些術語。這些術語僅用於將一個元件、區域、層或部分與另一元件、區域、層或部分區別開。因此，以下討論的第一元件、區域、層或部分可以被稱為第二元件、區域、層或部分而不背離示例性實施例的教導。
為便於描述此處可以使用諸如“在...之下”、“在...下面”、“下（lower)”、 “在...之上”、“上（upper)”等空間相對性術語以描述如附圖所示的一個元件或特徵與另一個（些）元件或特徵之間的關係。應當理解，空間相對性術語是用來概括除附圖所示取向之外的器件在使用或操作中的不同取向的。例如，如果把附圖中的器件翻轉過來，被描述為 “在”其他元件或特徵“之下”或“下面”的元件將會在其它元件或特徵的“上方”。因此，示例性術語“在...下面”就能夠涵蓋之上和之下兩種取向。器件可以採取其他取向（如旋轉 90度），此處所用的空間相對性描述符則做相應解釋。
此中使用的術語“水平面(horizontal)”定義為平行於半導體晶片或晶片基板的主平面或主表面的平面，而不論其方向。術語“垂直”是指垂直於剛才定義的“水平面”的方向。當使用諸如“在……上”、“在……下”、“底部”、“頂部”、“側面(如“側壁(sidewall) ”、“更高的”、“更低的”等術語時，均是指相對於水平面的定義。
術語“系統級封裝（SiP）”意味著複數個具有各種功能的IC晶片或晶粒係封閉在單個模組（封裝）內。SOC（System On a Chip，單晶片系統）係指將電腦或其他電子系統的各種元件整合進單個晶片中的積體電路。
本發明一實施例涉及一種半導體封裝，尤其涉及一種納入了RDL（Redistribution Layer，重分佈層或重分佈）中介層的多晶片（或多晶粒）封裝。
本發明一實施例涉及一種基於非TSV（Through Silicon Via，矽穿孔）的，合併了一RDL中介層（interposer）的三維線接合SIP。諸如SOC和DRAM KGD（Dynamic Random Access Memory known-good-die，已知合格的動態隨機存取記憶體晶粒）等半導體晶粒垂直地堆疊。SOC和DRAM KGD可以通過經由RDL中介層及/或封裝基板的線接合而彼此互連。本發明適用於各類應用，諸如行動電話或IOT（Internet of Things，物聯網）。
請參考第1圖，其為根據本發明一實施例的一半導體封裝1的橫截面示意圖。
如第1圖所示，該半導體封裝1包含：一載體基板10，具有相對的一第一表面10a和一第二表面10b。一晶片堆疊100設置於載體基板10的第一表面10a上。複數個焊球50（如BGA球）設置在載體基板10的第二表面10b上。對焊球50進行回焊以將半導體封裝1附著至PCB（Printed Circuit Board，印刷電路板）或母板（未示出）。
舉例而言，載體基板10可以為有機封裝基板，包含金屬導線和樹脂，諸如BT（bismalemide triazene）環氧樹脂或類似物。可以理解的是，可以使用其他材料來形成載體基板10，例如，陶瓷或塑料。為了簡單起見，沒有示出載體基板10的內部佈線（routing），其中該內部佈線將半導體晶粒的信號電性耦接至第二表面10b上的焊球50。
晶片堆疊100包含：一半導體晶粒11，係直接安裝於載體基板10的第一表面10a上。半導體晶粒11通過使用黏合劑來安裝於第一表面10a上，但是本發明並不限制於此。例如，根據本實施例，該半導體晶粒11可以為DRAM KGD，諸如LPDDR3（Low Power Double Data Rate 3，第三代低功耗雙倍資料率）或LPDDR4（第四代低功耗雙倍資料率），但是不限制於此。在一些實施例中，半導體晶粒可以為ASIC（Application-Specific Integrated Circuit，特定應用積體電路）。
根據本實施例，晶片堆疊100進一步包含：一中介層20，諸如RDL中介層。中介層20可以直接安裝在半導體晶粒11的頂面11a上。中介層20與半導體晶粒11的頂面11a部分重疊。例如，中介層20可以設置在半導體晶粒11的頂面11a的中央區域上，從而露出半導體晶粒11的外圍線接合墊區域。
中介層20通過使用黏合劑來安裝於頂面11a上，但是不限於此。例如，中介層20可以包含：一矽中介層或者一樹脂基板中介層。根據本實施例，中介層20不包含任何的矽通孔或者穿過基板的通孔（through substrate via）。
根據本實施例，晶片堆疊100進一步包含：一半導體晶粒12。例如，半導體晶粒12可以包含：一SOC或一ASIC，但是不限制於此。根據一實施例，半導體晶粒12係為一SOC並且半導體晶粒11係為一DRAM KGD。根據本實施例，半導體晶粒12和半導體晶粒11均為線接合晶片。另外，根據其他實施例，半導體晶粒12可以為安裝於中介層20上的覆晶半導體晶粒。
半導體晶粒12可以直接安裝於中介層20的頂面20a上。半導體晶粒12與中介層20的頂面20a部分重疊。例如，半導體晶粒12可以設置在中介層20的頂面20a的中央區域上，從而露出中介層20的外圍線接合墊區域。
通過使用黏合劑，可以將半導體晶粒12的無活性（inactive）的底面黏附至中介層20的頂面20a，但是不限制於此。半導體晶粒12的主動面（active surface）朝向上。在半導體晶粒12的主動面上，佈置了複數個I/O墊121和122。
根據本實施例，I/O墊121沿半導體晶粒12的第一邊緣設置，並且I/O墊122沿半導體晶粒12的第二邊緣設置，其中第一邊緣與第二邊緣相對。
根據本發明實施例，半導體封裝1可以進一步包含：一模塑料（molding compound）30，包封晶片堆疊100和載體基板10的頂面10a中未被該晶片堆疊100佔據的部分。模塑料30可以經受固化製程。模塑料30可以包含：環氧樹脂和二氧化矽填料（silica filler）的混合物，但不限制於此。
根據本實施例，在半導體晶粒11的頂面11a上，複數個接合墊111和112係佈置在其外圍線接合墊區域中。例如，在半導體晶粒11為DRAM KGD的情形中，接合墊111可以包含：CA（Command/Address，命令/地址）信號墊，以及接合墊112可能包含：DQ（數據）接墊。根據本實施例，接合墊111可以沿半導體晶粒11的第一邊緣設置，而接合墊112可以沿半導體晶粒11的第二邊緣設置，其中第一邊緣與第二邊緣相對。
根據本實施例，在中介層20的頂面20a上，複數個接合墊201，202和203係佈置在其外圍線接合墊區域中。根據本實施例，接合墊201設置為接近半導體晶粒11的頂面11a上的接合墊111。接合墊202和203設置為接近半導體晶粒11的頂面11a上的接合墊112。
根據本實施例，接合墊201中的至少一個係通過接合線311電性耦接至接合墊111中的至少一個，例如CA信號墊。通過內部走線204，接合墊201可以變更路線和重新佈置，從而電性耦接至接近接合墊（DQ墊）202的接合墊203。
用於傳送DQ和CA信號並且設置在半導體晶粒12的主動面上的I/O墊122分別通過接合線412和413分別電性耦接至接合墊202和203。用於傳送例如電源或接地信號的I/O墊121通過接合線411電性耦接至載體基板10的第一表面10a上的接合手指101。
由於中介層20可以在半導體晶粒11和半導體晶粒12之間提供RF（Radio Frequency，射頻）屏蔽（如結實的（solid）接地平面205），因此使用本發明係有優勢的。本發明實施例改善了半導體封裝1的RF性能。當相比於傳統的具有RDL的DDR時，本發明實施例更具有成本效應。
另外，通過在半導體晶粒11和半導體晶粒12之間結合中介層20，因此可以通過中介層20的內部走線204和通過在I/O墊122和重佈置的接合墊203之間延伸的接合線413來傳送第一半導體晶粒（如DRAM KGD）11的CA信號。可以通過接合線312，接合墊（DQ墊）202和接合線412來傳送第一半導體晶粒（如DRAM KGD）11的DQ信號。本發明實施例降低了接合線的長度。
另外，通過在半導體晶粒11和半導體晶粒12之間結合中介層20，可以減輕由於晶片堆疊100中的晶片的不同尺寸所招致的懸垂（overhang）問題。懸垂問題將在以下的第10圖中做更加詳細地描述。
請參考第2圖，其為根據本發明另一實施例的半導體封裝的橫截面示意圖，其中類似的符號表示類似的層、元件或區域。
如第2圖所示，第1圖的半導體封裝1與第2圖的半導體封裝2之間的不同在於：半導體封裝2中的晶片堆疊100a進一步包含：一位於半導體晶粒（如DRAM KGD）11和載體基板10之間的半導體晶粒21，諸如DRAM KGD。
根據本實施例，半導體晶粒11可以以階梯式（stepwise）的組態堆疊於半導體晶粒21上，但是不限制於此。根據本實施例，可以通過使用具有在半導體晶粒11和21之間提供的絕緣膜60的膜包線（Film Over Wire，FOW）技術來將半導體晶粒11堆疊於半導體晶粒21上。絕緣膜60避免半導體晶粒11接觸在半導體晶粒21和載體基板10之間延伸的接合線323，以及避免對接合線323的損傷。
根據本實施例，在半導體晶粒21的頂面21a上，複數個接合墊211和212佈置在其外圍線接合墊區域內。例如，接合墊211可以包含：CA（命令/地址）信號墊，以及接合墊212可以包含：DQ(數據)墊。類似地，接合墊211沿半導體晶粒21的第一邊緣設置，接合墊212沿半導體晶粒21的第二邊緣設置，其中第一邊緣與第二邊緣相對。
根據本實施例，在中介層20的頂面20a上，複數個接合墊201a，201b,202和203佈置在其外圍線接合墊區域內。根據本實施例，接合墊201a和201b設置為接近半導體晶粒11的頂面11a上的接合墊111以及半導體晶粒21的頂面21a上的接合墊211。接合墊202和203設置為接近半導體晶粒11的頂面11a上的接合墊112。
根據本實施例，接合墊201a中的至少一個係通過接合線311電性耦接至接合墊111中的至少一個，例如，CA信號墊(CA-1)。接合墊201b中的至少一個係通過接合線321電性耦接至接合墊211中的至少一個，如CA信號墊（CA-2）。通過內部走線204，可以對接合墊201a和201b重新佈線和重新佈置，從而電性耦接至接近接合墊（DQ-1+2）202的接合墊203。
用來傳送DQ和CA信號並且在半導體晶粒12的主動面上的I/O墊122分別通過接合線412和413電性耦接至接合墊202和203。用於傳送例如電源或接地信號的I/O墊121通過接合線411電性耦接至載體基板10的第一表面10a上的接合手指101。
本發明的一個特點是：通過中介層20來對兩個DRAM KGD的CA信號墊（CA-1和CA-2）重新佈線和重新佈置，以及在中介層20的接近SOC的對應I/O墊的一側上將該兩個DRAM KGD的CA信號墊（CA-1和CA-2）聚合在一起。根據本實施例，發源於半導體晶粒12的I/O墊122的CA信號進入接合墊203，並進入中介層20的走線204，並且接著從中介層20的接合墊201a和201b穿出。此後，CA信號分別進入半導體晶粒11的接合墊111和半導體晶粒21的接合墊211。
根據本實施例，每一個接合墊212（DQ-2）通過接合線323電性耦接至載體基板10的第一表面10a上的接合手指102。絕緣膜60可以覆蓋接合墊212以及部分地覆蓋接合線323。如第2圖所示，線弧（wire loop）的上部分嵌入於絕緣膜60中。
半導體晶粒11中的每個接合墊112（DQ-1）通過接合線313電性耦接至載體基板10中的第一表面10a上的接合手指103。中介層20上的用來傳送DQ信號的每一個接合墊202（DQ-1+2）通過接合線314電性耦接至載體基板10的第一表面10a上的接合手指104。根據本實施例，DQ信號通過載體基板10和中介層20在SOC（半導體晶粒12）和DRAM KGD（半導體晶粒11和21）之間傳送。
請參考第3圖，其為根據本發明另一實施例的一半導體封裝3的橫截面示意圖，其中類似的符號表示類似的層、元件或區域。根據該另一實施例，通過中介層20和載體基板10，CA信號在SOC和DRAM KGD之間傳送。
如第3圖所示，類似地，該半導體封裝3包含：一載體基板10，具有相對的一第一表面10a和一第二表面10b。一晶片堆疊100設置在載體基板10的第一表面10a上。晶片堆疊100包含：一半導體晶粒11，係直接安裝於載體基板10的第一表面10a上；一中介層20，直接安裝於半導體晶粒11的頂面11a上；以及一半導體晶粒12，直接安裝於中介層20的頂面20a上。
接合墊111，例如半導體晶粒11的CA信號墊，係通過接合線331電性耦接至接合手指103，以及中介層20的接合墊（CA墊）201通過接合線333電性耦接至接合手指102。接合手指103通過載體基板10中的內部走線電性耦接至接合手指102。
接合墊112，例如半導體晶粒11的DQ信號墊，係通過接合線332電性耦接至接合手指104，以及中介層20的接合墊（DQ墊）202係通過接合線314電性耦接至接合手指105。接合手指105可以通過載體基板10的內部走線電性耦接至接合手指104。
請參考第4圖，其為根據本發明又另一實施例的半導體封裝的橫截面示意圖，其中類似的符號表示類似的層、元件或區域。根據另一實施例，與第1圖所示的實施例的晶片堆疊相比，本實施例的晶片堆疊具有相反的組態。
如第4圖所示，該半導體封裝4包含：一載體基板10，具有相對的一第一表面10a和一第二表面10b。一晶片堆疊100b設置在載體基板10的該第一表面10a上。晶片堆疊100b包含：一半導體晶粒12，係直接安裝於載體基板10的第一表面10a上；一中介層20，安裝於半導體晶粒12上；以及一半導體晶粒11，安裝於中介層20上。
根據本實施例，一絕緣膜61可以設置在半導體晶粒12和中介層20之間，並且一絕緣膜62可以設置在中介層20和半導體晶粒11之間。絕緣膜61和絕緣膜62可以通過使用FOW技術來形成。
根據本實施例，諸如SOC等半導體晶粒12放置在晶片堆疊100b的底部，以及諸如DRAM KGD等半導體晶粒11放置在晶片堆疊100b的頂部。半導體晶粒11和12均為線接合晶片。
根據本實施例，用於傳送DQ和CA信號的並且設置在半導體晶粒12的主動面上的I/O墊122可以分別通過接合線412和413電性耦接至接合手指102和103。用於傳送例如接地或電源信號的I/O墊121可以通過接合線411電性耦接至載體基板10的第一表面10a上的接合手指101。
根據本實施例，在半導體晶粒11的頂面11a上，複數個接合墊111和112佈置在其外圍線接合墊區域內。例如，在半導體晶粒11為DRAM KGD的情形中，接合墊111可以包含：CA（命令/地址）信號墊，以及接合墊112可以包含：DQ（數據）墊。根據本實施例，接合墊111沿半導體晶粒11的第一邊緣設置，以及接合墊112沿半導體晶粒112的第二邊緣設置，其中第一邊緣與第二邊緣相對。
根據本實施例，在中介層20的頂面20a上，複數個接合墊201和203係設置在其外圍線接合墊區域內。根據本實施例，接合墊201設置為接近半導體晶粒11的頂面11a上的接合墊111。接合墊203設置為接近半導體晶粒11的頂面11a上的接合墊112。
根據本實施例，接合墊201中的至少一個係通過接合線311電性耦接至接合墊111中的至少一個，例如CA信號墊。接合墊201可以通過內部走線204而重新佈線和重新佈置，從而電性耦接至接合墊203（CA-RDL）。接合墊203係通過接合線315電性耦接至載體基板10的第一表面10a上的接合手指104。通過載體基板10的內部走線，接合手指104可以電性耦接至接合手指102，以在半導體晶粒12和11之間傳遞CA信號。
根據本實施例，接合墊112（例如DQ信號墊）中的至少一個係通過接合線313電性耦接至接合手指105。通過載體基板10的內部走線，接合手指105可以電性耦接至接合手指103，以在半導體晶粒12和11之間傳遞DQ信號。
請參考第5圖，其為根據本發明又另一實施例的半導體封裝的橫截面示意圖，其中類似的符號表示類似的層、元件或區域。
如第5圖所示，第4圖所示的半導體封裝4與第5圖的半導體封裝5之間的不同在於：半導體封裝5中的晶片堆疊100c進一步包含：一位於半導體晶粒11上方的半導體晶粒21，諸如DRAM KGD。根據本實施例，可以通過使用FOW技術來在半導體晶粒21和11之間提供絕緣膜63，從而使得半導體晶粒21通過該絕緣膜63堆疊在半導體晶粒11上。
根據本實施例，在半導體晶粒21的頂面21a上，複數個接合墊211和212係佈置在其外圍線接合墊區域內。例如，接合墊211可以包含：CA信號墊（CA-2）,以及接合墊212可以包含：DQ墊（DQ-2）。類似地，接合墊211沿半導體晶粒21的第一邊緣設置，以及接合墊212沿半導體晶粒21的第二邊緣設置，其中第一邊緣與第二邊緣相對。
根據本實施例，在中介層20的頂面20a上，複數個接合墊201a，201b和203係佈置在其外圍線接合墊區域內。根據本實施例，接合墊（CA-1+2）201a和201b係設置為接近半導體晶粒11的頂面11a上的接合墊111和半導體晶粒21的頂面21a上的接合墊211。接合墊（CA-RDL）203係設置為接近半導體晶粒11的頂面11a上的接合墊112。
根據本實施例，至少一個接合墊201a通過接合線311電性耦接至至少一個接合墊111，如CA信號墊（CA-1）。至少一個接合墊201b通過接合線321電性耦接至至少一個接合墊211，例如CA信號墊（CA-2）。接合墊201a和201b可以通過內部走線204進行重新佈線和重新佈置，從而電性耦接至接合墊203。根據本實施例，接合墊203係通過接合線315電性耦接至接合手指104。
根據本實施例，半導體晶粒11中的每個接合墊（DQ-1）112可以通過接合線313電性耦接至載體基板10的第一表面10a上的接合手指105。半導體晶粒21中的每個接合墊（DQ-2）212可以通過接合線323電性耦接至載體基板10的第一表面10a上的接合手指106。
用於傳送DQ和CA信號並且設置在半導體晶粒12的主動面上的I/O墊122可以分別通過接合線412和413電性耦接至接合手指103和102。用於傳送例如電源或接地信號的I/O墊121可以通過接合線411電性耦接至載體基板10的第一表面10a上的接合手指101。
請參考第6圖，其為根據本發明又另一實施例的半導體封裝6的橫截面示意圖，其中類似的符號表示類似的層、元件或區域。根據另一實施例，晶片堆疊具有與第1圖所示的實施例中的晶片堆疊相反的組態。
第6圖的半導體封裝6類似於第4圖的半導體封裝4，兩者之間的不同之外在於：第6圖的半導體封裝6中的半導體晶粒12為覆晶。
如第6圖所示，該半導體封裝6包含：一載體基板10，具有一相對的第一表面10a和一第二表面10b。一晶片堆疊100d設置在載體基板10的第一表面10a上。該晶片堆疊100d包含：一覆晶半導體晶粒12，係直接安裝於載體基板10的第一表面10a上；一中介層20，安裝於半導體晶粒12上；以及一半導體晶粒11，安裝於中介層20上。一絕緣膜62設置在中介層20和半導體晶粒11之間。絕緣膜62可以通過使用FOW技術來形成。
根據本發明實施例，諸如SOC等半導體晶粒12可以放置在晶片堆疊100d的底部，以及諸如DRAM KGD等半導體晶粒11可以設置在晶片堆疊100d的頂部。半導體晶粒12可以具有凸起的（bumped）主動面，該主動面通過使用習知的覆晶技術而直接面向並連接載體基板10的第一表面10a。
根據本發明實施例，中介層20可以直接設置在半導體晶粒12的無活性表面上。因此，可以節約第4圖所示的中介層20a和半導體晶粒12之間的絕緣膜。
根據本實施例，分別用來傳送DQ和CA信號並且在半導體晶粒12的主動面上的I/O墊122和123沒有使用接合線而電性耦接至載體基板10的內部走線。因此，可以縮短信號路徑的長度。
根據本實施例，類似地，在半導體晶粒11的頂面11a上，複數個接合墊111和112佈置在其外圍線接合墊區域內。例如，在半導體晶粒11為DRAM KGD的情形中，接合墊111可以包含：CA信號墊，以及接合墊112可以包含：DQ墊。根據本實施例，接合墊111沿半導體晶粒11的第一邊緣設置，接合墊112沿半導體晶粒11的第二邊緣設置，其中第一邊緣與第二邊緣相對。
根據本實施例，在中介層20的頂面20a上，複數個接合墊201和203佈置在其外圍線接合墊區域內。根據本實施例，接合墊201設置為接近半導體晶粒11的頂面11a上的接合墊111。接合墊203設置為接近半導體晶粒11的頂面11a上的接合墊112。
根據本實施例，至少一個接合墊201通過接合線311電性耦接至至少一個接合墊111，例如CA信號墊。接合墊201可以通過內部走線204被重新佈線和重新佈置，以電性耦接至中介層20的相對邊緣上的接合墊203（CA-RDL）。
接合墊203係通過接合線315電性耦接至載體基板10的第一表面10a上的接合手指104。通過載體基板10的內部走線，接合手指104可以電性耦接至I/O墊123，以在半導體晶粒12和11之間傳送CA信號。
根據本實施例，至少一個接合墊112，如DQ信號墊，係通過接合線313電性耦接至接合手指105。通過載體基板10的內部走線，接合手指105可以電性耦接至I/O墊122，以在半導體晶粒12和11之間傳遞DQ信號。
請參考第7圖，其為根據本發明又另一實施例的半導體封裝的橫截面示意圖。其中類似的符號表示類似的層、元件或區域。根據另一實施例，CA信號可以通過中介層20和載體基板10在SOC和DRAM KGD之間傳送。
如第7圖所示，類似地，該半導體封裝7包含：與第6圖相同的晶片堆疊100d。晶片堆疊100d包含：一覆晶半導體晶粒12，直接安裝在載體基板10的第一表面10a上；一中介層20，直接安裝在半導體晶粒12上；以及一半導體晶粒11，設置在中介層20上。儘管在該圖中僅示出了一顆DRAM KGD（半導體晶粒11），但是可以理解的是，複數個DRMA KGD可以設置於中介層20上，如第11圖所示。在第11圖中，兩顆DRAM KGD堆疊在中介層20上，即半導體晶粒11和21。
接合墊111，例如半導體晶粒11的CA信號墊，係通過接合線331電性耦接至接合手指101，以及中介層20的接合墊201係通過接合線333電性耦接至接合手指102。接合手指101通過載體基板10的內部走線電性耦接至接合手指102。
接合墊112，例如半導體晶粒11的DQ信號墊，係通過接合線313電性耦接至接合手指105，以及中介層20的接合墊（CA-RDL）203 通過接合線315電性耦接至接合手指104。經由載體基板10的內部走線，接合手指105和104可以分別電性耦接至I/O墊122和123，以在半導體晶粒12和11之間傳送DQ信號和CA信號。
請參考第8圖，其為根據本發明又另一實施例的半導體封裝的橫截面示意圖，其中類似的符號表示類似的層、元件或區域。
第8圖的半導體封裝8類似於第6圖的半導體封裝6，兩者之間的不同在於：該半導體封裝8包含：一剛性的支撐基板，諸如直接在中介層20下方的虛設（dummy）矽晶粒。
如第8圖所示，該半導體封裝8包含：一載體基板10，具有相對設置的一第一表面10a和一第二表面10b。一晶片堆疊100e設置在載體基板10的第一表面10a上。晶片堆疊100e包含：一覆晶半導體晶粒12，係直接安裝在載體基板10的第一表面10a上；一中介層20，安裝於半導體晶粒12上；一剛性支撐基板80，位於中介層20和半導體晶粒12之間，例如為虛設矽晶粒；以及一半導體晶粒11，安裝於中介層20上。根據本實施例，沒有絕緣膜設置在中介層20和半導體晶粒11之間。此中使用的術語“虛設（dummy）”意味著剛性支撐基板80不在中介層20和半導體晶粒12之間提供任何直接的電連接。
剛性支撐基板80附著至中介層20的底面，並且可以充當加強板（stiffener）的功能以及可以對中介層20提供機械支撐，剛性支撐基板80可以促進線接合製程並且改善產品良品率。剛性支撐基板80也可以改善封裝的翹曲問題。
根據本實施例，諸如SOC等半導體晶粒12放置在晶片堆疊100e的底部，並且諸如DRAM KGD等半導體晶粒11放置在晶片堆疊100e的頂部。半導體晶粒12可以具有凸出的主動面，該主動面直接面向載體基板10的第一表面10a，並通過使用習知的覆晶技術連接至第一表面10a。根據本實施例，剛性支撐基板80直接設置在半導體晶粒12的無活性表面上。
根據本實施例，分別用於傳送DQ和CA信號並且設置在半導體晶粒12的主動面上的I/O墊122和123沒有使用接合線而電性耦接至載體基板10的內部走線。在半導體晶粒11的頂面11a上，複數個接合墊111和112係佈置在其外圍線接合墊區域內。例如，在半導體晶粒11為DRAM KGD的情形中，接合墊111可以包含：CA信號墊，以及接合墊112可以包含：DQ墊。根據本實施例，接合墊111沿半導體晶粒11的第一邊緣設置，以及接合墊112沿半導體晶粒11的第二邊緣設置，其中第一邊緣相對於第二邊緣。
根據本實施例，在中介層20的頂面20a上，複數個接合墊201和203佈置在其外圍線接合墊區域內。根據本實施例，接合墊201設置為接近半導體晶粒11的頂面11a上的接合墊111。接合墊203設置為接近半導體晶粒11的頂面11a上的接合墊112。
根據本實施例，至少一個接合墊201通過接合線311電性耦接至至少一個接合墊111，例如CA信號墊。接合墊201通過內部走線204而被重新佈線以及重新佈置，從而電性耦接至中介層20的相對邊緣上的接合墊（CA-RDL）203。
接合墊203通過接合線315電性耦接至載體基板10的第一表面10a上的接合手指104。通過載體基板10的內部走線，接合手指104可以電性耦接至I/O墊123，以在半導體晶粒12和11之間傳送CA信號。
根據本實施例，至少一個接合墊112，例如DQ信號墊，係通過接合線313電性耦接至接合手指105。通過載體基板10的內部走線，接合手指105可以電性耦接至I/O墊122，以在半導體晶粒12和11之間傳送DQ信號。
請參考第9圖，其為根據本發明又另一實施例的半導體封裝的橫截面示意圖，其中類似的符號表示相似的層、元件或區域。
第9圖的半導體封裝9類似於第7圖的半導體封裝7，兩者之間的不同在於：半導體封裝9中示例的SOC為線接合晶片。
如第9圖所示，類似地，該半導體封裝9包含：一載體基板10和一位於載體基板10上的晶片堆疊100f。該晶片堆疊100f包含：一半導體晶粒12，直接安裝於載體基板10的第一表面10a上；一中介層20，設置在半導體晶粒12上，以及一半導體晶粒11，設置於中介層20上。
根據本實施例，絕緣膜61設置在半導體晶粒12和中介層20之間，以及絕緣膜62設置在中介層20和半導體晶粒11之間。絕緣膜61和62可以通過使用FOW技術來形成。
接合墊111，例如半導體晶粒11的CA信號墊，係通過接合線331電性耦接至接合手指106，以及中介層20的接合墊201係通過接合線333電性耦接至接合手指107。接合手指106係通過載體基板10中的內部走線電性耦接至接合手指107。
接合墊112，例如半導體晶粒11的DQ信號墊，係通過接合線313電性耦接至接合手指105，以及中介層20的接合墊203係通過接合線315電性耦接至接合手指104。
根據本實施例，用於傳送DQ和CA信號並且設置在半導體晶粒12的主動面上的I/O墊122係分別通過接合線412和413電性耦接至接合手指102和103。用於傳送例如電源或接地信號的I/O墊121可以通過接合線411電性耦接至載體基板10的第一表面10a上的接合手指101。
請參考第10圖，其為根據本發明又另一實施例的半導體封裝的橫截面示意圖，其中相似的符號表示相似的層、元件或區域。
第10圖的半導體封裝7a類似於第7圖的半導體封裝7，兩者之間的不同包含：（1）第10圖的半導體封裝7a在中介層20上具有複數個DRAM KGD，以及（2）半導體封裝7a中示例的SOC的尺寸小於第10圖中的其上覆蓋（overlying）的DRAM KGD的尺寸。中介層20可以改善示例的DRAM KGD和示例的SoC之間的懸垂問題。
如第10圖所示，該半導體封裝7a包含：一晶片堆疊100g。晶片堆疊100g包含：一覆晶半導體晶粒12，係直接設置在載體基板10的第一表面10a上；一中介層20，直接安裝在半導體晶粒12上；一半導體晶粒11，設置在中介層20上；以及一半導體晶粒21，設置在半導體晶粒11上。其中半導體晶粒11和21均為DRAM KGD。
根據本實施例，絕緣膜61可以設置在半導體晶粒11和中介層20之間，以及絕緣膜62可以設置在半導體晶粒21和11之間。絕緣膜61和62可以通過使用FOW技術來形成。
根據本實施例，半導體晶粒11的尺寸和半導體晶粒21的尺寸大於半導體晶粒12的尺寸。因此，在半導體晶粒11和12之間形成懸垂。在半導體晶粒11和12之間結合中介層20可以減輕此懸垂問題以及降低線接合的難度。
接合墊（CA-1）111，例如半導體晶粒11的CA信號墊，係通過接合線331電性耦接至接合手指102。接合墊（CA-2）211，例如半導體晶粒21的CA信號墊，係通過接合線341電性耦接至接合手指101。中介層20的接合墊201係通過接合線333電性耦接至接合手指103。接合手指102和103可以通過載體基板10中的內部走線電性耦接至接合手指101。
接合墊（DQ-1）112，例如半導體晶粒11的DQ信號墊，係通過接合線332電性耦接至接合手指105。接合墊（DQ-2）212，例如半導體晶粒21的DQ信號墊，係通過接合線342電性耦接至接合手指106。中介層20的接合墊（CA-RDL）203係通過接合線314電性耦接至接合手指104。接合手指104~106可以通過載體基板10中的內部走線電性耦接至半導體晶粒12的I/O墊122和123。
請參考第11圖，其為根據本發明又另一實施例的半導體封裝的橫截面示意圖，其中相似的符號表示相似的層、元件或區域。
如第11圖所示，該半導體封裝包含：一載體基板10和一位於載體基板10上的晶片堆疊。該晶片堆疊包含：一覆晶半導體晶粒12，係直接設置在載體基板10的第一表面10a上；一中介層20，直接安裝在半導體晶粒12上；一半導體晶粒11，設置在中介層20上；以及一半導體晶粒21，設置在半導體晶粒11上。其中半導體晶粒11和21均為DRAM KGD。
根據本實施例，絕緣膜61可以設置在半導體晶粒11和中介層20之間，以及絕緣膜62可以設置在半導體晶粒21和11之間。絕緣膜61和62可以通過使用FOW技術來形成。
根據本實施例，半導體晶粒11的尺寸和半導體晶粒21的尺寸小於半導體晶粒12的尺寸。
接合墊（CA-1）111，例如半導體晶粒11的CA信號墊，係通過接合線331電性耦接至接合手指102。接合墊（CA-2）211，例如半導體晶粒21的CA信號墊，係通過接合線341電性耦接至接合手指101。中介層20的接合墊201係通過接合線333電性耦接至接合手指103。接合手指102和103可以通過載體基板10中的內部走線電性耦接至接合手指101。
接合墊（DQ-1）112，例如半導體晶粒11的DQ信號墊，係通過接合線313電性耦接至接合手指105。接合墊（DQ-2）212，例如半導體晶粒21的DQ信號墊，係通過接合線342電性耦接至接合手指106。中介層20的接合墊（CA-RDL）203係通過接合線315電性耦接至接合手指104。接合手指104~106可以通過載體基板10中的內部走線電性耦接至半導體晶粒12的I/O墊122和123。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1、2、3、4、5、6、7、8、9、7a‧‧‧半導體封裝
10‧‧‧載體基板
10a‧‧‧第一表面
10b‧‧‧第二表面
100、100a、100b、100c、100d、100e、100f、100g‧‧‧晶片堆疊
50‧‧‧焊球
11、12、21‧‧‧半導體晶粒
20‧‧‧中介層
11a、20a、21a‧‧‧頂面
121、122、123‧‧‧I/O墊
30‧‧‧模塑料
111、112、201、202、203、211、212、201a、201b‧‧‧接合墊
311、411、412、413、323、313、314、315、331、332、333、341、342‧‧‧接合線
204‧‧‧走線
101、102、103、104、105、106、107‧‧‧接合手指
60、61、62、63‧‧‧絕緣膜
80‧‧‧剛性支撐基板
包含所附的圖式以提供實施例的進一步理解，並且將圖式納入其中並構成說明書的一部分。圖式示出了某些實施例，並且連同描述一起來解釋其原理。在圖式中： 第1圖為根據本發明一實施例的半導體封裝的橫截面示意圖； 第2圖為根據本發明另一實施例的半導體封裝的橫截面示意圖； 第3圖為根據本發明另一實施例的半導體封裝的橫截面示意圖； 第4圖為根據本發明又另一實施例的半導體封裝的橫截面示意圖； 第5圖為根據本發明又另一實施例的半導體封裝的橫截面示意圖； 第6圖為根據本發明又另一實施例的半導體封裝的橫截面示意圖； 第7圖為根據本發明又另一實施例的半導體封裝的橫截面示意圖； 第8圖為根據本發明又另一實施例的半導體封裝的橫截面示意圖； 第9圖為根據本發明又另一實施例的半導體封裝的橫截面示意圖； 第10圖為根據本發明又另一實施例的半導體封裝的橫截面示意圖； 第11圖為第7圖所描繪的半導體封裝的變形，其中DRAM晶片堆疊在中介層上。
1‧‧‧半導體封裝
10‧‧‧載體基板
10a‧‧‧第一表面
10b‧‧‧第二表面
100‧‧‧晶片堆疊
50‧‧‧焊球
11、12‧‧‧半導體晶粒
20‧‧‧中介層
11a、20a‧‧‧頂面
121、122‧‧‧I/O墊
30‧‧‧模塑料
111、112、201、202、203‧‧‧接合墊
311、411、412、413‧‧‧接合線
204‧‧‧走線
101‧‧‧接合手指

Claims (15)

  1. 一種半導體封裝，包含： 一載體基板，具有相對的一第一表面以及一第二表面；以及 一晶片堆疊，設置於該載體基板的該第一表面上，其中該晶片堆疊包含：一第一半導體晶粒，一第二半導體晶粒，以及一位於該第一和第二半導體晶粒之間的中介層，其中該中介層傳送該第一和第二半導體晶粒之間的信號。
  2. 如申請專利範圍第1項所述的半導體封裝，其中該第一和第二半導體晶粒均為線接合晶片。
  3. 如申請專利範圍第1項所述的半導體封裝，其中， 該第一半導體晶粒包含：一已知合格的動態隨機存取記憶體或者一特定應用積體電路； 及/或，該第二半導體晶粒包含：一系統單晶片或者一特定應用積體電路； 及/或，該載體基板包含：一具有金屬走線和樹脂的有機封裝基板； 及/或，該中介層包含：一矽中介層或者一樹脂基板中介層； 及/或，一接地平面，用來在該第一半導體晶粒和該第二半導體晶粒之間提供射頻屏蔽。
  4. 如申請專利範圍第1項所述的半導體封裝，其中該中介層包含：一命令/地址接合墊，一重佈置接合墊，一數據接合墊，以及一內部走線，其中該內部走線將該命令/地址接合墊或者該數據接合墊電性耦接至該重佈置接合墊。
  5. 如申請專利範圍第4項所述的半導體封裝，其中該第一半導體晶粒包含：至少一個命令/地址信號墊，設置在該第一半導體晶粒的第一邊緣上，以及至少一個數據信號墊，設置在該第一半導體晶粒的第二邊緣上，其中該第一邊緣相對於該第二邊緣；其中，該命令/地址接合墊接近該命令/地址信號墊以及該第一邊緣，該重佈置接合墊和該數據接合墊接近該數據信號墊和該第二邊緣。
  6. 如申請專利範圍第5項所述的半導體封裝，其中該命令/地址信號墊通過一第一接合線電性耦接至該命令/地址接合墊； 或者，該數據信號墊通過一第二接合線電性耦接至該數據接合墊； 或者，該數據信號墊和該重佈置接合墊均電性耦接至該載體基板。
  7. 如申請專利範圍第6項所述的半導體封裝，其中該第二半導體晶粒包含：一第一和第二輸入/輸出墊，位於該第二半導體晶粒的主動面上，並且分別用於傳送命令/地址信號和數據信號。
  8. 如申請專利範圍第7項所述的半導體封裝，其中該第一和第二輸入/輸出墊分別通過一第三接合線和一第四接合線電性耦接至該命令/地址接合墊和該數據接合墊； 或者，該第一和第二輸入/輸出墊均電性耦接至該載體基板。
  9. 如申請專利範圍第1項所述的半導體封裝，其中該第二半導體晶粒直接安裝於該載體基板的該第一表面上，該中介層安裝於該第二半導體晶粒上，以及該第一半導體晶粒安裝於該中介層上。
  10. 如申請專利範圍第9項所述的半導體封裝，其中該第一半導體晶粒為已知合格的動態隨機存取記憶體，該第二半導體晶粒為系統單晶片。
  11. 如申請專利範圍第9項所述的半導體封裝，其中另包含：一第一絕緣膜，位於該中介層和該第二半導體晶粒之間，以及一第二絕緣膜，位於該中介層和該第一半導體晶粒之間。
  12. 如申請專利範圍第11項所述的半導體封裝，其中該晶片堆疊另包含：一第三半導體晶粒，相鄰於該第一半導體晶粒； 以及一第三絕緣膜，位於該第三半導體晶粒和該第一半導體晶粒之間。
  13. 如申請專利範圍第1項所述的半導體封裝，其中該第一半導體晶粒和該第二半導體晶粒中的一個為覆晶。
  14. 如申請專利範圍第13項所述的半導體封裝，其中該第二半導體晶粒為該覆晶，且該第二半導體晶粒直接安裝於該載體基板的該第一表面上，該中介層安裝於該第二半導體晶粒上，該第一半導體晶粒安裝於該中介層上。
  15. 如申請專利範圍第14項所述的半導體封裝，其中另包含：一剛性支撐基板，位於該第二半導體晶粒和該中介層之間。
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