TWI716191B - 半導體封裝及其製造半導體封裝的方法 - Google Patents

半導體封裝及其製造半導體封裝的方法 Download PDF

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TWI716191B
TWI716191B TW108141270A TW108141270A TWI716191B TW I716191 B TWI716191 B TW I716191B TW 108141270 A TW108141270 A TW 108141270A TW 108141270 A TW108141270 A TW 108141270A TW I716191 B TWI716191 B TW I716191B
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chip
connection board
semiconductor package
hole
connection
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TW108141270A
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TW202115847A (zh
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楊吳德
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南亞科技股份有限公司
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Abstract

本揭露提供一種半導體封裝，其包括封裝基板、第一晶片、第二晶片、互連構件和多個接合引線。第一晶片設置在封裝基板上。第二晶片設置在第一晶片上方。所述互連構件配置為耦合所述第一晶片和所述第二晶片，並且包括第一連接板、第二連接板和焊球。第一連接板連接到第一晶片。第二連接板連接到第二晶片。焊球將第一連接板和第二連接板耦接。接合引線將互連構件耦接到封裝基板、第一晶片和第二晶片。

Description

半導體封裝及其製造半導體封裝的方 法
本揭露上係關於半導體晶片封裝及其製造方法，更具體而言，本揭露係關於不具有傳統上用於連接兩個堆疊的晶片的再分佈層的半導體晶片封裝及其製造方法。
半導體裝置對於許多現代應用是必不可少的。隨著電子技術的進步，半導體裝置的尺寸越來越小，同時具有更大的功能和更多的積體電路。由於半導體裝置的小型化，晶片堆疊封裝技術現在被廣泛用於製造半導體裝置。在這種封裝技術的生產過程中需執行許多製造步驟。
然而，以小型化規模製造的半導體裝置變得越來越複雜。任何半導體裝置在製造複雜性的增加都可能引起缺陷，例如不良的電互連或製造成本的增加。因此，半導體裝置的結構和製造的改良上即存在許多挑戰。
本揭露的一個層面提供一種半導體封裝，其包括封裝基板、第一晶片、第二晶片、互連構件和多個接合引線。 第一晶片設置在封裝基板上。第二晶片設置在第一晶片上方。所述互連構件配置為耦合所述第一晶片和所述第二晶片，並且包括第一連接板、第二連接板和焊球。第一連接板連接到第一晶片。第二連接板連接到第二晶片。焊球將第一連接板和第二連接板耦接。接合引線將互連構件耦接到封裝基板、第一晶片和第二晶片。
在部分實施例中，該第一連接板具有一第一通孔暴露出該第一晶片的一接線墊，並且該等接合引線其中之一者通過該第一通孔，以耦接該第一晶片的該接線墊至該第一連接板。並且該第二連接板具有一第二通孔暴露出該第二晶片的一接線墊，並且該等接合引線中的另一者通過該第二通孔，以耦接該第二晶片的該接線墊至該第二連接板。該第一通孔在垂直該封裝基板的方向上對及該第二通孔，且該第一通孔暴露該第一晶片的複數個接線墊，且該第二通孔暴露該第二晶片的複數個接線墊。
在部分實施例中，該第一連接板及該第二連接板各自包括一支撐層及設置於該支撐層之上的一電極。該第一連接板及該第二連接板各自通過一膠合材料連接至該第一晶片與該第二晶片。並且，該第一連接板及該第二連接板的該等電極位於該焊球的兩側。該第一連接板的該電極通過該等接合引線中的其中二個連接到該封裝基板和該第一晶片，並且該第二連接板的該電極通過該等接合引線中的其中一個連接到該第二連接板的該電極。
在部分實施例中，半導體封裝更包括一封裝材料，並且該第一晶片、該第二晶片、該互連構件及該等接合引線包覆於該封裝材料內。
本揭露的另一個層面提供一種製造上述任一實施例所述的半導體封裝的方法。所述方法包括：提供一封裝基板；放置一第一晶片在該封裝基板之上；放置一第二晶片在該第一晶片上方並藉由一互連構件耦接該第一晶片及該第二晶片。具體而言，藉由一互連構件耦接該第一晶片及該第二晶片，其中該互連構件的一第一連接板連接至該第一晶片，該互連構件的一第二連接板連接至該第二晶片，且該互連構件的一焊球連接至該第一連接板及該第二連接板。所述方法還包括藉由複數個接合引線耦接該互連構件至該封裝基板、該第一晶片及該第二晶片。
應當理解，前面的一般描述和下面的詳細描述都是示例性的，並且旨在提供對本揭露所要求保護的申請專利範圍進一步解釋。
1:半導體封裝
1L:下方部分
1U:上方部分
10:第一晶片
11:作動表面
110:外邊緣
12:接線墊
20:第一連接板
21:支撐層
210:外邊緣
22:通孔
220:內邊緣
23:電極
231:連接部
232:焊球接點
233:導線接點
234:導線接點
24:作動區域
25:作動區域
31:接合引線
32:接合引線
33:接合引線
34:接合引線
40:封裝基板
45:焊球
50:第二晶片
50A:第二晶片
51:作動表面
510:外邊緣
510A:外邊緣
52:接線墊
52A:接合焊盤
60:第二連接板
60A:第二連接板
61:支撐層
61A:支撐層
610:外邊緣
610A:外邊緣
62:通孔
620:內邊緣
63:電極
631:連接部
631A:連接部
632:焊球接點
632A:焊球接點
633:導線接點
633A:導線接點
634:導線接點
64:作動區域
65:作動區域
70:焊球
80:互連構件
90:封裝材料
當結合附圖閱讀時，根據以下詳細描述可更好地理解本揭示案的態樣。應注意，根據工業標準實踐，各種特徵未按比例繪製。事實上，為論述清楚，各特徵的尺寸可任意地增加或縮小。
第1-5圖為根據本揭露的部分實施例中製造半導體封裝的下方部分的多個步驟的示意圖。
第6-10圖為根據本揭露的部分實施例中製造半導體封裝的上方部分的多個步驟的示意圖。
第11圖為根據本揭露的部分實施例中製造半導體封裝的步驟中連結上方部分與下方部分的示意圖。
第12圖為根據本揭露的部分實施例的一半導體封裝的剖面圖。
第13圖為根據本揭露的部分實施例的一半導體封裝的上方部分的俯視圖。
以下揭示內容提供許多不同實施例或實例，以便實現各個實施例的不同特徵。下文描述部件及排列的特定實例以簡化本揭示內容。當然，此等實例僅為實例且不意欲為限制性。舉例而言，在隨後描述中在第二特徵上方或在第二特徵上第一特徵的形成可包括第一及第二特徵形成為直接接觸的實施例，以及亦可包括額外特徵可形成在第一及第二特徵之間，使得第一及第二特徵可不直接接觸的實施例。另外，本揭示案在各實例中可重複元件符號及/或字母。此重複為出於簡單清楚的目的，且本身不指示所論述各實施例及/或配置之間的關係。
此外，其與空間相關用詞，例如“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞，是為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關是。除了在圖式中繪示的方位外，這些空間相關用詞意欲包含使用中或操作中的裝置之不同方位。裝置可能被轉向不同 方位(旋轉90度或其他方位)，則在此使用的空間相關詞也可依此相同解釋。
應當理解的是，當一元件被稱為『連接』或『耦接』至另一元件時，它可以為直接連接或耦接至另一元件，又或是其中有一額外元件存在。相對的，當一元件被稱為『直接連接』或『直接耦接』至另一元件時，其中是沒有額外元件存在。
根據本揭露的部分實施例，一種製造半導體封裝的方法說明如下：
第1-5圖為根據本揭露的部分實施例中，製造一半導體封裝的下方部分的多個步驟的示意圖。如第1圖所示，準備半導體封裝下方部分的步驟從提供第一晶片10開始。第一晶片10可以包括由半導體材料製成的半導體基板，該半導體材料包括但不限於塊狀矽、半導體晶片、絕緣體上矽(silicon-on-insulator，SOI)基板或矽鍺基板。也可以使用包括III族、IV族和V族元素的其他半導體材料。
另外，第一晶片10還可包括電子層。電子層可以包括多個微電子元件。微電子元件的示例包括電晶體(例如，金屬氧化物半導體場效應電晶體(MOSFET)、互補金屬氧化物半導體(CMOS)電晶體、雙極型接面電晶體(BJT)、高壓電晶體、高頻電晶體、p通道和/或n通道場效應電晶體(PFET/NFET)等)；電阻器二極管；電容器；電感器；保險絲；和其他合適的裝置。各種加工可用於形成上述微電子元件，包括沉積、蝕刻、注入、微影、退火和其他合適的加工。微電子 元件互連以形成積體電路，例如邏輯裝置、儲存裝置(例如SRAM)、射頻裝置、輸入/輸出(I/O)裝置、系統整合晶片(system-on-chip，SOC)裝置、系統晶片(system-in-chip，SIC)裝置，其組合以及其他合適類型的裝置。
在一些實施例中，第一晶片10還包括形成在第一晶片10的作動表面11上的多個接線墊12。在部分實施例中，接線墊12電連接至在第一晶片10中的微電子元件並沿作動表面11的中心區域對齊。接線墊12可為形成在半導體晶片表面附近的各種端子中的任何一個，通過該端子晶片內的積體電路與外部電路之間進行電連接。
如第2圖所示，準備半導體封裝下方部分的步驟更包括提供一第一連接板20。在部分實施例中，第一連接板20包括一支撐層21及複數個電極23。通孔22形成於支撐層21上。通孔22位於支撐層21的中央區域，並且作動區域24及作動區域25位於通孔22的兩側。每一作動區域24、25將內邊緣220連接到支撐層21的外邊緣210。
電極23根據封裝基板的焊盤(如下所述)配置方式而排列在作動區域24或作動區域25上。在部分實施例中，每個電極23包括一連接部231、一焊球接點232和二個導線接點233、234。連接部231可以具有條形形狀，並且連接部231的延伸方向可以垂直於內邊緣220和外邊緣210。焊球接點232形成在連接部231的中央。導線接點233形成在連接部231與外邊緣210相鄰的一端，導線接點234形成在連接部231與內邊緣 220相鄰的另一端部。焊球接點232以及導線接點233、234的寬度可以比連接部231的寬度大，以利導電元件的電子連接。
如第3圖所示，準備半導體封裝下方部分的步驟更包括連接第一連接板20至第一晶片10。在部分實施例中，支撐層21之上與電極23所處的表面相對的後表面與第一晶片10的作動表面11直接接觸。支撐層21可以使用本領域已知的常規方法通過黏合劑層(未示出)附接到第一晶片10的作動表面11上。在組裝第一晶片10和第一連接板20之後，將第一連接板20的通孔22暴露出一個或多個接線墊12，並且每個接線墊12與其中一個電極23相鄰。支撐層21可以是印刷電路板。在部分實施例中，支撐層21可以由陶瓷、有機物、玻璃和/或半導體材料或結構製成。
在一些實施例中，支撐層21的尺寸與作動表面11的尺寸實質相同，並且在第一晶片10組裝至第一連接板20後，支撐層21的外邊緣210與第一晶片10的外邊緣110重疊。然而，應當理解，可以對本揭露的實施例做出許多變化和修改。在支撐層21的尺寸小於作動表面11的尺寸的情況下，在第一晶片10和第一連接板20組裝之後，支撐層21的外邊緣210可以遠離作動表面11的外邊緣110。
如第4圖所示，準備半導體封裝下方部分的步驟更包括連接第一連接板20耦接至第一晶片10。在部分實施例中，數個接合引線31用於將第一連接板20連接至第一晶片10。詳而言之，每個接合引線31從接線墊12其中之一者形成 到相鄰的導線接點234。接合引線31可以穿過通孔22，並且每個接合引線31的垂直投影的至少一部分位於通孔22內部。
如第5圖所示，準備半導體封裝下方部分的步驟更包括將第一晶片10以及第一連接板20放置於封裝基板40。在部分實施例中，封裝基板40可以是印刷電路板、陶瓷、有機物、玻璃和/或半導體材料或結構，以提供電源、接地、控制、監視等功能的基礎。
在一些實施例中，封裝基板40包括佈線特徵，例如焊盤43或走線層(未示出)，以將電子訊號傳送往返於第一晶片10。在將第一晶片10放置在封裝基板40之後，通過將接合引線32從一個焊盤43形成到相鄰的導線接點233，以將第一晶片10連接至封裝基板40。如此，半導體封裝的下方部分1L則製作完成。封裝基板40可進一步包括形成在封裝基板40的底面上的多個焊球45(第12圖)，用於將電子訊號傳送至其他電器裝置(例如，主機板或其他晶片組)。
第6-10圖為根據本揭露的部分實施例中，製造半導體封裝的上方部分的多個步驟的示意圖。
如第6圖所示，準備半導體封裝上方部分的步驟從提供第二晶片50開始。第二晶片50可以包括由半導體材料製成的半導體基板，該半導體材料包括但不限於塊狀矽、半導體晶片、絕緣體上矽(silicon-on-insulator，SOI)基板或矽鍺基板。也可以使用包括III族、IV族和V族元素的其他半導體材料。
另外，第二晶片50還可包括電子層。電子層可以包括多個微電子元件。微電子元件的示例包括電晶體(例如，金屬氧化物半導體場效應電晶體(MOSFET)、互補金屬氧化物半導體(CMOS)電晶體、雙極型接面電晶體(BJT)、高壓電晶體、高頻電晶體、p通道和/或n通道場效應電晶體(PFET/NFET)等)；電阻器二極管；電容器；電感器；保險絲；和其他合適的元素。各種加工可用於形成上述微電子元件，包括沉積、蝕刻、注入、微影、退火和其他合適的加工。微電子元件互連以形成積體電路，例如邏輯裝置，儲存裝置(例如SRAM)，射頻裝置，輸入/輸出(I/O)裝置，系統整合晶片(system-on-chip，SOC)裝置，系統晶片(system-in-chip，SIC)裝置，其組合以及其他合適類型的裝置。
在一些實施例中，第二晶片50還包括形成在第二晶片50的作動表面51上的多個接線墊52。在部分實施例中，接線墊52電連接至在第二晶片50中的微電子元件並沿作動表面51的中心區域對齊。接線墊52可為形成在半導體晶片表面附近的各種端子中的任何一個，通過該端子晶片內的積體電路與外部電路之間進行電連接。
如第7圖所示，準備半導體封裝上方部分的步驟更包括提供一第二連接板60。在部分實施例中，第二連接板60包括一支撐層61及複數個電極63。通孔62形成於支撐層61上。通孔62位於支撐層61的中央區域，並且兩個作動區域64、65位於通孔62的兩側。每一作動區域64、65將內邊緣620連接到支撐層61的外邊緣610。
電極63根據封裝基板的焊盤配置方式而排列在作動區域64或作動區域65上(如下所述)。在部分實施例中，每個電極63包括一連接部631、一焊球接點632和二個導線接點633、634。連接部631可以具有條形形狀，並且連接部631的延伸方向可以垂直於內邊緣620和外邊緣610。焊球接點632形成在連接部631的中央。導線接點633形成在連接部631與外邊緣610相鄰的一端，導線接點634形成在連接部631與內邊緣620相鄰的另一端部。焊球接點632以及導線接點633、634的寬度可以比連接部631的寬度大，以利導電元件的電子連接。
如第8圖所示，準備半導體封裝上方部分的步驟更包括連接第二連接板60至第二晶片50。在部分實施例中，支撐層61之上與電極63所處的表面相對的後表面與第二晶片50的作動表面51直接接觸。支撐層61可以使用本領域已知的常規方法通過黏合劑層(未示出)附接到第二晶片50的作動表面51上。在組裝第二晶片50和第二連接板60之後，將第二連接板60的通孔62暴露出一個或多個接線墊52，並且每個接線墊52與其中一個電極63相鄰。支撐層61可以是印刷電路板。在部分實施例中，支撐層61可以由陶瓷、有機物、玻璃和/或半導體材料或結構製成。
在一些實施例中，支撐層61的尺寸與作動表面51的尺寸實質相同，並且在第二晶片50組裝至第二連接板60後，支撐層61的外邊緣610與第二晶片50的外邊緣510重疊。然而，應當理解，可以對本揭露的實施例做出許多變化和修改。在支撐層61的尺寸小於作動表面51的尺寸的情況下，在 第二晶片50和第二連接板60組裝之後，支撐層61的外邊緣610可以遠離作動表面51的外邊緣510。
如第9圖所示，準備半導體封裝上方部分的步驟更包括連接第二連接板60耦接至第二晶片50。在部分實施例中，數個接合引線33用於將第二連接板60連接至第二晶片50。詳而言之，每個接合引線33從接線墊52其中之一者形成到相鄰的導線接點634。接合引線33可以穿過通孔62，並且每個接合引線33的垂直投影的至少一部分位於通孔62內部。
如第10圖所示，準備半導體封裝上方部分的步驟更包括分配焊球70至電極63的焊球接點632之上。焊球70可為錫球。如此，半導體封裝上方部分1U即完成製作。
參照第11圖，在下方部分1L與上方部分1U完成後，如第12圖所示，製作半導體封裝1的方法更包括藉由上下翻轉上方部分1U使焊球70位於焊球接點232、632之間，以組裝下方部分1L與上方部分1U。在本揭露中，由於第一連接板20、第二連接板60及焊球70配置用於在第一晶片10和第二晶片50傳送訊號，第一連接板20、第二連接板60及焊球70亦稱作「互連構件80」。封裝材料90可以包括熱固性環氧樹脂。如此，完成半導體封裝1的製作。
如第12圖所示，當上方部分1U堆疊在下部部分1L之上時，第一晶片10的作動表面11面向上，第二晶片50的作動表面51面向下。互連構件80位於作動表面11和作動表面51之間。另外，第一連接板20的通孔22在與封裝基板40垂直 的方向上與第二連接板60的通孔62對齊。接合引線31和33相對於通孔22和62設置。
應當理解的是，雖然接合引線31、接合引線32和接合引線33各自用於將封裝基板40連接到第一晶片10，並且將第一晶片10連接到第一連接板20，並且將第二晶片50連接到第二連接板60，但本揭露並不僅此為限。在部分實施例中，在第一晶片10中形成有層間連接點(未示出)，並且省略了接合引線32。第一晶片10經由形成在第一晶片10背面上諸如凸塊的連接件連接至封裝基板40。在部分實施例中，第一連接板20和第二連接板60其中之一由形成於相對應晶片上的再分佈層(redistribution layer，RDL)所代替，但是保留了第一連接板20和第二連接板60中的另一個，其中再分佈層直接連接到焊球70。
第13圖是根據本揭露的一些實施例的半導體封裝的上方部分的俯視圖。本揭露還可以應用於接合焊盤52A是沿著第二晶片50A的邊緣設置的樣態，並且引線連接至在第二連接板60A上的電極63A。
在一實施例中，第二連接板60A的支撐層61A在中心區域上沒有形成通孔，並且支撐層61A的外邊緣610A遠離第二晶片50A的外邊緣510A。接合焊盤52A位於外邊緣510A和外邊緣610A之間。電極63A包括連接部631A、焊球接點632A和導線接點633A。焊球接點632A和導線接點633A連接到連接部631A的兩端。焊球70分配在焊球接點632A上。接合引線34自導線接點633A形成至相鄰的接合焊盤52A。
本揭露的實施例使用互連構件在面對面的雙晶片封裝(face to face dual die package，F2F DDP)中耦合兩個半導體晶片。由於至少一個晶片上不需形成再分配層(RDL)，因此降低了半導體封裝的製造成本，並且降低了產品設計複雜度以及每個半導體封裝的部件數量。
儘管已經參考某些實施例相當詳細地描述了本揭露的內容，但是其他實施例也是有可能的。因此，所附申請專利範圍的精神和範圍不應限於這裡包含的實施例的描述。
對於本領域技術人員可顯而易見的是，在不脫離本揭露的範圍或精神的情況下，可以對本揭露的結構進行各種修改和變化。鑑於前述內容，本揭露包括上述實施例的修改和變化，只要它們落入所附申請專利範圍的範圍內即可。
1‧‧‧半導體封裝
1L‧‧‧下方部分
1U‧‧‧上方部分
10‧‧‧第一晶片
11‧‧‧作動表面
12‧‧‧接線墊
20‧‧‧第一連接板
22‧‧‧通孔
23‧‧‧電極
31‧‧‧接合引線
32‧‧‧接合引線
33‧‧‧接合引線
40‧‧‧封裝基板
45‧‧‧焊球
50‧‧‧第二晶片
51‧‧‧作動表面
52‧‧‧接線墊
60‧‧‧第二連接板
62‧‧‧通孔
63‧‧‧電極
70‧‧‧焊球
80‧‧‧互連構件
90‧‧‧封裝材料

Claims (10)

  1. 一種半導體封裝，包括：
    一封裝基板；
    一第一晶片，設置於該封裝基板之上；
    一第二晶片，設置於該第一晶片上方；
    一互連構件，包括：
    一第一連接板，連接該第一晶片；
    一第二連接板，連接該第二晶片；以及
    一焊球，耦接於該第一連接板與該第二連接板；以及
    複數個接合引線，耦接該互連構件至該封裝基板、該第一晶片與該第二晶片。
  2. 如申請專利範圍第1項所述的半導體封裝，其中該第一連接板具有一第一通孔暴露出該第一晶片的一接線墊，並且該等接合引線其中之一者通過該第一通孔，以耦接該第一晶片的該接線墊至該第一連接板。
  3. 如申請專利範圍第2項所述的半導體封裝，其中該第二連接板具有一第二通孔暴露出該第二晶片的一接線墊，並且該等接合引線中的另一者通過該第二通孔，以耦接該第二晶片的該接線墊至該第二連接板。
  4. 如申請專利範圍第1項所述的半導體封裝，其中該第一連接板及該第二連接板各自包括一支撐層及設置於該支撐層之上的一電極。
  5. 如申請專利範圍第4項所述的半導體封裝，其中該第一連接板及該第二連接板的該等電極位於該焊球的兩側。
  6. 一種製造半導體封裝的方法，包括：
    提供一封裝基板；
    放置一第一晶片在該封裝基板之上；
    放置一第二晶片在該第一晶片上方；
    藉由一互連構件耦接該第一晶片及該第二晶片，其中該互連構件的一第一連接板連接至該第一晶片，該互連構件的一第二連接板連接至該第二晶片，且該互連構件的一焊球連接至該第一連接板及該第二連接板；以及
    藉由複數個接合引線耦接該互連構件至該封裝基板、該第一晶片及該第二晶片。
  7. 如申請專利範圍第6項所述製造半導體封裝的方法，其中該等接合引線其中之一者形成於該第一晶片的一接線墊與該第一連接板之間並通過形成在該第一連接板上的一通孔。
  8. 如申請專利範圍第7項所述製造半導體封裝的方法，其中該等接合引線其中之另一者形成於該第二晶片的一接線墊與該第二連接板之間並通過形成在該第二連接板上的一通孔。
  9. 如申請專利範圍第6項所述製造半導體封裝的方法，其中該第一連接板及該第二連接板各自包括一支撐層及設置於該支撐層之上的一電極。
  10. 如申請專利範圍第9項所述製造半導體封裝的方法，其中該第一連接板及該第二連接板的該等電極位於該焊球的兩側。
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