CN109786339B - 半导体封装与其制造方法 - Google Patents

半导体封装与其制造方法 Download PDF

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CN109786339B
CN109786339B CN201611225737.9A CN201611225737A CN109786339B CN 109786339 B CN109786339 B CN 109786339B CN 201611225737 A CN201611225737 A CN 201611225737A CN 109786339 B CN109786339 B CN 109786339B
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semiconductor
package
interposer
semiconductor die
die
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CN109786339A (zh
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林柏均
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明公开了一种半导体封装与其制造方法，半导体封装包含封装基板、第一半导体晶片、第二半导体晶片与上中介层。第一半导体晶片与第二半导体晶片置于封装基板上。上中介层电性连接至第一半导体晶片与第二半导体晶片。第一半导体晶片与第二半导体晶片置于封装基板与上中介层之间。因上中介层连接半导体晶片，使得一个半导体晶片可通过上中介层而电性连接至另一个半导体晶片。亦即，上中介层在半导体晶片之间提供晶片至晶片的连接。

Description

半导体封装与其制造方法
技术领域
本发明是有关于一种半导体封装
背景技术
集成电路(integrated circuit,IC)制造技术整合了多数不同功能，例如中央处理单元逻辑、图形功能、快取记忆体与其他系统功能，以制作集成系统上晶片(system-on-chip,SOC)或系统中晶片(system-in-chip,SIC)的设计。SOC/SIC设计可降低制产品设计的复杂度与降低每个产品的元件数量。集成电路为微型装置，其具有微小的接触垫以连接其他的集成电路或非集成电路元件。把连接到其他元件的连接件制作在基板，例如印刷电路板(printed circuit board,PCB)，上。然而，产品可能需要一个具有不同功能且分别封装的系统板，其可能会增加系统板的面积，造成功率损失，以及整合成本的增加。
发明内容
本发明的目的在于提供一种半导体封装与其制造方法，以降低产品设计难度和产品元件数量及制造成本。
本发明的一实施例是提供一种半导体封装，包含封装基板、第一半导体晶片、第二半导体晶片与上中介层。第一半导体晶片与第二半导体晶片置于封装基板上。上中介层电性连接至第一半导体晶片与第二半导体晶片。第一半导体晶片与第二半导体晶片置于封装基板与上中介层之间。
在一个或多个实施方式中，半导体封装还包含至少一个连接元件，置于第一半导体晶片与封装基板之间以连接第一半导体晶片与封装基板。
在一个或多个实施方式中，第一半导体晶片与第二半导体晶片之间具有间隙，该间隙至少部分置于上中介层与封装基板之间。
在一个或多个实施方式中，上中介层包含核心与第一走线层。核心具有相对的第一表面与第二表面。第一表面面向封装基板。第一走线层置于第一表面上。第一走线层连接第一半导体晶片与第二半导体晶片。
在一个或多个实施方式中，上中介层还包含第二走线层，置于第二表面上。
在一个或多个实施方式中，第二走线层电性连接第一半导体晶片。
在一个或多个实施方式中，半导体封装还包含第三半导体晶片，置于上中介层上。
在一个或多个实施方式中，第三半导体晶片电性连接至上中介层。
在一个或多个实施方式中，半导体封装还包含第四半导体晶片，置于第三半导体晶片与上中介层之间。第四半导体晶片中包含贯穿结构以连接第三半导体晶片与上中介层。
在一个或多个实施方式中，上中介层中包含贯穿结构以连接第一半导体晶片与第三半导体晶片。
在一个或多个实施方式中，半导体封装还包含第四半导体晶片，电性连接第三半导体晶片。第三半导体晶片置于第四半导体晶片与上中介层之间。
在一个或多个实施方式中，半导体封装还包含第三半导体晶片，置于第一半导体晶片与封装基板之间。
在一个或多个实施方式中，半导体封装还包含下中介层，置于第一半导体晶片与封装基板之间。
在一个或多个实施方式中，下中介层电性连接至第一半导体晶片与第二半导体晶片之间。
在一个或多个实施方式中，下中介层中包含贯穿结构以连接第一半导体晶片与封装基板。
本发明的另一实施例是提供一种半导体封装的制造方法，包含在封装基板上放置第一半导体晶片与第二半导体晶片。黏合第一半导体晶片与第二半导体晶片。在第一半导体晶片与第二半导体晶片上放置上中介层以连接第一半导体晶片与第二半导体晶片。第一半导体晶片与第二半导体晶片置于上中介层与封装基板之间。
在一个或多个实施方式中，制造方法还包含在封装基板上放置下中介层。第一半导体晶片与第二半导体晶片置于下中介层上且置于上中介层与下中介层之间。
在一个或多个实施方式中，制造方法还包含在上中介层上放置第三半导体晶片。
本发明的再一实施例是提供一种半导体封装的制造方法，包含在上中介层上放置第一半导体晶片与第二半导体晶片。黏合第一半导体晶片与第二半导体晶片。在第一半导体晶片与第二半导体晶片上放置封装基板。第一半导体晶片与第二半导体晶片置于封装基板与上中介层之间。
在一个或多个实施方式中，制造方法还包含在第一半导体晶片与第二半导体晶片上放置下中介层。第一半导体晶片与第二半导体晶片置于下中介层与上中介层之间。
在上述实施方式中，上中介层连接半导体晶片，使得一个半导体晶片可通过上中介层而电性连接至另一个半导体晶片。亦即，上中介层在半导体晶片之间提供晶片至晶片(chip-to-chip)的连接。
附图说明
图1为本发明一些实施方式的半导体封装的立体图。
图2为图1的半导体封装的侧视图。
图3为依据本发明一些实施方式的半导体封装的侧视图。
图4为依据本发明一些实施方式的半导体封装的侧视图。
图5为依据本发明一些实施方式的半导体封装的侧视图。
图6为依据本发明一些实施方式的半导体封装的侧视图。
图7为依据本发明一些实施方式的半导体封装的侧视图。
图8为依据本发明一些实施方式的半导体封装的侧视图。
图9为依据本发明一些实施方式的半导体封装的侧视图。
图10A至图10D为根据本发明一些实施方式的半导体封装的制造方法在不同阶段的立体图。
图11为根据本发明一些实施方式的半导体封装的制造方法的流程图。
图12为根据本发明一些实施方式的半导体封装的制造方法的流程图。
图13A至图13D为根据本发明一些实施方式的半导体封装的制造方法在不同阶段的立体图。
图14为根据本发明一些实施方式的半导体封装的制造方法的流程图。
图15为根据本发明一些实施方式的半导体封装的制造方法的流程图。
具体实施方式
以下将以附图公开本发明的多个实施方式，为明确说明起见，许多实务上的细节将在以下叙述中一并说明。然而，应了解到，这些实务上的细节不应用以限制本发明。也就是说，在本发明部分实施方式中，这些实务上的细节是非必要的。此外，为简化附图起见，一些公知惯用的结构与元件在附图中将以简单示意的方式绘示。
图1为本发明一些实施方式的半导体封装的立体图，而图2为图1的半导体封装的侧视图。半导体封装包含封装基板110、多个半导体晶片与上中介层130。举例而言，在图1中，半导体封装包含二个半导体晶片120a与120b，然而本发明不以此为限。半导体晶片120a与120b置于封装基板110上。上中介层130电性连接至半导体晶片120a与120b，且半导体晶片120a与120b置于封装基板110与上中介层130之间。
在本实施方式中，上中介层130连接半导体晶片120a与120b，使得半导体晶片120a可通过上中介层130而电性连接至半导体晶片120b。亦即，上中介层130在半导体晶片120a与120b之间提供晶片至晶片(chip-to-chip)的连接。在本实施方式中，半导体晶片120a与120b之间形成间隙G，且间隙G至少部分置于上中介层130与封装基板110之间。
至少一个半导体晶片120a与120b包含半导体基板122与第一电路层124，第一电路层124形成于半导体基板110中或上。半导体晶片120a与120b可通过多种合适的架构包含，如绘示的覆晶架构，或其他架构如打线接合方式以接至封装基板110。在覆晶架构中，半导体晶片120a与120b的第一电路层124利用连接元件140，例如凸块或其他合适的连接元件以接至封装基板110。亦即，连接元件140置于半导体晶片120a和120b与封装基板110之间，以连接至少一个半导体晶片120a或120b与封装基板110。在图1与图2中，一些连接元件140置于半导体晶片120a与封装基板110之间，且另一些连接元件140置于半导体晶片120b与封装基板110之间。在一些其他的实施方式中，半导体晶片120a连接至封装基板110，但半导体晶片120b与封装基板110电性绝缘。
半导体基板122的材质可为半导体材料，包含，但不限于块硅、半导体晶圆、绝缘层上硅基板或硅化锗基板。其他半导体材料包含第三族、第四族与第五族的元素可被利用。第一电路层124可包含多个微电子元件。微电子元件例如包含电晶体(例如金属氧化半导体场效电晶体(metal oxide semiconductor field effect transistors,MOSFET)、互补金属氧化半导体(complementary metal oxide semiconductor,CMOS)电晶体、双极性电晶体(bipolar junction transistors,BJT)、高压电晶体、高频电晶体、P型通道与/或N型通道场效电晶体(PFET/NFET)等等)、电阻、二极管、电容、电感、保险丝与/或其他合适的元件。可执行不同的工艺以形成不同的微电子元件，例如沉积、蚀刻、布植、光微影、退火与/或其他合适的工艺。微电子元件可互相连接以形成集成电路，例如逻辑装置、记忆体装置(例如静态随机存储器(SRAM))、无线电频率(RF)装置、输入/输出(input/output,I/O)装置、晶片上系统(system-on-chip,SoC)装置、晶片中系统(system-in-chip,SIC)装置、其组合与/或其他合适种类的装置。
至少一个半导体晶片120a与120b还包含第二电路层126，置于封装基板110内或上且相对于第一电路层124。亦即，半导体基板122置于第一电路层124与第二电路层126之间。第二电路层126可包含多个上述的微电子元件或者为重分布层。在一些实施方式中，第二电路层126可经由贯穿结构或外部线路结构(未绘示)以连接至第一电路层124。
上中介层130具有核心132与第一走线层134。第一走线层134可包含多个走线。核心132具有相对的第一表面132a与第二表面132b。第一表面132a面向封装基板110。第一走线层134置于核心132的第一表面132a。第一走线层134连接半导体晶片120a与120b。在一些实施方式中，第一走线层134为重分布层或逻辑元件，本发明不以此为限。在一些实施方式中，上中介层130的核心132的材质可为陶瓷、有机材料、玻璃与/或半导体材料或结构(例如为硅或绝缘层上硅)。
半导体封装还包含多个连接元件160，置于上中介层130与半导体晶片120a与120b之间以连接上中介层130与半导体晶片120a与120b。在一些实施方式中，连接元件160可为凸块，其相较于连接打线的接合垫具有较小的接合面积，使得第一走线层134的布线可较密集，因此上中介层130的尺寸可缩小。不过在其他一些实施方式中，连接元件160可为打线或其他合适的结构。
在图1与图2中，封装基板110可为印刷电路板、陶瓷、有机材、玻璃与/或半导体材料或结构，其提供背板电源、接地、控制与监控等等。封装基板110可包含电路绕线特征，以将电子信号从半导体晶片120a与/或120b提取或送至半导体晶片120a与/或120b。在一些实施方式中，封装基板110可包含如垫或走线层(未绘示)的电路绕线特征，以接收连接元件140与从半导体晶片120a与/或120b提取或送至半导体晶片120a与/或120b的电子信号。多个连接件150例如焊球可耦合至封装基板110的表面以进一步将电子信号连至其他电子装置(例如主机板或其他晶片组)。
虽然图1绘示二个半导体晶片120a与120b以及一个上中介层130，在其他的实施方式中，可包含更多以其他可能方式(包含三维结构)连接的半导体晶片与上中介层130。
图3为依据本发明一些实施方式的半导体封装的侧视图。图3与图2的半导体封装的不同处在于连接元件165。在图3中，上中介层130还包含第二走线层136，相对于第一走线层134。亦即，第二走线层136置于核心132的第二表面132b上，且核心132置于第一走线层134与第二走线层136之间。第二走线层136可包含多个走线。在一些实施方式中，第二走线层136为重分布层或逻辑元件，本发明不以此为限。第二走线层136可电性连接至半导体晶片120a与/或120b。举例而言，半导体封装可还包含至少一个连接元件165(例如为打线)连接第二走线层136与半导体晶片120a或120b。通过多个连接元件165，半导体晶片120a与120b可还通过第二走线层136而连接彼此。因半导体晶片120a与120b可通过第一走线层134与第二走线层136连接彼此，第一走线层134与第二走线层136的布线面积可减少。至于图3的半导体封装的其他结构细节与图2的半导体封装相似，因此便不再赘述。
图4为依据本发明一些实施方式的半导体封装的侧视图。图4与图3的半导体封装的不同处在于半导体晶片120c。在图4中，半导体晶片120c置于上中介层130上。半导体晶片120c可为覆晶架构，而半导体晶片120c的第一电路层124则接触上中介层130的第二走线层136。因此，半导体晶片120c可通过第二走线层136而电性连接至半导体晶片120a与/或半导体晶片120b。在一些实施方式中，连接元件145可置于半导体晶片120c与上中介层130之间以连接半导体晶片120c与上中介层130。连接元件145可为凸块或其他合适的结构。至于图4的半导体封装的其他结构细节与图3的半导体封装相似，因此便不再赘述。
图5为依据本发明一些实施方式的半导体封装的侧视图。图5与图4的半导体封装的不同处在于上中介层130的架构。在图5中，上中介层130还包含贯穿结构138，连接第一走线层134与第二走线层136。贯穿结构138可为晶片穿孔贯穿结构(through-die via,TDV)，而如果上中介层130的核心132的材质为硅，则贯穿结构138则为硅穿孔贯穿结构(through-silicon via,TSV)。如此一来，半导体晶片120c可电性连接至半导体晶片120a与/或半导体晶片120b。在一些实施方式中，图4的连接元件165可省略。至于图5的半导体封装的其他结构细节与图4的半导体封装相似，因此便不再赘述。
图6为依据本发明一些实施方式的半导体封装的侧视图。图6与图4的半导体封装的不同处在于半导体晶片120d的存在。在图6中，半导体封装还包含半导体晶片120d，置于半导体晶片120c与上中介层130之间。半导体晶片120c与120d形成半导体晶片堆叠。半导体晶片120d电性连接至上中介层130。在一些实施方式中，半导体晶片120c电性连接至半导体晶片120d。在一些其他的实施方式中，半导体晶片120c通过置于半导体晶片120d中的贯穿结构180(例如TDV与/或TSV)或者打线(未绘示)而电性连接半导体晶片120c与上中介层130。在一些其他的实施方式中，形成于上中介层130上的半导体晶片堆叠可包含多于两个半导体晶片。在一些其他的实施方式中，多于一个半导体晶片堆叠可置于上中介层130上并通过上中介层130而连接彼此。通过如此的架构，半导体晶片之间的互连路径因上中介层130的存在而减少，且半导体晶片中的贯穿结构180的数量也可减少，其缩小半导体晶片的排除区域(keep-out zones,KOZs)。至于图6的半导体封装的其他结构细节与图4的半导体封装相似，因此便不再赘述。
图7为依据本发明一些实施方式的半导体封装的侧视图。图7与图2的半导体封装的不同处在于半导体晶片120e与120f的存在。在图7中，半导体晶片120e置于半导体晶片120a与封装基板110之间，因此半导体晶片120a与120e形成一个半导体晶片堆叠。半导体晶片120f置于半导体晶片120b与封装基板110之间，因此半导体晶片120b与120f形成另一个半导体晶片堆叠。半导体晶片120e与120f可具有与半导体晶片120a与120b相似的架构。半导体晶片堆叠置于上中介层130与封装基板110之间。在一些实施方式中，上中介层130可连接二个半导体晶片堆叠的半导体晶片。举例而言，上中介层130可通过分别形成于半导体晶片120a与120b的贯穿结构180而连接半导体晶片120e与120f。在一些其他的实施方式中，半导体晶片120a可通过上中介层130与置于半导体晶片120b中的贯穿结构180而连接半导体晶片120f，然而本发明不以此为限。在一些实施方式中，半导体晶片120c或图6的半导体晶片堆叠可置于上中介层130上，且依照实际需求而电性连接至其他半导体晶片。至于图7的半导体封装的其他结构细节与图2的半导体封装相似，因此便不再赘述。
图8为依据本发明一些实施方式的半导体封装的侧视图。图8与图7的半导体封装的不同处在于下中介层190的存在。在图8中，半导体封装还包含下中介层190，置于半导体晶片120a与封装基板110之间以及半导体晶片120b与封装基板110之间。下中介层190具有核心192与面向半导体晶片120a、120b、120e与120f的第一走线层194。第一走线层194可包含多个走线。第一走线层194连接至少二个半导体晶片120a、120b、120e与120f。举例而言，半导体晶片120a可通过在半导体晶片120e与120f的贯穿结构(未绘示)与下中介层190而电性连接至半导体晶片120b。在一些实施方式中，第一走线层194可为重分布层或逻辑装置，而本发明不以此为限。在一些实施方式中，下中介层190的核心192的材质可为陶瓷、有机材料、玻璃与/或半导体材料或结构(例如为硅或绝缘层上硅)。至于图8的半导体封装的其他结构细节与图7的半导体封装相似，因此便不再赘述。
图9为依据本发明一些实施方式的半导体封装的侧视图。图9与图8的半导体封装的不同处在于贯穿结构195的存在。在图9中，下中介层190还包含至少一个贯穿结构195，且贯穿结构195连接至少一个半导体晶片120a、120b、120e与120f以及封装基板110。至于图9的半导体封装的其他结构细节与图8的半导体封装相似，因此便不再赘述。
以下提供根据一些实施方式的一种半导体封装的制造方法。图10A至图10D为根据本发明一些实施方式的半导体封装的制造方法于不同阶段的立体图，而图11为根据本发明一些实施方式的半导体封装的制造方法的流程图。在以下的实施方式中，之前提及的结构与材料细节将不再重复，仅提供额外的数据以说明图10A至图10D的半导体封装。请先参照图10A与图11。提供封装基板110。封装基板110可为印刷电路板、陶瓷、有机材、玻璃与/或半导体材料或结构，其提供背板电源、接地、控制与监控等等。
在步骤S12中，多个半导体晶片置于(或接触至或固定至或接合至)封装基板110。举例而言，二个半导体晶片120a与120b置于封装基板110上。至少一个半导体晶片120a与120b包含半导体基板122、第一电路层124与第二电路层126。半导体基板122置于第一电路层124与第二电路层126之间。半导体晶片120a与120b的第一电路层124可通过连接元件140而接合至封装基板110。在一些实施方式中，连接元件140可为凸块。在一些实施方式中，至少一个半导体晶片120a与120b还包含至少一个贯穿结构(TDV或TSV)以连接第一电路层124与第二电路层126。
接着请参照图10B与图11。在步骤S14中，黏合半导体晶片120a与120b。在一些实施方式中，可利用点胶(underfill dispenser)210黏合半导体晶片120a与120b，以于半导体晶片120a、120b与封装基板110之间形成机械键结。在一些实施方式中，点胶210的材质可为树脂或其他合适的材料。
接着请参照图10C与图11。上中介层130置于(或接触至或固定至或接合至)半导体晶片120a与120b上，使得上中介层130连接半导体晶片120a与120b如步骤S16所示。上中介层130包含核心132与形成于核心132上的第一走线层134。第一走线层134面向半导体晶片120a与120b。多个连接元件160可形成于上中介层130的第一走线层134，而上中介层130再通过连接元件160固定于半导体晶片120a与120b上。或者，连接元件160可形成于半导体晶片120a与120b上，而上中介层130再通过连接元件160固定于半导体晶片120a与120b上。如此一来，半导体封装即完成。
在一些实施方式中，若至少一个半导体晶片120c置于(或接触至或固定至或接合至)上中介层130上，则上中介层130还包含第二走线层136，相对第一走线层134设置。第二走线层136可具有布线架构，以连接半导体晶片120c与其他元件(例如半导体晶片120a与/或120b)。请参照图10D与图11。在步骤S18中，半导体晶片120c通过，例如，至少一个连接元件145，而固定于上中介层130上。半导体晶片120c包含半导体基板122与置于半导体基板122上的第一电路层124，且第一电路层124面向上中介层130。
图12为根据本发明一些实施方式的半导体封装的制造方法的流程图。在一些实施方式中，如步骤S11所示，下中介层置于(或接触至或固定至或接合至)封装基板上。接着，如步骤S13所示，半导体晶片被固定于下中介层上。下中介层可连接半导体晶片。接着为步骤S14与S16，因其内容已于上述段落描述过，因此便不再赘述。
图13A至图13D为根据本发明一些实施方式的半导体封装的制造方法于不同阶段的立体图，而图14为根据本发明一些实施方式的半导体封装的制造方法的流程图。在以下的实施方式中，之前提及的结构与材料细节将不再重复，仅提供额外的数据以说明图13A至图13D的半导体封装。请先参照图13A与图14。提供上中介层130。上中介层130包含核心132与置于核心132上的第一走线层134。
在步骤S22中，多个半导体晶片置于(或接触至或固定至或接合至)上中介层130。举例而言，二个半导体晶片120a与120b置于上中介层130上，因此上中介层130连接半导体晶片120a与120b。半导体晶片120a与120b的第二电路层126可通过连接元件160而接合至上中介层130的第一走线层134上。在一些实施方式中，连接元件160可为凸块。
请参照图13B与图14。在步骤S24中，黏合半导体晶片120a与120b。在一些实施方式中，可利用点胶(underfill dispenser)210黏合半导体晶片120a与120b，以于半导体晶片120a、120b与上中介层130之间形成机械键结。在一些实施方式中，点胶210的材质可为树脂或其他合适的材料。
接着请参照图13C与图14。封装基板110置于(或接触至或固定至或接合至)半导体晶片120a与120b上，使得半导体晶片120a与120b置于封装基板110与上中介层130之间，如步骤S26所示。举例而言，图13B的结构可翻转并固定于封装基板110上。多个连接元件140可形成于封装基板110，而封装基板110再通过连接元件140固定于半导体晶片120a与120b上。或者，连接元件140可形成于半导体晶片120a与120b上，而封装基板110再通过连接元件140固定于半导体晶片120a与120b上。如此一来，半导体封装即完成。
在一些实施方式中，若至少一个半导体晶片120c置于(或接触至或固定至或接合至)上中介层130上，则上中介层130还包含第二走线层136，相对第一走线层134设置。第二走线层136可具有布线架构，以连接半导体晶片120c与其他元件(例如半导体晶片120a与/或120b)。请参照图13D与第14图。在步骤S28中，半导体晶片120c通过，例如，至少一个连接元件145，而固定于上中介层130上。半导体晶片120c包含半导体基板122与置于半导体基板122上的第一电路层124，且第一电路层124面向上中介层130。
图15为根据本发明一些实施方式的半导体封装的制造方法的流程图。在一些实施方式中，在步骤S24后，下中介层置于半导体晶片上，如步骤S25所示，使得半导体晶片置于上中介层与下中介层之间。下中介层可连接半导体晶片。接着，如步骤S27所示，封装基板固定于下中介层上。
虽然本发明已以实施方式公开如上，然其并非用以限定本发明，任何所属领域的一般技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视权利要求所界定的为准。

Claims (20)

1.一种半导体封装，其特征在于，包含：
封装基板；
第一半导体晶片与第二半导体晶片，置于所述封装基板上；
点胶，被配置成在所述第一半导体芯片与所述第二半导体芯片之间形成机械键结；以及
上中介层，电性连接至所述第一半导体晶片与所述第二半导体晶片，其中所述第一半导体晶片与所述第二半导体晶片置于所述封装基板与所述上中介层之间，且所述点胶与所述封装基板之间或所述点胶与所述上中介层之间具有空气间隙。
2.如权利要求1所述的半导体封装，其特征在于，还包含至少一个连接元件，置于所述第一半导体晶片与所述封装基板之间以连接所述第一半导体晶片与所述封装基板。
3.如权利要求1所述的半导体封装，其特征在于，所述第一半导体晶片与所述第二半导体晶片之间具有间隙，所述间隙至少部分置于所述上中介层与所述封装基板之间。
4.如权利要求1所述的半导体封装，其特征在于，所述上中介层包含：
核心，具有相对的第一表面与第二表面，其中所述第一表面面向所述封装基板；以及
第一走线层，置于所述第一表面上，其中所述第一走线层连接所述第一半导体晶片与所述第二半导体晶片。
5.如权利要求4所述的半导体封装，其特征在于，所述上中介层还包含第二走线层，置于所述第二表面上。
6.如权利要求5所述的半导体封装，其特征在于，所述第二走线层电性连接所述第一半导体晶片。
7.如权利要求1所述的半导体封装，其特征在于，还包含第三半导体晶片，置于所述上中介层上。
8.如权利要求7所述的半导体封装，其特征在于，所述第三半导体晶片电性连接至所述上中介层。
9.如权利要求8所述的半导体封装，其特征在于，还包含第四半导体晶片，置于所述第三半导体晶片与所述上中介层之间，其中所述第四半导体晶片中包含贯穿结构以连接所述第三半导体晶片与所述上中介层。
10.如权利要求7所述的半导体封装，其特征在于，所述上中介层中包含贯穿结构以连接所述第一半导体晶片与所述第三半导体晶片。
11.如权利要求7所述的半导体封装，其特征在于，还包含第四半导体晶片，电性连接所述第三半导体晶片，其中所述第三半导体晶片置于所述第四半导体晶片与所述上中介层之间。
12.如权利要求1所述的半导体封装，其特征在于，还包含第三半导体晶片，置于所述第一半导体晶片与所述封装基板之间。
13.如权利要求1所述的半导体封装，其特征在于，还包含下中介层，置于所述第一半导体晶片与所述封装基板之间。
14.如权利要求13所述的半导体封装，其特征在于，所述下中介层电性连接至所述第一半导体晶片与所述第二半导体晶片之间。
15.如权利要求13所述的半导体封装，其特征在于，所述下中介层中包含贯穿结构以连接所述第一半导体晶片与所述封装基板。
16.一种半导体封装的制造方法，其特征在于，包含：
在封装基板上放置第一半导体晶片与第二半导体晶片；
利用点胶黏合所述第一半导体晶片与所述第二半导体晶片，以于所述第一半导体芯片与所述第二半导体芯片之间形成机械键结；以及
在所述第一半导体晶片与所述第二半导体晶片上放置上中介层以连接所述第一半导体晶片与所述第二半导体晶片，其中所述第一半导体晶片与所述第二半导体晶片置于所述上中介层与所述封装基板之间，且所述点胶与所述上中介层之间具有空气间隙。
17.如权利要求16所述的制造方法，其特征在于，还包含在所述封装基板上放置下中介层，其中所述第一半导体晶片与所述第二半导体晶片置于所述下中介层上且置于所述上中介层与所述下中介层之间。
18.如权利要求16所述的制造方法，其特征在于，还包含在所述上中介层上放置第三半导体晶片。
19.一种半导体封装的制造方法，其特征在于，包含：
在上中介层上放置第一半导体晶片与第二半导体晶片；
利用点胶黏合所述第一半导体晶片与所述第二半导体晶片，以于所述第一半导体芯片与所述第二半导体芯片之间形成机械键结；以及
在所述第一半导体晶片与所述第二半导体晶片上放置封装基板，其中所述第一半导体晶片与所述第二半导体晶片置于所述封装基板与所述上中介层之间，且所述点胶与所述封装基板之间具有空气间隙。
20.如权利要求19所述的制造方法，其特征在于，还包含在所述第一半导体晶片与所述第二半导体晶片上放置下中介层，其中所述第一半导体晶片与所述第二半导体晶片置于所述下中介层与所述上中介层之间。
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