KR20170002266A - 플립 칩 패키징 - Google Patents
플립 칩 패키징 Download PDFInfo
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- KR20170002266A KR20170002266A KR1020150166790A KR20150166790A KR20170002266A KR 20170002266 A KR20170002266 A KR 20170002266A KR 1020150166790 A KR1020150166790 A KR 1020150166790A KR 20150166790 A KR20150166790 A KR 20150166790A KR 20170002266 A KR20170002266 A KR 20170002266A
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Abstract
집적회로(integrated circuit; IC) 패키지는 제1 기판; 제1 기판 위에 배치된 제2 기판; 제1 및 제2 기판을 전기적으로 연결시키도록 제1 및 제2 기판 사이에 배치된 복수의 커넥터들; 제약층과 제1 기판 사이에 캐비티가 형성되도록 제1 및 제2 기판 위에 배치된 제약층; 및 캐비티 내에 배치되고 제약층을 통해 연장하는 몰딩 물질을 포함한다. 제약층은 상단 표면 및 대향하는 하단 표면을 구비하고, 몰딩 물질은 제약층의 상단 표면으로부터 하단 표면으로 연장한다.
Description
반도체 집적 회로(IC) 산업은 기하급수적 성장을 경험하고 있다. IC 물질과 설계의 기술적 발전으로 각 세대가 이전 세대보다 더 작고 복잡한 회로를 갖는 여러 세대의 IC가 생산되어 왔다. IC의 발전 과정에서, 기능적 밀도(즉, 칩 면적 당 상호연결된 장치들의 수)는 전반적으로 증대된 반면, 지오메트리 크기(즉, 제조 공정을 이용하여 생성될 수 있는 최소 부품(또는 라인))는 감소하였다. 이러한 축소 공정은 생산 효율을 증가시키고 관련 비용을 감소시키는 것에 의해 전반적으로 이익을 제공한다. 이러한 축소는 IC 처리 및 제조의 복잡성을 증가시켰다.
IC 처리 및 제공의 이러한 진보가 실현되기 위해서는, IC 패키징에서도 유사한 발전이 필요하다. 예를 들면, IC 칩은 반도체 웨이와 같은 기판 상에 형성된 반도체 장치를 포함하고, 집적회로로의 전기적 인터페이스를 제공하기 위해 금속화 접촉부 또는 부착부, 패드를 포함한다. 칩의 내부 회로와, 예를 들면 회로 기판, 다른 칩 또는 웨이퍼와 같은 외부 회로간의 연결을 제공하기 위한 종래의 기술은 와이어 본딩을 포함하고, 와이어가 칩 접촉 패드를 외부 회로에 연결시키기 위해 이용된다. 플립 칩 패키지라고 알려진 보다 최근의 칩 연결 기술은 IC 칩의 접촉 패드 상으로 퇴적된 솔더 범프를 이용해서 IC 칩을 외부 회로에 연결시키기 위해 제공된다. 칩을 외부 회로(예를 들면, 기판)에 장착시키도록, 칩이 위아래가 뒤집어지고, 이 칩의 접촉 패드가 기판 상에서 매칭되는 접촉 패드와 정렬된다. 그런 다음, 언더필(칩과 기판 사이에 흐르는 접착제)이 뒤집어진 칩과, 회부 회로를 지지하는 기판 사이에서 흘러서 IC 장치와 외부 회로 간의 기계적 및/또는 전기적 상호연결을 완성시킨다. 생성되는 플립 칩 패키지는 종래의 캐리어 기판 시스템보다 훨씬 작은데, 그 이유는 칩이 외부 회로 상에 직접 배치되어 그 결과 상호연결 와이어가 훨씬 짧아질 수 있기 때문이다. 결과적으로, 인덕턴스와 저항 열이 크게 감쇠되어 더 고속의 장치를 가능케 하게 된다.
하지만, 예를 들면, IC 칩, 기판과 같은 플립 칩 패키지의 부품들과 언더필간의 열 확장 불일치의 고유 계수(inherent) 때문에, 높은 패키지 휨 및 열 응력이 플립 칩 패키지 내에 종종 유도된다. 이러한 높은 열 응역과 휨은 칩 내에서 로우-k 상호연결 층(들) 내의 박리를 야기할 뿐만 아니라, 고장을 야기하는 솔더 범프 균일을 초래해서, 플립 칩 패키지의 장기간의 동작 신뢰도를 감퇴시킨다.
집적회로(integrated circuit; IC) 패키지는 제1 기판; 제1 기판 위에 배치된 제2 기판; 제1 및 제2 기판을 전기적으로 연결시키도록 제1 및 제2 기판 사이에 배치된 복수의 커넥터들; 제약층과 제1 기판 사이에 캐비티가 형성되도록 제1 및 제2 기판 위에 배치된 제약층; 및 캐비티 내에 배치되고 제약층을 통해 연장하는 몰딩 물질을 포함한다. 제약층은 상단 표면 및 대향하는 하단 표면을 구비하고, 몰딩 물질은 제약층의 상단 표면으로부터 하단 표면으로 연장한다.
본 발명 개시의 양상은 첨부한 도면과 함께 읽을 때 하기의 상세한 설명으로부터 가장 잘 이해된다. 업계의 표준적 관행에 따라, 다양한 특징부들은 실제 크기대로 도시되지 않는 것을 주목해야 한다. 사실상, 다양한 특징부들의 치수는 논의의 명확성을 위해 임의로 증가되거나 감소될 수 있다.
도 1은 본 발명 개시의 실시예에 따라 반도체 장치를 패키징하는 흐름도를 예증한다.
도 2a 내지 2f는 본 발명의 일부 실시예에 따라 다양한 제조 스테이지들에서 패키징된 반도체 장치의 단면도를 예증한다.
도 1은 본 발명 개시의 실시예에 따라 반도체 장치를 패키징하는 흐름도를 예증한다.
도 2a 내지 2f는 본 발명의 일부 실시예에 따라 다양한 제조 스테이지들에서 패키징된 반도체 장치의 단면도를 예증한다.
하기의 개시는 본 발명의 상이한 특징부들을 구현하기 위한 다수의 상이한 실시예들 또는 예시들을 제공한다. 컴포넌트 및 배열의 특정 예는 본 발명을 단순화하도록 이하에서 설명된다. 물론, 이것들은 단지 예시이고, 제한하는 것으로 의도되지 않는다. 예를 들면, 이하의 설명에서 제2 특징부 위에 또는 제2 특징부 상에 제1 특징부의 형성은, 제1 및 제2 특징부들이 직접 접촉해서 형성되는 실시예를 포함하고, 추가적인 특징부가 제1 및 제2 특징부 사이에 형성될 수 있어서 제1 및 제2 특징부가 직접 접촉될 수 없는 실시예를 또한 포함할 수 있다. 또한, 본 발명 개시는 다양한 예시들에서 참조 번호들 및/또는 문자들을 반복할 수 있다. 이 반복은 간략함과 명료함을 위한 것이고, 논의되는 다양한 실시예들 및/또는 구성들 사이의 관계를 본질적으로 지시하지는 않는다.
또한, "밑에", "아래에", "더 낮은", "위에", "상부에" 등과 같은 공간적으로 상대적인 용어들은 도면들에서 예증되는 바와 같이 하나의 요소 또는 특징부와 다른 요소(들) 또는 특징부(들)간의 관계를 설명하도록 설명의 용이함을 위해 본 명세서에서 이용될 수 있다. 공간적으로 상대적인 용어들은 도면들에서 묘사된 방위에 추가적으로, 사용 또는 동작 중인 장치의 상이한 방위들을 포괄하도록 의도된다. 장치는 이와는 다르게 지향될(90도 또는 다른 방위로 회전됨) 수 있고, 본 명세서에서 이용되는 공간적으로 상대적인 설명자는 이에 따라 마찬가지로 해석될 수 있다.
도 1을 참조하면, 반도체 장치(칩)를 패키징하는 방법(100)의 흐름도가 본 발명 개시의 다양한 양상에 따라 예증된다. 방법(100)은 단순히 예이고, 본 발명 개시를 제한하는 것으로 의도되지 않는다. 방법(100) 이전에, 그 동안에, 그리고 그 이후에 추가적인 동작들이 제공될 수 있으며, 방법의 추가적인 실시예들에 대하여 설명된 일부 동작들이 대체, 제거, 또는 여기저기로 이동될 수 있다. 방법(100)은 다양한 제조 단계에서 반도체 칩의 일부를 단면도로 예증하는 도 2a 내지 도 2f와 함께 이하에서 설명된다. 칩은 SRAM 및/또는 다른 논리 회로, 저항기, 커패시터 및 인덕터와 같은 수동 컴포넌트, 및 p형 FET(PFET), n형 FET(NFET), FinFET, 금속 산화물 반도체 전계 효과 트랜지스터(MOSFET), 상보형 금속 산화물 반도체(CMOS) 트랜지스터, 바이폴라 트랜지스터, 고전압 트랜지스터, 고주파수 트랜지스터, 다른 메모리 셀, 및 이들의 조합과 같은 능동 컴포넌트를 포함한, IC의 처리 및/또는 패키징 중에 제조된 중간 장치 또는 그 일부일 수 있다.
방법(100)은 패키지 기판(200)을 제공하는 단계(102)에서 시작하고, 도 2a에 도시된 바와 같이 장치 기판(202)을 패키지 기판(200)에 연결시키는 단계(104)에서 계속된다. 일부 실시예에서, 패키지 기판(200)은, 이하에서 논의되는 바와 같이, 장치 기판(202)을 위한 실제 영역(real estate)을 제공하도록 동작가능한 다양한 방식들에서 구현될 수 있다. 예를 들면, 패키지 기판(200)은 다이 리드 프레임, 인쇄회로기판(printed circuit board; PCB), 다중 칩 패키지 기판 또는 다른 유형의 기판을 포함할 수 있다.
도 2a를 여전히 참조하면, 장치 기판(202)은 트랜지스터, 전기적으로 프로그래밍가능 판독 전용 메모리(electrically programmable read only memory; EPROM) 셀, 전기적으로 소거가능한 프로그래밍가능 판독 전용 메모리(electrically erasable programmable read only memory; EEPROM) 셀, 정적 랜덤 액세스 메모리(static random access memory; SRAM) 셀, 동적 랜덤 액세스 메모리(dynamic random access memory ; DRAM) 셀, 다른 마이크로전자 장치들과 같은 하나 이상의 마이크로전자/나노전자 장치들을 포함할 수 있으며, 이 장치들은 하나 이상의 집적 회로들을 형성하도록 상호연결될 수 있다. 장치 기판(202)은, 하나 이상의 종래의 또는 장차 개발될 마이크로전자/나노전자 장치들이 위에 또는 내부에 형성될 수 있는 하나 이상의 기판들을 고려한다. 장치 기판(202) 및/또는 패키지 기판(200)의 벌크는 실리콘-온-인슐레이터(silicon-on-insulator; SOI) 기판 및/또는 실리콘, 갈륨 비화물, 변형된 실리콘, 실리콘 게르마늄, 탄화물, 다이아몬드 및 다른 물질들일 수 있다.
도 2a의 예증된 실시예에서, 장치 기판(202)은 하나 이상의 솔더 범프들을 포함할 수 있다. 도시된 바와 같이, 장치 기판(202)은 장치 기판(202)의 표면(202a)에 고정된 솔더 범프들(204, 206, 및 208)을 포함한다. 비록 도 2a의 예증된 실시예에서, 솔더 범프들(204, 206, 및 208)이 구(sphere) 기반의 형상이지만, 연결시키기 위해 적절한 다양한 형상들의 커넥터가 솔더 범프들 중 하나로서 사용될 수 있으며 본 발명의 개시의 범위 내에 여전히 속한다. 또한, 장치 기판(202)의 이러한 표면(202a)은 위에서 논의된 마이크로전자/나노전자 장치들을 포함할 수 있다. 즉, 솔더 범프들(204, 206, 및 208)은 마이크로전자/나노전자 장치들에 (전기적으로) 연결될 수 있다. 이러한 장치 기판(202)은 솔더 범프(들)을 패키지 기판에 노출시키는 것을 가능케 하도록 위아래가 뒤집어지므로(수직으로 180도 회전됨), 장치 기판(202)과 솔더 범프들(202, 204, 및 208)의 조합은 플립 칩으로서 일반적으로 지칭된다. 즉, 장치 기판(202)이 뒤집혀졌으므로, 표면(202a)은 장치 기판(202)의 상단 표면이라고 또한 지칭된다.
패키지 기판(200)은 패키지 기판(200)과 장치 기판(202) 사이의 연결을 제공하도록 구성된 적어도 하나의 접촉 패드를 더 포함할 수 있다. 보다 구체적으로, 패키지 기판(200)의 접촉 패드들 각각은 장치 기판의 각 솔더 범프와 정렬될 수 있어서, 장치 기판(202)이 요구되는 방식으로 패키지 기판(200)에 연결된다.
방법(100)은 장치 기판(202)의 표면(202b) 위에 계면층(210)을 퇴적하는 동작(106)에서 계속된다. 장치 기판(202)이 뒤집혀졌으므로, 표면(202b)은 장치 기판(202)의 하단 표면이라고 또한 지칭된다. 일부 실시예에서, 계면층(210)은 두 개의 연결된 층들을 위한 계면을 제공하고, 두 개의 연결된 층들을 추가적으로 본딩하도록 구성된다. 예를 들면, 계면층(210)은, 장치 기판(202)로부터 계면층(210)의 반대쪽에 있는 열 확산기(예를 들면, 도 2c와 관련해서 제약층(220))와 장치 기판(202)을 본딩한다. 계면층(210)은 또한, 장치 기판(202)의 표면(202b)으로부터 열 확산기(예를 들면, 도 2c와 관련해서 제약층(220))에 열 에너지를 효율적으로 전달하도록 구성될 수 있다. 따라서, 연결된 층들을 본딩하고, 한 쪽에서 다른 쪽으로 열 에너지를 전달할 수 있는 임의의 유형의 물질들이 계면층(210)에 의해 사용될 수 있다. 예를 들면, 계면층(210)은 전도 페이스트, 그리스(grease), 상변화 물질(phase change material; PCM), 열 패드, 및/또는 열 막을 포함할 수 있다.
방법(100)은 패키지 기판(200) 위에 개구(219)를 포함하는 제약층(220)을 퇴적하는 동작(108)에서 계속된다. 제약층(220)은 패키지 기판(200)의 상단 표면을 둘러싸기 위해 사용된다. 일부 실시예에서, 패키징된 장치가 사용 중일 때, 열 사이클링 동안, 패키징된 장치(예를 들면, 패키지 기판(200), 장치 기판(202), 및 제약층(220))에 대해 제약을 제공하도록, 제약층(220)은 높은 탄성율과 중간 열 확장 계수(예를 들면, 약 18 ppm/℃ 내지 약 26 ppm/℃ 범위임)를 포함할 수 있다. 보다 구체적으로, 열 사이클링(들) 동안에, 제약층(220)은, 계면층(210)을 통해 전달된 열을 소멸시키도록 동작가능한 열-소멸층으로서 작용할 수 있다. 따라서, 제약층(220)은 열 싱크 또는 열 확산기라고 통상 지칭된다. 특정 실시예에서, 제약층(220)은 니켈로 코팅된 구리로 제조되고, 예를 들면, 구리 알루미나이드와 니켈 알루미나이드와 같은 다양한 적절한 금속/2종 이상의 금속 물질들이 사용될 수 있다. 비록 본 발명 개시의 제약층(220)이 약 0.5 밀리미터 내지 2 밀리미터 사이의 범위의 두께로 제한되지만, 요구되는 제약 및 열 소멸을 제공할 수 있는 두께의 임의의 값이 사용될 수 있고, 본 발명 개시의 범위 내에 여전히 있게 될 것이다.
도 2c를 여전히 참조하면, 예증된 실시예에서, 제약층(220)은 캐비티(221)와 통해 있는 적어도 하나의 개구(예를 들면, 219)를 포함할 수 있다. 개구(219)는 예를 들면, 레이저 드릴링 방법, 기계적 드릴링 방법, 및/또는 화학적 에칭 방법과 같은, 개구를 제공하기 위한 다양한 적절한 방법을 통해 형성될 수 있다. 제약층의 이러한 개구는 이하에서 보다 상세히 설명된 바와 같이 몰딩 물질이 개구(219)를 통해 그리고 캐비티(221) 내로 흐르게 하도록 구성된다. 비록 일부 특정 실시예에서, 개구(219)가 동작(108) 동안 형성되지만(즉, 개구는 제약층(220)을 퇴적시키기 전에 쉽게 형성됨), 개구(219)는 분리된 개별적인 동작에서 형성될 수 있다. 예를 들면, 방법(100)은 동작(108) 이전 또는 이후에 수행될 수 있는 위에서 논의된 바와 같은 개구를 제공하는 선택적 동작(미도시됨)을 포함할 수 있다.
방법(100)은 캐비티(221)를 몰딩 물질(230)로 채우는 동작(110)에서 계속된다. 도시된 바와 같이, 캐비티(221)는 패키지 기판(200), 장치 기판(202), 솔더 범프(204 내지 208), 계면층(210), 및 제약층(220)에 의해 규정된다. 일부 실시예에서, 몰딩 물질은, 장치 기판(202)을 굽힘 손상/응력으로부터 추가적으로 보호하도록 패키징된 장치를 강화(stiffen)시키는 고 인장 계수를 포함한다. 이러한 몰딩 물질은 예를 들면, 에폭시 폴리머, 수지 물질 등일 수 있다.
도 2e를 참조하면, 방법(100)은 몰징 물질(230)을 경화(231)시키는 동작(112)으로 진행한다. 일부 실시예에서, 경화(231)는, 몰딩 물질(230)을 경화(harden)시키도록 약 100 ℃ 내지 180 ℃ 범위의 온도로 몰딩 물질을 가열하는 것을 포함할 수 있다.
도 2f를 참조하면, 방법(100)은, 패키지 기판(200)의 하단 표면에 고정되는 복수의 솔더 범프들(252, 254, 및 256)을 통해 패키지 기판(200)이 추가적인 패키지 기판(280)에 연결되는 동작(114)으로 진행한다. 패키지 기판(200)의 이러한 하단 표면은 결합된 플립 칩(즉, 장치 기판(202)과 솔더 범프(204 내지 208))으로부터 패키지 기판(200)에 대향한다. 추가적 패키지 기판(280)은 다이 리드 프레임, 인쇄회로기판(printed circuit board; PCB), 다중 칩 패키지 기판 또는 다른 유형의 기판을 포함할 수 있다.
전술한 논의를 기초로, 본 발명 개시가 다양한 이점을 제공한다는 것을 알 수 있다. 그러나, 모든 장점이 필수적으로 여기에 논의되지는 않으며 다른 실시예들은 상이한 장점들을 제공할 수 있고 모든 실시예에 대해 특정 장점이 요구되는 것은 아님을 알 것이다.
본 발명 개시가 제공하는 이점들 중 하나는 IC 칩을 패키징하는 신규한 방식을 제공한다. 위에서 논의된 바와 같이, 본 발명의 개시된 방법 및 시스템을 사용함으로써, 제약층은 패키징된 IC 칩 전체를 위한 제약을 제공할 뿐만 아니라 열-소멸층으로서 또한 기능할 수 있다. 또한, 제약층의 개구를 사용해서, 패키징된 IC 칩 내의 갭에 존재하는 임의의 가능한 습기 및/또는 공기를 배출하기 위해 사용될 수 있다. 또한, 패키지 기판을 둘러싸기 위해 (개구와 함께) 개시된 제약층을 퇴적시킴으로써, 몰딩 물질이 패키징된 IC 칩 내의 갭을 채울 수 있고, 경화된 후에, 물딩 물질은 장치 기판 및 연결된 솔더 범프에 강성(stiffness) 및/또는 보호를 추가적으로 제공할 수 있다.
본 발명 개시는 장치 기판을 패키징하기 위한 방법을 제공한다. 보다 구체적으로, 본 방법은 패키지 기판을 제공하는 단계; 장치 기판을 패키지 기판에 연결하는 단계; 패키지 기판 및 장치 기판 위에 개구를 포함하는 제약층 - 제약층과 패키지 기판 사이에 캐비티가 규정됨 -; 및 제약층의 개구를 통해 몰딩 물질로 캐비티를 채우는 단계를 포함한다.
본 발명 개시는 장치 기판을 패키징하기 위한 방법을 제공한다. 보다 구체적으로, 본 발명은 장치 기판을 패키지 기판에 연결하는 단계; 금속 층을 장치 및 패키지 기판 - 금속층과 패키지 기판 사이에 캐비티가 규정됨 - 위에 형성하는 단계; 금속층 내에 개구 - 개구는 캐비티와 교통함 - 를 형성하는 단계; 및 몰딩 물질을 개구를 통해 캐비티 내에 형성하는 단계를 포함한다.
본 발명 개시는 집적회로(integrated circuit; IC) 패키지를 제공한다. IC 패키지는 제1 기판; 제1 기판 위에 배치된 제2 기판; 제1 및 제2 기판을 전기적으로 연결시키도록 제1 및 제2 기판 사이에 배치된 복수의 솔더 범프들; 제약층과 제1 기판 사이에 캐비티가 형성되도록 제1 및 제2 기판 위에 배치된 제약층; 및 캐비티 내에 배치되고 제약층을 통해 연장하는 몰딩 물질을 포함한다. 제약층은 상단 표면 및 대향하는 하단 표면을 구비하고, 몰딩 물질은 제약층의 상단 표면으로부터 하단 표면으로 연장한다.
전술된 설명은, 당업자가 본 발명 개시의 양상을 더 잘 이해할 수 있도록 다수의 실시예의 특징을 서술한다. 당업자는, 자신이 본 명세서에서 소개된 실시예의 동일한 목적을 수행하고/수행하거나 동일한 이점을 달성하기 위한 다른 프로세스와 구조체를 설계하기 위한 기초로서 본 발명 개시를 쉽게 이용할 수 있다는 것을 인식해야 한다. 당업자는, 이러한 등가의 구성이 본 발명 개시의 정신과 범위를 이탈하지 않고, 자신이 본 발명 개시의 정신과 범위를 이탈하지 않고 본 명세서의 다양한 변화, 대체, 및 교체를 할 수 있다는 것을 또한 인식해야 한다.
Claims (10)
- 방법에 있어서,
패키지 기판을 제공하는 단계;
장치 기판을 상기 패키지 기판에 연결하는 단계;
상기 패키지 기판과 상기 장치 기판 위에 개구를 포함하는 제약층을 형성하는 단계로서, 상기 제약층과 상기 패키지 기판 사이에 캐비티가 규정되는 것인, 상기 제약층 형성 단계; 및
상기 제약층의 개구를 통해 몰딩 물질로 상기 캐비티를 채우는 단계
를 포함하는, 방법. - 제1항에 있어서, 상기 장치 기판을 상기 패키지 기판에 연결하는 단계는 상기 장치 기판의 하단 표면 상에 고정(secure)되는 적어도 하나의 커넥터를 상기 패키지 기판에 본딩하는 단계를 포함하는 것인, 방법.
- 제2항에 있어서, 상기 장치 기판의 하단 표면은 상기 적어도 하나의 커넥터에 연결된 적어도 하나의 마이크로전자 요소 또는 나노전자 요소를 포함하는 것인, 방법.
- 제1항에 있어서, 상기 장치 기판과 상기 제약층 사이에 계면층을 퇴적시키는 단계를 더 포함하는 것인, 방법.
- 제4항에 있어서, 상기 계면층은 상기 장치 기판과 상기 제약층을 본딩하도록 구성되는 것인, 방법.
- 제1항에 있어서, 상기 몰딩 물질은 수지 물질과 폴리머 중 적어도 하나를 포함하는 것인, 방법.
- 제1항에 있어서, 100 ℃ 내지 180 ℃ 범위의 온도로 상기 캐비티를 채우는 상기 몰딩 물질을 경화시키는 단계를 더 포함하는 것인, 방법.
- 제1항에 있어서, 상기 몰딩 물질로 상기 캐비티를 채우는 단계 후에, 적어도 하나의 커넥터를 상기 패키지 기판의 하단 표면에 연결하는 단계를 더 포함하고, 상기 하단 표면은 상기 장치 기판과 상기 패키지 기판의 반대편에(opposite) 있는 것인, 방법.
- 방법에 있어서,
장치 기판을 패키지 기판에 연결하는 단계;
상기 장치 기판 및 상기 패키지 기판 위에 개구를 구비하는 금속층을 형성하는 단계로서, 상기 금속층과 상기 패키지 기판 사이에 캐비티가 규정되는 것인, 상기 금속층 형성 단계; 및
상기 개구를 통해 상기 캐비티 내에 몰딩 물질을 형성하는 단계
를 포함하는 방법. - 집적회로(integrated circuit; IC) 패키지에 있어서,
제1 기판;
상기 제1 기판 위에 배치된 제2 기판;
상기 제1 기판 및 상기 제2 기판을 전기적으로 연결시키도록 상기 제1 기판 및 상기 제2 기판 사이에 배치된 복수의 커넥터들;
제약층과 상기 제1 기판 사이에 캐비티가 형성되도록 상기 제1 기판 및 상기 제2 기판 위에 배치된 상기 제약층; 및
상기 캐비티 내에 배치되고 상기 제약층을 통해 연장하는 몰딩 물질
을 포함하고,
상기 제약층은 상단 표면 및 대향하는 하단 표면을 구비하고, 상기 몰딩 물질은 상기 제약층의 상단 표면으로부터 하단 표면으로 연장하는 것인, 집적회로(IC) 패키지.
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EP3439028A1 (de) | 2017-08-03 | 2019-02-06 | Siemens Aktiengesellschaft | Leistungsmodul mit mindestens einem leistungshalbleiter |
CN109920787B (zh) * | 2017-12-12 | 2021-05-25 | 中芯国际集成电路制造(北京)有限公司 | 互连结构的设计方法、装置及制造方法 |
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JP2991172B2 (ja) * | 1997-10-24 | 1999-12-20 | 日本電気株式会社 | 半導体装置 |
US6091603A (en) * | 1999-09-30 | 2000-07-18 | International Business Machines Corporation | Customizable lid for improved thermal performance of modules using flip chips |
JP4630449B2 (ja) | 2000-11-16 | 2011-02-09 | Towa株式会社 | 半導体装置及びその製造方法 |
CN100380636C (zh) * | 2002-09-30 | 2008-04-09 | 先进互连技术有限公司 | 用于整体成型组件的热增强封装及其制造方法 |
US20070023769A1 (en) | 2003-09-16 | 2007-02-01 | Keiji Nishimoto | Led lighting source and led lighting apparatus |
CN100589226C (zh) | 2004-04-15 | 2010-02-10 | 泽斯吸气剂公司 | 用于真空或者不活泼气体封装的led的集成的吸气剂 |
CN1855450A (zh) * | 2005-04-25 | 2006-11-01 | 矽品精密工业股份有限公司 | 高散热性的半导体封装件及其制法 |
CN101101880A (zh) * | 2006-07-03 | 2008-01-09 | 矽品精密工业股份有限公司 | 散热型封装结构及其制法 |
CN101174599A (zh) * | 2006-10-30 | 2008-05-07 | 松下电器产业株式会社 | 半导体器件和半导体器件的制造方法 |
KR101086964B1 (ko) | 2009-06-09 | 2011-11-29 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지의 제조 방법 |
TWI590394B (zh) * | 2011-03-10 | 2017-07-01 | 住友電木股份有限公司 | 半導體裝置之製造方法 |
GB2489100A (en) * | 2011-03-16 | 2012-09-19 | Validity Sensors Inc | Wafer-level packaging for a fingerprint sensor |
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US9666556B2 (en) | 2017-05-30 |
CN106298549A (zh) | 2017-01-04 |
TW201701370A (zh) | 2017-01-01 |
CN106298549B (zh) | 2021-05-11 |
TWI597787B (zh) | 2017-09-01 |
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