CN104867909B - 用于有源装置的嵌入式管芯再分布层 - Google Patents

用于有源装置的嵌入式管芯再分布层 Download PDF

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CN104867909B
CN104867909B CN201510086501.0A CN201510086501A CN104867909B CN 104867909 B CN104867909 B CN 104867909B CN 201510086501 A CN201510086501 A CN 201510086501A CN 104867909 B CN104867909 B CN 104867909B
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substrate
integrated circuit
redistribution layer
embedded
package
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CN104867909A (zh
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刘凯
K·纳加拉坚
S·马德
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Maxim Integrated Products Inc
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Abstract

本发明描述了嵌入式集成电路封装件，其包括：基板组件；嵌入在所述基板组件内的集成电路管芯；至少一个基板再分布层，其为下述至少之一：与所述嵌入式集成电路管芯的表面接触、或间接结合到所述嵌入式集成电路管芯的表面上；和与所述基板再分布层接触的过孔。其采用一个或多个基板再分布层(RDL)来布局电极节点和/或用于电流再分布。集成电路管芯被嵌入到铜芯基板中。基板RDL接触嵌入式管芯的表面，其中至少一个过孔(例如热过孔)与基板RDL接触以在嵌入式管芯和外部触头之间提供电互连。附加的基板RDL或WLP RDL可以被包含到封装件中以在嵌入式管芯和外部触头之间提供变化的电流分布。本发明还描述了一种电子装置。

Description

用于有源装置的嵌入式管芯再分布层
相关申请的交叉引用
本申请要求享有2014年2月21日提交的题为“EMBEDDED DIE REDISTRIBUTIONLAYERS FOR ACTIVE DEVICE”的美国临时申请No.61/942,845的权益。美国临时申请No.61/942,845以其整体通过引用被包含在本文中。
背景技术
消费性电子装置，特别是诸如智能手机、平板电脑等移动电子装置越来越多地采用更小、更紧凑的部件来为其使用者提供所需的特征。这些装置通常采用三维集成电路装置(3D IC)。三维集成电路装置是采用两层或更多层有源电子部件的半导体装置。穿透基板的过孔(through-substrate via，TSV)将装置的不同层(例如，不同基板)上的电子部件互连，从而允许装置被竖直和水平地集成。因此，三维集成电路装置可以在比传统二维集成电路装置更小、更紧凑的占用区域内提供增加的功能。
半导体装置的制造中使用的传统制造方法采用显微光刻法将集成电路图案化到由诸如硅、砷化镓等半导体形成的圆晶片上。通常，图案化的晶片被分割成单独的集成电路芯片或管芯，以将各集成电路彼此分开。各单独的集成电路芯片使用多种封装技术被组装或封装，以形成可以安装到印刷电路板或其它基板上的半导体装置。
发明内容
描述了采用一个或多个基板再分布层(RDL)来布局电极节点和/或用于电流再分布的嵌入式管芯封装件。在一或多个实现方式中，集成电路管芯被嵌入到基板中。基板RDL为下述至少之一：与嵌入式集成电路管芯的表面接触、或间接结合到嵌入式集成电路管芯的表面上，其中至少一个过孔(例如，热过孔)与基板RDL接触以提供电互连。附加的基板RDL或WLP RDL可以被包含到封装件中以在嵌入式管芯和外部触头之间提供变化的电流分布。
根据本发明的一个方面，一种嵌入式集成电路封装件，其包括：基板组件；嵌入在所述基板组件内的集成电路管芯；至少一个基板再分布层，其为下述至少之一：与所述嵌入式集成电路管芯的表面接触、或间接结合到所述嵌入式集成电路管芯的表面上；和与所述基板再分布层接触的过孔。
可选地，所述基板组件包括铜基板。
可选地，所述至少一个基板再分布层与所述嵌入式集成电路管芯的表面接触。
可选地，所述嵌入式集成电路封装件不含焊料球互连件。
可选地，所述嵌入式集成电路封装件还包括：结合到所述嵌入式集成电路管芯的表面上的晶片级封装再分布层，其中所述至少一个基板再分布层通过至少一个过孔被间接地结合到所述嵌入式集成电路管芯的表面上。
可选地，所述晶片级封装再分布层比所述至少一个基板再分布层薄。
可选地，所述至少一个基板再分布层包括与所述嵌入式集成电路管芯的表面接触的第一基板再分布层，并包括通过至少一个过孔可操作地结合到所述第一基板再分布层上的第二基板再分布层。
可选地，所述嵌入式集成电路封装件，还包括：结合到所述基板组件上的散热器组件。
根据本发明的另一方面，一种电子装置，其包括：印刷电路板；和结合到所述印刷电路板上的嵌入式集成电路封装件，所述嵌入式集成电路封装件包括：
基板组件；嵌入在所述基板组件内的集成电路管芯；至少一个基板再分布层，其为下述至少之一：与所述嵌入式集成电路管芯的表面接触、或间接结合到所述嵌入式集成电路管芯的表面上；和与所述基板再分布层接触的过孔。
可选地，所述基板组件包括铜基板。
可选地，所述至少一个基板再分布层与所述嵌入式集成电路管芯的表面接触。
可选地，所述嵌入式集成电路封装件不含焊料球互连件。
可选地，所述嵌入式集成电路封装件还包括：结合到所述嵌入式集成电路管芯的表面上的晶片级封装再分布层，其中所述至少一个基板再分布层通过至少一个过孔被间接地结合到所述嵌入式集成电路管芯的表面上。
可选地，所述晶片级封装再分布层比所述至少一个基板再分布层薄。
可选地，所述至少一个基板再分布层包括与所述嵌入式集成电路管芯的表面接触的第一基板再分布层，并包括通过至少一个过孔可操作地结合到所述第一基板再分布层上的第二基板再分布层。
可选地，所述电子装置还包括：结合到所述基板组件上的散热器组件。
根据本发明的又一方面，一种嵌入式集成电路封装件，其包括：第一再分布层，其形成多个伸出部，所述多个伸出部中的每个包括一个或多个嵌入式电路封装件，所述一个或多个嵌入式电路封装件具有与嵌入式管芯可操作地结合的一个或多个过孔；第二再分布层，其形成第二多个伸出部，所述第二多个伸出部中的每个包括一个或多个嵌入式电路封装件，所述一个或多个嵌入式电路封装件具有与嵌入式管芯可操作地结合的一个或多个过孔；其中第一再分布层的所述多个伸出部中的一个或多个被定位成邻近所述第二多个伸出部的相应部分中的一个或多个。
可选地，所述嵌入式集成电路封装件还包括：一个或多个长条过孔，其被定位在所述第一再分布层和所述第二再分布层中的一个或多个的表面上，所述一个或多个长条过孔中的每个连接所述一个或多个过孔中的至少两个。
可选地，所述多个伸出部的各部分相对于所述第二多个伸出部的各部分以交错构造进行布置。
可选地，所述第一再分布层和所述第二再分布层中的一个或多个包括外露的焊垫部分，所述外露的焊垫部分露出到所述封装件的外部。
本发明内容被提供以便以简化形式介绍下文在具体实施方式中进一步描述的概念的精选者。本发明内容并不打算用来标识所要求保护的主题的关键特征或必要特征，也不打算用来帮助确定所要求保护的主题的范围。
附图说明
详细说明将参照附图进行描述。说明书和附图的不同实例中可以使用相同的附图标记表示相似或相同的项目。
图1是示出了根据本发明实施例的具有基板再分布层的嵌入式集成电路封装件的示意剖视图。
图2是示出了根据本发明实施例的具有基板再分布层和晶片级封装再分布层的嵌入式集成电路封装件的示意剖视图。
图3是示出了根据本发明实施例的具有基板再分布层的多个层的嵌入式集成电路封装件的示意剖视图。
图4是示出了根据本发明实施例的结合到外部散热器的图1的嵌入式集成电路封装件的示意剖视图。
图5是根据本发明实施例的嵌入式集成电路封装件的布局构造的示意俯视图。
图6是图5的布局构造的示意俯视图，具有分布在根据本发明实施例的封装件的表面上的长条过孔。
具体实施方式
概述
封装技术，例如包含引线框封装的封装技术，被用来将电路装置与封装件集成，以便于该集成电路与外部电触头(例如，印刷电路板(PCB)的电触头)相接。例如，晶片级封装(WLP)可以与晶片凸点技术一起利用来提供IC装置，由此IC装置的取向被翻转到引线框或基板上来产生封装件。在封装件组装期间，焊料连接件(例如，焊料球或凸块)可用来使IC装置的电连接器和引线框或基板匹配。然而，这样的构造可能由于使用焊料合金作为互连件而引起电迁移有关的故障，可能引起灵活性和可布局的设计能力问题，可能引起板级可靠性问题，并且可能需要相对厚的外形因子，从而增加了产品封装件的整体尺寸。
因此，描述了采用一个或多个基板再分布层来布局电极节点和/或用于电流再分布的嵌入式集成电路装置。在一个或多个实现方式中，没有焊料被用在嵌入式集成电路装置的封装组件和结构中，从而产生具有高效率和灵活的封装设计的相对薄的封装件(例如，小外形因子)。在一个或多个实现方式中，集成电路管芯被嵌入到铜芯基板中。基板再分布层(RDL)接触嵌入式管芯的表面，其中至少一个过孔(例如，热过孔)与基板RDL接触以在嵌入式管芯和外部触头之间提供电互连。管芯的表面的至少一部分可包括对管芯的一部分提供电绝缘和/或保护的钝化层。附加的基板RDL或WLP RDL可以被包含到封装件中以在嵌入式管芯和外部触头之间提供变化的电流分布。
实施例
图1示出根据本发明实施例的嵌入式集成电路封装件100。如图所示，嵌入集成电路封装件100包括嵌入到基板104中的有源集成电路芯片(或管芯)102。在一个或多个实现方式中，基板104包括铜芯基板，但也可以使用替代的或附加的材料，包括但不限于，硅或其它印刷电路板(PCB)材料，等等。例如，基板104可以由铜芯片材制成。在一个或多个实现方式中，嵌入式集成电路封装件100被集成为场效应晶体管(FET)，诸如横向扩散的高功率场效应晶体管(LSMOS-FET)。
嵌入式管芯102可经由粘合材料106被附着到基板104。在一个实现方式中，用来将嵌入式管芯102附着到基板104上的粘合材料106是管芯贴装膜(DAF)。在加工过程中DAF可以在将管芯102从其晶片单片化之前被附着到管芯102上，由此DAF和管芯102随后作为一个单元附着到基板104上。封装件100可包括分布在基板104上在管芯102上面的层压材料108(例如，电介质材料、基于玻璃的材料、透明材料、环氧树脂，等等)。由于管芯102被嵌入在基板104中，所以封装件100可以免于模制(例如，可以不需要模制的结构支撑来相对于基板固定管芯的位置)和/或不含焊料球连接件(由于基板RDL(一个或多个)在嵌入式管芯和基板/封装件的表面之间提供了必要的电连接)，这可提供相对薄的封装件100。例如，封装件100可具有从大约0.4mm(毫米)到大约0.5mm(毫米)的厚度，而传统的封装件可以为大约0.7mm(毫米)和更大。
可以在封装件100内的管芯102的至少一侧上形成钝化层110。钝化层110可以包括电绝缘体，其用作用于管芯102和/或封装件100的其它部件的绝缘体和/或保护层，保护其不受后面的制造步骤和环境因素的影响。在一种实现方式中，钝化层110可以包括形成在管芯102的顶面上而不覆盖管芯102的触垫的一层二氧化硅(SiO2)。在另一实现方式中，并取决于制造工艺，钝化层110可包括阻焊层。在其它实现方式中，钝化层110还可以包括薄膜(例如，苯并环丁烯(BCB)等)。
封装件100还包括形成在封装件100内的一个或多个基板再分布层(RDL)112。通常，基板RDL可以为比常规的晶片级封装(WLP)RDL厚的材料，因此可以提供具有与纯粹利用WLP RDL(一个或多个)的封装件相比改进的电流处理能力的封装件。例如，在一个或多个实现方式中，可以使用20微米厚的基板RDL。如图1所示，封装件100包括在嵌入式管芯102和外部触头之间提供电互连的一个基板RDL 112。在一个或多个实现方式中，通过钻入(例如，激光钻孔)层压材料108中并且在封装件100内在管芯102的表面的至少一部分上沉积镀铜(并且也可以接触钝化层110的一部分)而形成基板RDL 112。该封装件包括与基板RDL 112接触的一个或多个过孔(例如，热过孔)114。例如，过孔114可以形成为从封装件100的表面116开始并延续到管芯102的一部分上。封装件100的表面可以包括定位在过孔114之间以限定所露出的基板(例如，在封装件100的表面上露出的铜)的图案的阻焊层材料118。虽然图1显示了具有一个基板RDL的封装件100，但是可以预期的是，RDL的其它/附加构造可被用在封装件100内，如下所述。此外，虽然本文描述的封装件显示了单一嵌入式管芯，但是在一个或多个实现方式中，封装件也可以包括嵌入在基板内的多个(例如，两个或更多个)嵌入式管芯。在封装件包括多个嵌入式管芯的情况下，管芯可以电连接至封装件内的一个或多个其它管芯。通过利用多个管芯，管芯中的一个或多个可以在功能、尺寸、构造等方面不同于其它各管芯。
现在参考图2，根据本发明实施例的具有两层再分布层的嵌入式集成电路封装件200被示出。如图所示，封装件200包括基板RDL 112和晶片级封装(WLP)RDL 202，其可以包括用于使节距设计不同的节点灵活性。与图1的封装件100类似，封装件200可以包括一个或多个嵌入式管芯102、基板104、粘合材料106、层压材料108、钝化层110、过孔114和阻焊层118。封装件200还可以包括定位在封装件200的表面116和WLP RDL 202之间的再钝化层204。例如，再钝化层204可以被定位在基板RDL 112和WLP RDL 202之间，使得基板RDL 112形成在再钝化层204上。一个或多个过孔114可以将WLP RDL 202与形成在再钝化层204的顶面206上的基板RDL 112连接。封装件200可以包括与基板RDL 112接触的一个或多个过孔114。例如，过孔114可以形成为从封装件200的表面116开始并延续到定位于再钝化层204的顶面206上的基板RDL 112上。封装件200的表面116可以包括位于过孔114之间的阻焊层材料118。在一个或多个实现方式中，附加的基板层可以被增加以解决用于特定装置设计的功率需求或电流分布。
现在参考图3，根据本发明实施例的具有两层再分布层的嵌入式集成电路封装件300被示出。如图所示，封装件300包括第一基板RDL 112和第二基板RDL 302。与图1的封装件100和/或图2的封装件200类似，封装件300可以包括一个或多个嵌入式管芯102、基板104、粘合材料106、层压材料108、钝化层110、过孔114和阻焊层118。封装件300的第一基板RDL 112可以被定位在管芯102的表面的至少一部分上(并且也可以接触钝化层110的一部分)。第二基板RDL 302可以被定位在第一基板RDL 112和封装件300的表面116之间。一个或多个过孔114可以将第一基板RDL 112与第二基板RDL 302连接。另外，封装件300可以包括与第二基板RDL 302接触的一个或多个过孔114。例如，过孔114可以形成为从封装件300的表面116开始并延续到定位于封装件300的表面116和第一基板RDL 112之间的第二基板RDL302上。封装件300的表面116可以包括位于过孔114之间的阻焊层材料118。在一个或多个实现方式中，附加的基板层可以被增加以解决用于特定装置设计的功率需求或电流分布。
现在参考图4，嵌入式集成电路封装件100被示出为与散热器组件400结合。如图所示，封装件100可通过定位在散热器组件400和封装件100的基板104之间的导热材料402附装至散热器组件400。散热器组件400构造成消散由封装件100产生并通过导热材料402传递到散热器组件400的热量。散热器组件400的设计可取决于封装件100的特性。例如，散热器组件400可以是针翅(pin-fin)式散热器(诸如图4中所示)。在各实现方式中，封装件100的基板104为金属基板(例如，铜芯基板)，在这种情况下直接连接可以形成在基板104和散热器组件400之间。这种直接连接可以由于封装件100和散热器组件400之间有效的传热结构而提供封装件100的增强的热性能。在各实施方式中，导热材料402可以是导热粘合剂，例如热增强型粘合材料(TEAM)。
总体参考图5和6，嵌入式电路封装件可以相对于彼此被定位以形成布局构造，如从俯视图所示。例如，多个过孔114可以从一个或多个封装件的表面116延伸到一个或多个嵌入式集成电路(例如，如图1-4中所示)。这些布局构造可以适用于图1-4中所示的每一个封装结构。在图5和6所示的布局构造中，第一铜RDL 500形成三个伸出部502、504、506，其每一个包括可以直接或间接地连接到嵌入式管芯的多个过孔114。第二铜RDL 508形成三个伸出部510、512和514，其每一个包括可以直接或间接地连接到嵌入式管芯的多个过孔114。用于第一铜RDL 500和第二铜RDL 508中每一个的伸出部可以具有相同或不同的物理特性，包括但不限于，长度、厚度，等。在各实现方式中，第一铜RDL 500的伸出部以交错或错位的方式相对于所述第二铜RDL 508的伸出部布置。例如，第一铜RDL 500的伸出部502被定位成邻近第二铜RDL 508的伸出部510。第二铜RDL 508的伸出部510也被定位成邻近第一铜RDL500的伸出部504。伸出部504也被定位成邻近第二铜RDL 508的伸出部512。各伸出部以交错的方式继续下去。伸出部的其它构造可以被提供，使得不同构造可以提供相关联封装件的不同性能特点。例如，第一铜RDL 500的一个或多个伸出部可以在第二铜RDL 508的伸出部介入前彼此邻近。
一个或多个外露焊垫516可以相对于第一铜RDL 500和第二铜RDL 508中的每一个存在。各铜RDL的其它部分可以例如由阻焊层覆盖。每个伸出部可以连接到外露焊垫516，使得每个伸出部经由外露焊垫516被连接，从而给设计提供了巨大的灵活性。外露焊垫516通常在集成了RDL的封装件的外部可触及。如图6所示，长条过孔可以连接伸出部上的两个或多个过孔114，以便例如提高过孔的电性能。例如，长条过孔600连接伸出部502的每个过孔，而长条过孔602连接伸出部510的每个过孔。此外，本文描述的封装件可以提供总体上灵活的设计能力，例如通过支持球栅阵列(BGA)和栅格阵列(LGA)封装类型。
结论
虽然以专用于结构特征和/或处理操作的语言描述了本发明主题，但是应当理解，在所附权利要求中限定的主题并非必须限于上述具体特征或行为。相反，上述具体特征和行为是作为实施权利要求的示例性形式公开的。

Claims (14)

1.一种嵌入式集成电路封装件，其包括：
基板组件；
嵌入在所述基板组件内的集成电路管芯；
与所述集成电路管芯接触的层压材料；
钝化层，其至少一部分与所述嵌入的集成电路管芯的表面直接接触；
至少一个基板再分布层，其具有与所述嵌入的集成电路管芯的表面直接接触的至少一部分以及与所述钝化层直接接触的至少另一部分，所述至少一个基板再分布层还包括定位在所述层压材料与所述钝化层之间的至少一部分，其中所述钝化层的至少一部分定位在所述嵌入的集成电路管芯的表面与所述至少一个基板再分布层的所述至少另一部分之间，所述嵌入的集成电路管芯的表面与所述层压材料、所述钝化层、以及所述至少一个基板再分布层中的每个直接接触；和
与所述基板再分布层接触的过孔，
所述嵌入式集成电路封装件还包括：
结合到所述嵌入的集成电路管芯的表面上的晶片级封装再分布层，
其中所述至少一个基板再分布层通过至少一个过孔被间接地结合到所述嵌入的集成电路管芯的表面上，其中，所述晶片级封装再分布层比所述至少一个基板再分布层薄。
2.根据权利要求1所述的嵌入式集成电路封装件，其中，所述基板组件包括铜基板。
3.根据权利要求1所述的嵌入式集成电路封装件，其中，所述嵌入式集成电路封装件不含焊料球互连件。
4.根据权利要求1所述的嵌入式集成电路封装件，其中，所述至少一个基板再分布层包括与所述嵌入的集成电路管芯的表面接触的第一基板再分布层，并包括通过至少一个过孔可操作地结合到所述第一基板再分布层上的第二基板再分布层。
5.根据权利要求1所述的嵌入式集成电路封装件，还包括：
结合到所述基板组件上的散热器组件。
6.一种电子装置，其包括：
印刷电路板；和
结合到所述印刷电路板上的且根据权利要求1至5任一所述的嵌入式集成电路封装件，
所述嵌入式集成电路封装件还包括结合到所述嵌入的集成电路管芯的表面上的晶片级封装再分布层，
其中所述至少一个基板再分布层通过至少一个过孔被间接地结合到所述嵌入的集成电路管芯的表面上，其中，所述晶片级封装再分布层比所述至少一个基板再分布层薄。
7.根据权利要求6所述的电子装置，其中，所述基板组件包括铜基板。
8.根据权利要求6所述的电子装置，其中，所述至少一个基板再分布层与所述嵌入的集成电路管芯的表面接触。
9.根据权利要求6所述的电子装置，其中，所述嵌入式集成电路封装件不含焊料球互连件。
10.根据权利要求6所述的电子装置，其中，所述至少一个基板再分布层包括与所述嵌入的集成电路管芯的表面接触的第一基板再分布层，并包括通过至少一个过孔可操作地结合到所述第一基板再分布层上的第二基板再分布层。
11.根据权利要求6所述的电子装置，还包括：
结合到所述基板组件上的散热器组件。
12.一种嵌入式集成电路封装件，其包括：
第一再分布层，其形成多个伸出部，所述多个伸出部中的每个包括一个或多个嵌入式电路封装件，所述一个或多个嵌入式电路封装件具有与嵌入式管芯可操作地结合的一个或多个过孔，其中所述嵌入式电路封装件包含：
基板组件；
嵌入在所述基板组件内的集成电路管芯；
与所述集成电路管芯接触的层压材料；
钝化层，其至少一部分与所述嵌入的集成电路管芯的表面直接接触；
至少一个基板再分布层，其具有与所述嵌入的集成电路管芯的表面直接接触的至少一部分以及与所述钝化层直接接触的至少另一部分，所述至少一个基板再分布层还包括定位在所述层压材料与所述钝化层之间的至少一部分，其中所述钝化层的至少一部分定位在所述嵌入的集成电路管芯的表面与所述至少一个基板再分布层的所述至少另一部分之间，所述嵌入的集成电路管芯的表面与所述层压材料、所述钝化层、以及所述至少一个基板再分布层中的每个直接接触，其中，所述嵌入式集成电路封装件还包括结合到所述嵌入的集成电路管芯的表面上的晶片级封装再分布层，其中所述至少一个基板再分布层通过至少一个过孔被间接地结合到所述嵌入的集成电路管芯的表面上，其中，所述晶片级封装再分布层比所述至少一个基板再分布层薄；以及
第二再分布层，其形成第二多个伸出部，所述第二多个伸出部中的每个包括一个或多个嵌入式电路封装件，所述一个或多个嵌入式电路封装件具有与嵌入式管芯可操作地结合的一个或多个过孔，
其中第一再分布层的所述多个伸出部中的一个或多个被定位成邻近所述第二多个伸出部的相应部分中的一个或多个，并且其中，所述多个伸出部中的各部分以相对于所述第二多个伸出部的相应部分交错的方式布置。
13.根据权利要求12所述的嵌入式集成电路封装件，还包括：
一个或多个长条过孔，其被定位在所述第一再分布层和所述第二再分布层中的一个或多个的表面上，所述一个或多个长条过孔中的每个连接所述一个或多个过孔中的至少两个。
14.根据权利要求12所述的嵌入式集成电路封装件，其中，所述第一再分布层和所述第二再分布层中的一个或多个包括外露的焊垫部分，所述外露的焊垫部分露出到所述封装件的外部。
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