CN106298549A - 倒装芯片封装 - Google Patents

倒装芯片封装 Download PDF

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Publication number
CN106298549A
CN106298549A CN201510743052.2A CN201510743052A CN106298549A CN 106298549 A CN106298549 A CN 106298549A CN 201510743052 A CN201510743052 A CN 201510743052A CN 106298549 A CN106298549 A CN 106298549A
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China
Prior art keywords
substrate
restraint layer
layer
cavity
package substrate
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Granted
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CN201510743052.2A
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CN106298549B (zh
Inventor
刘育志
张建国
游济阳
卢景睿
林志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Abstract

本发明提供一种集成电路(IC)封装件，包括：第一衬底；设置在第一衬底上方的第二衬底；设置在第一与第二衬底之间的多个连接件，以电连接第一与第二衬底；设置在第一和第二衬底上方的约束层，使得在约束层与第一衬底之间形成腔体；以及设置在腔体内并且穿过约束层延伸的模塑材料。约束层具有顶面和相对的底面，并且模塑材料从约束层的顶面延伸至底面。本发明还提供了一种形成集成电路(IC)封装件的方法。

Description

倒装芯片封装
技术领域
本发明总体涉及半导体领域，更具体地，涉及倒装芯片的封装。
背景技术
半导体集成电路(IC)工业经历了快速增长。IC材料和设计的技术进步产生了多代IC，其中，每一代都具有比前一代更小且更复杂的电路。在IC演进过程中，在几何尺寸(即，使用制造工艺可形成的最小组件(或线))减小的同时，功能密度(即，单位芯片面积中的互连器件的数量)已普遍增加。这种按比例缩小的工艺通常通过增加生产效率和降低相关成本来提供很多益处。这样的按比例缩小增大了处理和制造IC的复杂程度。
为了实现IC处理和制造的这些进步，也需要在IC封装中有类似的发展。例如，IC芯片包括形成在诸如半导体晶圆的衬底上的半导体器件，并且包括用于对集成电路提供电接口的金属化的接触件或附接件、焊盘。用于在芯片的内部电路与诸如电路板、其他芯片或晶圆的外部电路之间提供连接的传统技术包括引线接合，其中引线用于将芯片接触焊盘连接至外部电路。已知为倒装芯片封装的较新的芯片连接技术使用沉积在IC芯片的接触焊盘上的焊料凸块将IC芯片连接至外部电路。为了将芯片安装至外部电路(如，衬底)，以倒置方式将芯片翻转并且芯片的接触焊盘与衬底上的匹配的接触焊盘对准。然后底部填充物(在芯片与衬底之间流动的粘合剂)在翻转的芯片与支撑外部电路的衬底之间流动，以完成IC器件与外部电路之间的机械和/或电互连。因为芯片直接放置在外部电路上，使得互连引线可以更短，所以形成的倒装芯片封装件比传统的基于载体的系统小得多。结果，大大降低了电感和电阻发热，使得更高速的器件成为可能。
然而，由于倒装芯片封装件(诸如，例如IC芯片、衬底和底部填充物)的各组件之间固有的热膨胀系数不匹配，所以经常在倒装芯片封装件中诱生封装件高度翘曲和高热应力。这种高热应力和翘曲不仅导致芯片中的低k互连层(各层)的分层，而且还引起焊料凸块破裂，从而导致故障，使得倒装芯片封装件工作的长期可靠性劣化。
发明内容
根据本发明的一个方面，提供了一种方法，包括：提供封装衬底；将器件衬底连接至封装衬底；在封装衬底和器件衬底上方形成包括开口的约束层，其中，在约束层与封装衬底之间限定腔体；以及通过约束层的开口利用模塑材料来填充腔体。
优选地，将器件衬底连接至封装衬底包括将固定在器件衬底的底面上的至少一个连接件接合至封装衬底。
优选地，器件衬底的底面包括连接至至少一个连接件的至少一个微电子和/或纳米电子元件。
优选地，该方法还包括：在器件衬底与约束层之间沉积界面层。
优选地，界面层被配置为将器件衬底与约束层接合。
优选地，模塑材料包括树脂材料和聚合物中的至少一种。
优选地，该方法还包括：在大约100℃至180℃的范围内的温度下，对填充腔体的模塑材料进行固化。
优选地，该方法还包括：在利用模塑材料填充腔体之后，将至少一个连接件连接至封装衬底的底面，其中，底面关于封装衬底与器件衬底相对。
根据本发明的另一方面，提供了一种方法，包括：将器件衬底连接至封装衬底；在器件衬底和封装衬底上方形成具有开口的金属层，其中，在金属层与封装衬底之间限定腔体；以及通过开口在腔体中形成模塑材料。
优选地，该方法还包括：对腔体中的模塑材料进行固化。
优选地，该方法还包括：在器件衬底上直接形成界面层。
优选地，将器件衬底连接至封装衬底包括将器件衬底的顶面上的连接件接合至封装衬底的上表面。
优选地，模塑材料包括树脂材料和聚合物中的至少一种。
优选地，金属层包括介于大约0.3mm至大约3mm范围内的厚度。
根据本发明的又一方面，提供了一种集成电路(IC)封装件，包括：第一衬底；第二衬底，设置在第一衬底上方；多个连接件，设置在第一衬底与第二衬底之间，以电连接第一衬底与第二衬底；约束层，设置在第一衬底和第二衬底上方，使得在约束层与第一衬底之间形成腔体；以及模塑材料，设置在腔体内并且穿过约束层延伸，其中，约束层具有顶面和相对的底面，并且模塑材料从约束层的顶面延伸至底面。
优选地，该封装件还包括：界面层，设置在第二衬底的顶面与约束层的底面之间。
优选地，界面层被配置为将约束层与第二衬底接合。
优选地，模塑材料将穿过约束层的开口流动。
优选地，模塑材料包括由树脂材料和聚合物中的至少一种制成的材料。
优选地，第二衬底的底面包括连接至多个连接件中的至少一个连接件的至少一个微电子和/或纳米电子元件。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各个方面。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1示出了根据本发明的实施例的封装半导体器件的流程图。
图2A至图2F示出了根据本发明的一些实施例的处于各个制造阶段中的封装的半导体器件的截面图。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现所提供主题的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在多个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等空间关系术语以描述如图所示的一个元件或部件与另一元件或部件的关系。除图中所示的方位之外，空间关系术语意欲包括使用或操作过程中的器件的不同的方位。装置可以以其它方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可同样地作相应地解释。
现在参考图1，示出了根据本发明的各个方面的封装半导体器件(芯片)的方法100的流程图。方法100仅是实例，而不意欲限制本发明。可以在方法100之前、期间和之后提供附加的操作，并且对于该方法的附加的实施例，可以取代、省略所述的一些操作或者变换它们的顺序。下面结合图2A至图2F描述方法100，这些图以截面图的形式示出了处于各个制造阶段的半导体芯片的部分。芯片可以是在IC的处理和/或封装期间制造的中间器件或其一部分，该中间器件可以包括：SRAM和/或其他逻辑电路；无源组件，诸如电阻器、电容器和电感器；以及有源组件，诸如p型FET(PFET)、n型FET(NFET)、FinFET、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极型晶体管、高压晶体管、高频晶体管、其他存储器单元和/或它们的组合。
方法100开始于操作102，提供封装衬底200，继续操作104，如图2A所示，将器件衬底202连接至封装衬底200。如下文将讨论的，在一些实施例中，可以以多种方式实现封装衬底200，这些方式对于向器件衬底202提供基板(real estate)是可行的。例如，封装衬底200可以包括管芯引线框架(lead frame)、印刷电路板(PCB)、多芯片封装衬底或其他类型的衬底。
还参考图2A，器件衬底202可以包括一个或多个微电子/纳米电子器件，诸如晶体管、电可编程只读存储器(EPROM)单元、电可擦除可编程只读存储器(EEPROM)单元、静态随机存取存储器(SRAM)单元、动态随机存取存储器(DRAM)单元和其他的微电子器件，可以互连这些器件，以形成一个或多个集成电路。器件衬底202涉及一个或多个衬底，一个或多个传统的或今后开发的微电子/纳米电子器件可以形成在这些衬底上面或内部。器件衬底202和/或封装衬底200的块体(bulk)可以是绝缘体上硅(SOI)衬底和/或可以包括硅、砷化镓、应变硅、硅锗、碳化物、金刚石和其他材料。
在图2A示出的实施例中，器件衬底202可以包括一个或多个焊料凸块。如图所示，器件衬底202包括固定至器件衬底202的表面202a的焊料凸块204、206和208。尽管在图2A示出的实施例中，焊料凸块204、206和208是基于球体的形状，但是具有适用于连接的各种形状的连接件都可以用作一个焊料凸块并且仍落在本发明的范围内。此外，器件衬底202的这种表面202a可以包括以上讨论的微电子/纳米电子器件。就是说，焊料凸块204、206和208可以(电)连接至微电子/纳米电子器件。由于器件衬底202上下倒转(垂直旋转180°)以使得焊料凸块暴露于封装衬底，所以器件衬底202与焊料凸块202、204和208的组合通常称作倒装芯片。就是说，因为器件衬底202倒转，所以也将表面202a称作器件衬底202的顶面。
封装衬底200还可以包括被配置为在封装衬底200与器件衬底202之间提供连接的至少一个接触焊盘。更具体地，封装衬底200的每一个接触焊盘都可以与器件衬底的每一个焊料凸块对准，使得用期望的方式将器件衬底202连接至封装衬底200。
方法100继续操作106，其中，在器件衬底202的表面202b上方沉积界面层210。因为器件衬底202倒转，所以也将表面202b称作器件衬底202的底面。在一些实施例中，界面层210被配置为向两个连接的层提供界面并且进一步接合两个连接的层。例如，界面层210接合器件衬底202与散热器(如，参考图2C的约束(constraint)层220)，该散热器关于界面层210与器件衬底202相对。界面层210还可被配置为将来自器件衬底202的表面202b的热量有效地转移至散热器(如，关于图2C的约束层220)。因此，能够接合连接的各层并且将热量从一层转移至另一层的任何类型的材料都可以用于界面层210。例如，界面层210可以包括：导电胶(paste)、润滑脂、相变材料(PCM)、导热垫片(thermal pad)和/或导热膜。
方法100继续操作108，其中，在封装衬底200上方沉积包括开口219的约束层220。约束层220用于包围封装衬底200的顶面。在一些实施例中，约束层220可以包括高弹性模量和中等热膨胀系数(如，在约18ppm/℃至约26ppm/℃的范围内)，以当封装的器件使用时，在热循环期间对封装的器件(如，封装衬底200、器件衬底202和约束层220)提供抑制。更具体地，在热循环期间，约束层220可以用作散热层，该散热层对于散发经过界面层210传导的热量是可行的。这样，约束层220通常被称作吸热器或散热器。虽然在具体的实施例中，约束层220由涂覆有镍的铜制成，但是可以使用各种合适的金属/金属间化合物(intermetallic material)，诸如，例如铝化铜和铝化镍。尽管本发明的约束层220被限制为厚度在大约0.5mm至2mm的范围之间，但是能够提供期望的抑制和散热的厚度的任意数值都可以采用并且仍然在本发明的范围内。
还参考图2C，在示出的实施例中，约束层220可以包括与腔体221连通的至少一个开口(如，219)。可以通过用于形成开口的各种合适的方法(诸如，例如激光钻孔方法、机械钻孔方法和/或机械蚀刻方法)来形成开口219。如下文更加具体的描述，约束层的这种开口被配置为使模塑材料能够流经开口219并且进入腔体221。尽管在一些具体的实施例中，在操作108期间形成开口219(即，在沉积约束层220之前开口易于形成)，但是可以在独立且单个操作中形成开口219。例如，方法100可以包括可选的操作(未示出)，提供如上所讨论的开口，并且该操作可以在操作108之前或之后执行。
方法100继续操作110，利用模塑材料230填充腔体221。如图所示，通过封装衬底200、器件衬底202、焊料凸块204至208、界面层210、约束层220来限定腔体221。在一些实施例中，模塑材料包括使封装的器件变硬的高强度模量，以进一步保护器件衬底202免受弯曲破坏/应力。例如，这种模塑材料可以是环氧树脂聚合物、树脂材料等。
参考图2E，方法100继续操作112，对模塑材料230进行固化231。在一些实施例中，固化231可以包括将模塑材料加热至大约100℃至180℃的范围内的温度，以硬化模塑材料230。
参考图2F，方法100进行至操作114，其中通过固定至封装衬底200的底面的多个焊料凸块252、254和256将封装衬底200连接至附加的封装衬底280。封装衬底200的该底面关于封装衬底200与连接的倒装芯片(即，器件衬底202和焊料凸块204至208)相对。附加的封装衬底280可以包括管芯引线框架、印刷电路板(PCB)、多芯片封装衬底或其他类型的衬底。
基于以上所讨论的，可以看出，本发明提供了各种优势。然而，应该理解，没必要在本文中论述所有的优势，并且其他实施例可以提供不同的优势，因此并不需要所有的实施例都具有特定的优势。
本发明的一个优势在于，提供了封装IC芯片的新方法。如以上所讨论的，通过使用目前公开的方法和系统，约束层整体不仅对封装的IC芯片提供抑制，而且用作散热层。此外，利用约束层的开口，模塑材料可用于排除可能存在于封装的IC芯片内的空隙中的水分和/或空气。进一步，通过沉积所公开的约束层(具有开口)以包围封装衬底，模塑材料可以填充封装的IC芯片内的空隙，并且在其被固化之后，模塑材料还可以对器件衬底和连接的焊料凸块提供硬度和/或保护。
本发明提供了一种用于封装器件衬底的方法。更具体地，该方法包括：提供封装衬底；将器件衬底连接至封装衬底；在封装衬底和器件衬底上方形成包括开口的约束层，其中在约束层与封装衬底之间限定腔体；以及通过约束层的开口利用模塑材料来填充腔体。
本发明提供了一种用于封装器件衬底的方法。更具体地，该方法包括：将器件衬底连接至封装衬底；在器件衬底和封装衬底上方形成金属层，其中在金属层与封装衬底之间限定腔体；在金属层中形成开口，其中开口与腔体连通；以及通过开口在腔体中形成模塑材料。
本发明提供了一种集成电路(IC)封装件。IC封装件包括：第一衬底；设置在第一衬底上方的第二衬底；设置在第一与第二衬底之间的多个焊料凸块，以电连接第一与第二衬底；设置在第一和第二衬底上方的约束层，使得在约束层与第一衬底之间形成腔体；以及设置在腔体内并且穿过约束层延伸的模塑材料。约束层具有顶面和相对的底面，并且模塑材料从约束层的顶面延伸至底面。
上面论述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种方法，包括：
提供封装衬底；
将器件衬底连接至所述封装衬底；
在所述封装衬底和所述器件衬底上方形成包括开口的约束层，其中，在所述约束层与所述封装衬底之间限定腔体；以及
通过所述约束层的开口利用模塑材料来填充所述腔体。
2.根据权利要求1所述的方法，其中，将所述器件衬底连接至所述封装衬底包括将固定在所述器件衬底的底面上的至少一个连接件接合至所述封装衬底。
3.根据权利要求2所述的方法，其中，所述器件衬底的底面包括连接至所述至少一个连接件的至少一个微电子和/或纳米电子元件。
4.根据权利要求1所述的方法，还包括：在所述器件衬底与所述约束层之间沉积界面层。
5.根据权利要求4所述的方法，其中，所述界面层被配置为将所述器件衬底与所述约束层接合。
6.根据权利要求1所述的方法，其中，所述模塑材料包括树脂材料和聚合物中的至少一种。
7.一种方法，包括：
将器件衬底连接至封装衬底；
在所述器件衬底和所述封装衬底上方形成具有开口的金属层，其中，在所述金属层与所述封装衬底之间限定腔体；以及
通过所述开口在所述腔体中形成模塑材料。
8.根据权利要求7所述的方法，还包括：对所述腔体中的模塑材料进行固化。
9.一种集成电路(IC)封装件，包括：
第一衬底；
第二衬底，设置在所述第一衬底上方；
多个连接件，设置在所述第一衬底与所述第二衬底之间，以电连接所述第一衬底与所述第二衬底；
约束层，设置在所述第一衬底和所述第二衬底上方，使得在所述约束层与所述第一衬底之间形成腔体；以及
模塑材料，设置在所述腔体内并且穿过所述约束层延伸，
其中，所述约束层具有顶面和相对的底面，并且所述模塑材料从所述约束层的顶面延伸至所述底面。
10.根据权利要求9所述的封装件，还包括：界面层，设置在所述第二衬底的顶面与所述约束层的底面之间。
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