CN108573933A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN108573933A
CN108573933A CN201710650755.XA CN201710650755A CN108573933A CN 108573933 A CN108573933 A CN 108573933A CN 201710650755 A CN201710650755 A CN 201710650755A CN 108573933 A CN108573933 A CN 108573933A
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semiconductor chip
face
resin
chip
semiconductor
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CN108573933B (zh
Inventor
唐金祐次
福田昌利
本间庄
本间庄一
三浦正幸
小牟田直幸
赤羽由佳
尾山幸史
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

本发明的实施方式提供一种更有效率地利用树脂将半导体芯片积层体密封而成的半导体装置及其制造方法。实施方式的半导体装置具备：配线衬底，具有第1面；芯片积层体，位于所述第1面上，且包含第1半导体芯片、设置在所述第1半导体芯片与所述第1面之间且具有贯通电极的第2半导体芯片、及设置在所述第2半导体芯片与所述第1面之间的第3半导体芯片；第1树脂，位于所述第1面与所述第3半导体芯片之间且与所述第1面及所述第3半导体芯片相接；以及第2树脂，位于所述第2半导体芯片与所述第1面之间，与所述第2半导体芯片及所述第1面相接并将所述芯片积层体密封，且材料与所述第1树脂不同。

Description

半导体装置及其制造方法
[相关申请案]
本申请案享有以日本专利申请案2017-46390号(申请日：2017年3月10日)作为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
对于NAND(Not AND，与非)型闪存等要求高容量的器件，提出了将半导体芯片呈多段积层并进行树脂密封的方法。关于各半导体芯片，为了使信号提取的传输速度更高速化，利用TSV(Through Silicon VIA，硅穿孔)方式的积层方式受到关注。
发明内容
本发明的实施方式提供一种更有效率地利用树脂将半导体芯片积层体密封而成的半导体装置及其制造方法。
实施方式的半导体装置具备：配线衬底，具有第1面；芯片积层体，位于所述第1面上，且包含第1半导体芯片、设置在所述第1半导体芯片与所述第1面之间且具有贯通电极的第2半导体芯片、及设置在所述第2半导体芯片与所述第1面之间的第3半导体芯片；第1树脂，位于所述第1面与所述第3半导体芯片之间且与所述第1面及所述第3半导体芯片相接；以及第2树脂，位于所述第2半导体芯片与所述第1面之间，与所述第2半导体芯片及所述第1面相接并将所述芯片积层体密封，且材料与所述第1树脂不同。
附图说明
图1是表示第1实施方式的半导体装置的构成的剖视图。
图2是表示第1实施方式的半导体装置的构成的剖视图。
图3(a)～(e)是说明第1实施方式的半导体装置的平面布局的图。
图4是说明第1实施方式的半导体装置的第1制造方法的流程图。
图5(a)及(b)是说明第1实施方式的半导体装置的第1制造方法的图。
图6(a)及(b)是说明第1实施方式的半导体装置的第1制造方法的图。
图7(a)及(b)是说明第1实施方式的半导体装置的第1制造方法的图。
图8是说明第1实施方式的半导体装置的第1制造方法的图。
图9是说明第1实施方式的半导体装置的第1制造方法的图。
图10是说明第1实施方式的半导体装置的另一制造方法的流程图。
图11是说明第1实施方式的半导体装置的第2制造方法的流程图。
图12(a)及(b)是说明第1实施方式的半导体装置的第2制造方法的图。
图13是说明第1实施方式的半导体装置的第2制造方法的图。
图14是表示第2实施方式的半导体装置的构成的图。
图15(a)及(b)是说明第2实施方式的半导体装置的制造方法的图。
图16(a)及(b)是说明第2实施方式的变化例的图。
具体实施方式
(第1实施方式)
以下，参照图1至图13，对第1实施方式的半导体装置进行说明。此外，在以下的附图的记载中，对于相同的部分，以相同的符号来表示。其中，附图中，厚度与平面尺寸的关系、比率等与实际不同，是示意性的图。另外，在本说明书中，为了方便说明，而使用XYZ正交坐标系统。在该坐标系统中，将相对于配线衬底的主面平行的方向且相互正交的2个方向设为X方向及Y方向，将相对于这些X方向及Y方向两者正交的方向设为Z方向(高度方向)。
图1是表示第1实施方式的半导体装置的构成的XZ截面示意图。图2是表示相当于图1的A-A'的半导体装置的YZ切断截面的示意图。如图1所示，本实施方式的半导体装置具备包含支撑衬底1、半导体芯片2、贯通电极3、逻辑LSI(Large-scale integrated circuit，大规模集成电路)(半导体芯片)4及金属凸块5的芯片积层体、配线衬底6、及树脂模具7。此外，在以下说明中，将逻辑LSI4设为半导体芯片4。
本实施方式的半导体装置具有如下构造：在配线衬底6上倒装芯片连接包含支撑衬底1、半导体芯片2及半导体芯片4的芯片积层体，且包含半导体芯片2及4间的配线衬底6上的芯片积层体由树脂7模塑。树脂模具7例如使用环氧树脂等。
支撑衬底1具有与配线衬底6对向的第1面1a、及与第1面1a相反的面即第2面1b。在支撑衬底1的第1面1a，经由粘接剂11粘接着半导体芯片2-1。
支撑衬底1例如使用引线框架等金属板、硅衬底、或膜材料等。粘接剂11例如包含附模组胶膜。
在半导体芯片2-1的与支撑衬底1相反的面形成多个金属凸块5，金属凸块5电连接于形成在半导体芯片2-2的贯通电极3。另外，同样地，半导体芯片2-2的贯通电极3经由金属凸块5而电连接于形成在半导体芯片2-3的贯通电极3。在半导体芯片2-3的与配线衬底6对向的面形成着未图示的再配线。半导体芯片2-3的贯通电极3经由金属凸块5与半导体芯片4连接。将支撑衬底1、半导体芯片2及半导体芯片4一并作为芯片积层体。
在半导体芯片4与配线衬底6之间具有粘接剂12。粘接剂12例如使用NCP(NonConductive Paste，非导电膏)及NCF(Non Conductive Film，非导电膜)。NCP及NCF例如使用包含丙烯酸系树脂或环氧树脂的树脂，但并无特别限定。例如，粘接剂12是与树脂模具7不同的材料。通过具有粘接剂12，而易于将芯片积层体固定在配线衬底上。
半导体芯片2例如包含NAND型闪存等存储器芯片。半导体芯片2、4可使用硅衬底、SiC或GaN等衬底等，但并无特别限定。在本实施方式中，半导体芯片4与半导体芯片2相比，XY平面上的面积较小。
设置在半导体芯片2-2、2-3的贯通电极(Through Silicon Via：TSV)3将电位或信号传输到半导体芯片2-1、2-2。
半导体芯片2与共通的半导体芯片4并联连接(总线连接)。也就是说，对通过贯通电极3而在芯片积层方向上形成的共通的数据总线，并联连接着多个半导体芯片2的数据输入输出线。
金属凸块5例如使用Au、Ni、Cu、Sn、Bi、Zn、In、或其合金。或者，也可以代替金属凸块而使用包含Au、Ni、Cu、Al、Pd、或其合金的电极垫。
本实施方式中的半导体芯片2的数量例如表示了3个，但半导体芯片2的数量并无特别限定。另外，金属凸块5的数量也并无特别限定。
配线衬底6具有树脂制的绝缘层61、及金属制的配线层62。绝缘层61具有核心层及增层。在配线衬底6上，以相对于配线衬底6来说半导体芯片4最近，支撑衬底1最远的方式搭载着芯片积层体。
例如，在图1中，配线衬底6具有作为芯片积层体的搭载面的第1面6a、及作为第1面6a的相反面的第2面6b。在配线衬底6的第2面6b形成着外部连接端子9。在将半导体装置用作BGA(Ball Grid Array，球栅阵列)封装的情况下，外部连接端子9使用具有焊料球、镀焊料、镀Au等的突起端子。在将半导体装置用作LGA(Land Grid Array，栅格阵列)封装的情况下，外部连接端子9使用金属焊垫。
在配线衬底6的第1面6a设置内部连接端子10。内部连接端子10例如经由焊料凸块8而连接于除半导体芯片4以外的芯片积层体的最下段的半导体芯片2-3的与第1面6a对向的面的电极垫2-3a。在图1中，焊料凸块8例如形成在第1焊料凸块8a与第2焊料凸块8b的至少两个部位。内部连接端子10在与芯片积层体连接时作为连接部(连接垫)而发挥功能，且经由配线衬底6的配线网与外部连接端子9电连接。焊料凸块8的个数并无特别限定，但为了改善连接不良，较理想的是设置多个。
位于配线衬底6的第1面6a上的芯片积层体、金属凸块5、及焊料凸块8整体被树脂模具7覆盖且密封。
此外，如图1所示，也可以在半导体芯片2间及半导体芯片2与4间设置粘接剂13。另外，如图2所示，也可以在与配线衬底6的第1面6a对向的半导体芯片2-3与配线衬底6之间设置粘接剂14。利用粘接剂13及14，从而半导体芯片2间、及配线衬底6与芯片积层体的固定变得牢固，能够减少位置偏移。
此时，在树脂的弹性模数或玻璃转移点(Tg)处于粘接剂12＜粘接剂13＜树脂模具7的大小关系的情况下，能够进一步抑制树脂模具7的界面剥离。进而，在热膨胀系数处于树脂模具7＜粘接剂12＜粘接剂13的大小关系的情况下，能够进一步抑制配线衬底6的翘曲，从而改善第1及第2焊料凸块8a、b与配线衬底6的连接不良。粘接剂13例如使用SA(SpacerAdhesive，间隔胶)。粘接剂13例如包含含有丙烯酸系树脂或环氧树脂等的材料。粘接剂14例如使用NCP，但并无特别限定。此外，本实施方式的玻璃转移点是使用DMA(DynamicMechanical Analysis，动态力学分析)法进行测定，热膨胀系数是利用TMA(Thermomechanical Analysis，热机械分析)法进行测定。弹性模数例如为弯曲弹性模数。
接下来，对上述粘接剂12及13在配线衬底6上的XY平面的布局进行说明。
图3(a)～(e)是表示除芯片积层体及树脂模具7以外的配线衬底6的第1面6a的XY平面图。将形成第1焊料凸块8a的区域设为第1焊料凸块区域8a'，将形成第2焊料凸块的区域设为第2焊料凸块区域8b'。进而，以虚线表示供搭载半导体芯片4的区域。
如图3(a)所示，本实施方式的半导体装置至少在半导体芯片4与配线衬底6之间具有粘接剂12。另外，此时，如图3(b)、(d)所示，也可以设置使半导体芯片2与配线衬底6粘接的粘接剂14。粘接剂14的个数或配置并无特别限定，例如，粘接剂12及粘接剂14呈一直线状位于Y方向上。如图3(c)所示，粘接剂12及粘接剂14的数量也可以分别为2个以上，还可以在第1及第2焊料凸块区域8a'、8b'的外侧进而设置粘接剂14。此外，所谓外侧是指在以第1及第2焊料凸块区域8a'、8b'作为轴的X方向上与半导体芯片4为相反侧的区域。另一方面，所谓内侧是指在以第1及第2焊料凸块区域8a'、8b'作为轴的X方向上半导体芯片4侧的区域。
上述中，例如，如下关系成立：位于半导体芯片4与配线衬底之间的粘接剂12的粘接面积比位于半导体芯片2与配线衬底6之间且设置在第1及第2焊料凸块区域8a'、8b'的内侧的粘接剂14的粘接面积大。
如图3(e)所示，在进而设置第3焊料凸块区域8c，焊料凸块区域有3个以上的情况下，或者，在半导体芯片4有2个以上的情况下，也同样地，上述面积的关系成立。
其中，在图3中，只要至少在半导体芯片4与配线衬底6之间设置粘接剂12即可，焊料凸块区域及粘接剂的位置、个数、面积等并无特别限定。
根据本实施方式的半导体装置，通过在芯片积层体与配线衬底之间局部地设置粘接剂12(及14)，能够抑制配线衬底6的翘曲，从而抑制焊料凸块8与配线衬底的连接不良。进而，能够减少树脂模具7在半导体芯片4表面的界面剥离。
接下来，使用图4至图10，对本实施方式的半导体装置的第1制造方法进行说明。
图4是以制造步骤顺序表示本实施方式的半导体装置的第1制造方法的流程图。图5～图8是以步骤顺序表示制造步骤的半导体装置的XZ剖视图。
如图5(a)所示，在预先形成着金属凸块5的半导体芯片2-1的与形成着金属凸块5的面为相反侧的面设置粘接剂11，并使粘接剂11粘接在支撑衬底1的第1面1a(S-1)。此时，也可以预先在支撑衬底1形成粘接剂11。
接着，如图5(b)所示，将预先形成着贯通电极3且具有金属凸块5的半导体芯片2-2积层在半导体芯片2-1上(S-2)。贯通电极3的形成是例如通过BSV(Back Side VIA，背侧通过)方式的晶片工艺来进行。此外，所谓BSV方式是如下方法：在衬底表面形成具有配线的LSI及表电极，从衬底背面朝向配线形成孔，并将金属埋入到孔中，由此形成TSV。
此处，以形成在半导体芯片2-2的贯通电极3与形成在半导体芯片2-1的金属凸块5在相对于支撑衬底1大致垂直的Z轴上下重叠的方式进行积层。以相同的方式将具有贯通电极3的半导体芯片2-3积层在半导体芯片2-2上(图6(a))。在半导体芯片2-3中，例如在与半导体芯片2-2为相反侧的面具有再配线(未图示)及电极垫2-3a。此外，关于半导体芯片2的积层，也可以使用如下方法：不在半导体芯片2-1预先形成金属凸块5，而在半导体芯片2-2及2-3的与支撑衬底1对向的面预先形成金属凸块5，并如上所述那样使它们积层。
接着，如图6(b)所示，将形成着金属凸块5的半导体芯片4积层在半导体芯片2-3上(S-3)。此时，例如以金属凸块5位于半导体芯片2-3的贯通电极3上的方式搭载。此外，也可以在半导体芯片2-3的与配线衬底6对向的面形成再配线。在该情况下，在再配线上搭载金属凸块5。以此方式完成芯片积层体。其后，进行第1回流焊(还原回流焊)(S-4)。
在上述芯片积层体中，第1回流焊之前使各个半导体芯片2积层时的温度是以未达金属凸块5的熔融温度进行，由此，使半导体芯片间不机械性地连接。由此，降低如下危险：在积层半导体芯片2时，因反复进行金属凸块5的熔融或凝固而导致金属凸块5变脆，从而半导体芯片2的连接部断裂。
接着，如图7(a)、(b)所示，在具有配线的配线衬底6的第1面6a的内部连接端子10上形成第1及第2焊料凸块8a、8b及粘接剂12(S-5)，将利用上述方法制造而成的芯片积层体倒装芯片安装在第1面6a(S-6)。此时，使形成在半导体芯片2-3的电极垫2-3a及配线衬底6上的焊料凸块8与配线衬底6重叠。使半导体芯片4经由粘接剂12而粘接在配线衬底6。此外，关于进行倒装芯片安装时的温度，也可以未达形成在配线衬底6的第1及第2焊料凸块8a、8b的熔融温度进行。
在将粘接剂14设置在半导体芯片2与配线衬底6之间的情况下，在配线衬底6上形成粘接剂12的同时进行粘接剂14的形成。
接着，将搭载着芯片积层体的配线衬底6在还原气氛内进行加热，使半导体芯片的金属凸块5及配线衬底6的焊料凸块8熔融，而进行第2回流焊(S-7)。由此，使芯片积层体与配线衬底6电连接。
接着，如图8所示，利用树脂模具7将也包含半导体芯片2之间及芯片积层体与配线衬底6之间的配线衬底6上一次性密封(S-8)。
如图9所示，在配线衬底6的第2面6b形成外部连接端子9。最后，进行半导体装置的片段化(单片化)(未图示)。
以上述方式完成利用本实施方式的第1制造方法的半导体装置。
根据第1制造方法的半导体装置的制造方法，通过在配线衬底6上形成粘接剂12，与不形成粘接剂12的情况相比，能够将芯片积层体更稳定地固定在配线衬底6。另外，因为在半导体芯片4与配线衬底6之间预先形成粘接剂12，所以与无粘接剂12的情况相比，能够降低树脂模具7难以填充而产生间隙从而变得密接不良的可能性。进而，在形成芯片积层体之后，能够不利用底部填充剂等将树脂一次填充到芯片间，而是一次性地将整体进行树脂密封。因此，能够削减步骤数。
以下，在第1制造方法中，如图10所示，也有不进行第1回流焊的方法。在该情况下，代替第1回流焊而在半导体芯片2间及半导体芯片2与4之间设置粘接剂13，由此将芯片积层体固定。粘接剂13是在积层半导体芯片2及4时设置在芯片间(S-2、3)。粘接剂13是在涂布到半导体芯片之后，通过光刻步骤来形成。在图10所示的流程中，将利用粘接剂13而固定的芯片积层体倒装芯片安装在配线衬底6之后进行最初的回流焊(S-6)。由此，因为回流焊次数变为1次，所以能够进一步削减步骤数。
此外，在按照图4所示的流程图进行制造的情况下，也可以设置粘接剂13，而将芯片积层体进一步固定。
接着，使用图11至图13，对本实施方式的半导体装置的第2制造方法进行说明。
图11是以制造步骤顺序表示本实施方式的半导体装置的第2制造方法的流程图。图12及图13是表示制造步骤的一部分的半导体装置的XZ剖视图。此外，关于与第1制造方法相同的部分，省略其说明。
如图12(a)所示，与第1制造方法同样地形成进行第1回流焊之前的芯片积层体(S-1～S-3)。此时，也可以在半导体芯片2间、及半导体芯片2与4之间设置粘接剂13。
接着，如图12(b)所示，在半导体芯片4涂布粘接剂12(S-4)。也可以视需要也在半导体芯片2涂布粘接剂12。
接着，如图13所示，将涂布有粘接剂12的芯片积层体倒装芯片安装在预先形成着焊料凸块8的配线衬底6(S-6)。
在第2制造方法中，在将芯片积层体安装到配线衬底6时，将配线衬底6设定为粘接剂12的硬化温度。因此，芯片积层体与配线衬底6被粘接剂12固定。其后，通过回流焊将配线衬底6与芯片积层体电连接(S-7)。最后，与第1制造方法同样地，利用树脂模具7将配线衬底6上整体一次性密封(S-8)，从而完成第2制造方法的半导体装置。
根据第2制造方法的半导体装置的制造方法，具有与第1制造方法相同的效果，进而，当在芯片积层体上直接涂布粘接剂12之后，将其安装到配线衬底6上，因此在倒装芯片安装时能够将配线衬底6设定为粘接剂12的硬化温度。例如，在将粘接剂12直接涂布到配线衬底6上的情况下，如果将配线衬底6设为粘接剂12的硬化温度，那么有在安装芯片积层体之前粘接剂12硬化而无法进行配线衬底6与芯片积层体的固定的危险。因此，必须在不提升配线衬底6的温度的情况下使芯片积层体的温度上升，因为对芯片积层体施加负载，除此以外，从支撑衬底1侧提升芯片积层体的温度，所以到粘接剂12达到硬化温度为止需花费时间。此外，对于芯片积层体的负载是指例如因温度上升所致的半导体芯片2间的粘接剂13或金属凸块5的变形。
以上，根据第2制造方法的半导体装置的制造方法，能够进行芯片积层体的安装时间较短，且进一步提高可靠性的半导体装置的制造。
此外，第1及第2制造方法中所示的半导体装置的剖视图是一例，粘接剂的个数等并无特别限定。
(第2实施方式)
接下来，一边参照图14至图16，一边对第2实施方式进行说明。
第2实施方式与第1实施方式相比，在不使用支撑衬底的方面不同。此外，除此以外的构成及制造方法与第1实施方式相同。
图14是表示第2实施方式的半导体装置的构成的剖视图。如图14所示，本实施方式的半导体装置与第1实施方式相比，不使用支撑衬底。也就是说，配线衬底上的芯片积层体的最上段(Z轴上段)成为半导体芯片2-1。此外，其他构成因为与第1实施方式相同，所以省略其说明。另外，在图14的半导体装置中，也可以在半导体芯片2及4间设置粘接剂13，还可以在半导体芯片2与配线衬底6之间设置粘接剂14。
如图15(a)所示，第2实施方式的半导体装置的制造方法是在预先形成着金属凸块5的半导体芯片2-1上积层预先形成着贯通电极3及金属凸块5的半导体芯片2-2。此时，以在相对于半导体芯片2-1大致垂直的Z轴方向上，半导体芯片2-1的金属凸块5与半导体芯片2-2的贯通电极3的位置重叠的方式进行积层。其后的步骤因为与第1实施方式相同，所以省略说明。此外，如图15(b)所示，也可以在半导体芯片2之间及半导体芯片2与4之间设置粘接剂13。另外，也可以在半导体芯片2与配线衬底6之间设置粘接剂14。
以上，根据本实施方式的半导体装置，具有与第1实施方式相同的效果，进而，与第1实施方式相比，能够在不使用支撑衬底的情况下形成芯片积层体，所以削减了步骤数及费用。
接下来，一边参照图16，一边对第2实施方式的另一制造方法进行说明。
另一制造方法与第1实施方式的制造方法相比，在使用带材料的方面不同。此外，除此以外的方法与第1实施方式相同。
如图16(a)所示，准备具有粘接性的带材料100，使形成着金属凸块的半导体芯片2-1粘接在带材料100之上。关于带材料100，例如只要为单面具有粘接性的材料，那么其形状或材质不限。其后，与第1实施方式同样地形成芯片积层体。其后，使带材料100从芯片积层体剥离。带材料100的剥离例如使用拾取工具A及吸附工具B等。
在图16(b)中示出使用拾取工具A及吸附工具B的带材料100的剥离方法。利用拾取工具A将芯片积层体向上推，同时利用吸附工具B吸附芯片积层体的半导体芯片4，由此能够使带材料100从芯片积层体剥离。此外，此时被吸附的半导体芯片也可以是半导体芯片2。其后的制造方法如第1实施方式所示。
以上，根据本实施方式的半导体装置的另一制造方法，具有与第1实施方式相同的效果，进而，与第1实施方式相比，因为在之后使带材料剥离，所以能够削减半导体装置的面积。
对本发明的若干个实施方式进行了说明，但这些实施方式是作为示例而提出的，并非意在限定发明的范围。这些新颖的实施方式能够以其他各种方式实施，且能够在不脱离发明主旨的范围内进行各种省略、替换、变更。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1 支撑衬底
1a、6a 第1面
1b、6b 第2面
2 半导体芯片
3 贯通电极
4 逻辑LSI(半导体芯片)
5 金属凸块
6 配线衬底
7 树脂模具
8a、8b 焊料凸块
9 外部连接端子
10 内部连接端子
11、12、13、14 粘接剂(树脂)
61 绝缘层
62 配线层
100 带材料

Claims (10)

1.一种半导体装置，其特征在于具备：
配线衬底，具有第1面；
芯片积层体，位于所述第1面上，且包含第1半导体芯片、设置在所述第1半导体芯片与所述第1面之间且具有贯通电极的第2半导体芯片、及设置在所述第2半导体芯片与所述第1面之间的第3半导体芯片；
第1树脂，位于所述第1面与所述第3半导体芯片之间且与所述第1面及所述第3半导体芯片相接；以及
第2树脂，位于所述第2半导体芯片与所述第1面之间，与所述第2半导体芯片及所述第1面相接并将所述芯片积层体密封，且材料与所述第1树脂不同。
2.根据权利要求1所述的半导体装置，其特征在于：
在所述第1半导体芯片与所述第2半导体芯片之间具有第3树脂，该第3树脂与所述第1及第2半导体芯片相接且材料与所述第2树脂不同。
3.根据权利要求1或2所述的半导体装置，其特征在于：
在所述第2半导体芯片与所述第1面之间具有第4树脂，该第4树脂与所述第2半导体芯片及所述第1面相接，且材料与所述第2树脂不同。
4.根据权利要求2所述的半导体装置，其特征在于：
在所述第1、第2及第3树脂中，弹性模数或玻璃转移点中的任一者成为第1树脂＜第3树脂＜第2树脂。
5.根据权利要求2所述的半导体装置，其特征在于：
在所述第1、第2及第3树脂中，热膨胀系数成为第2树脂＜第1树脂＜第3树脂。
6.一种半导体装置的制造方法，其特征在于：
在第1半导体芯片的第1面上，经由第1凸块电极将具有贯通电极的第2半导体芯片以所述第1凸块电极与所述贯通电极重叠的方式积层，
在所述第2半导体芯片上，以所述贯通电极与第2凸块电极重叠的方式经由所述第2凸块电极使第3半导体芯片积层而形成芯片积层体，
在配线衬底的第2面形成第1树脂，
一边使所述第1树脂与所述第3半导体芯片粘接，一边经由第3凸块电极将所述芯片积层体搭载在所述配线衬底的第2面，
通过回流焊将所述第1衬底与所述芯片积层体电连接，
将所述第2面上及所述第1、第2及第3半导体芯片间树脂密封。
7.一种半导体装置的制造方法，其特征在于：
在第1半导体芯片的第1面上，经由第1凸块电极将具有贯通电极的第2半导体芯片以所述第1凸块电极与所述贯通电极重叠的方式积层，
在所述第2半导体芯片上，以所述贯通电极与第2凸块电极重叠的方式经由所述第2凸块电极使第3半导体芯片积层而形成芯片积层体，
在所述第3半导体芯片的与所述第2凸块电极所在的面相反的面上形成第1树脂，
将形成着所述第1树脂的所述芯片积层体以所述第1树脂粘接在配线衬底的第2面的方式搭载，
通过回流焊将所述配线衬底与所述芯片积层体电连接，
将所述第2面上及所述第1、第2及第3半导体芯片间树脂密封。
8.根据权利要求6或7所述的半导体装置的制造方法，其特征在于：
在将所述芯片积层体搭载在所述配线衬底的第2面之前，进行所述芯片积层体的回流焊，使所述贯通电极与所述第1及第2凸块电极分别电连接。
9.根据权利要求6或7所述的半导体装置的制造方法，其特征在于：
在所述第1半导体芯片与所述第2半导体芯片之间设置与所述第1及第2半导体芯片相接的第2树脂。
10.根据权利要求6或7所述的半导体装置的制造方法，其特征在于：
在所述第2半导体芯片与所述配线衬底的第2面之间设置与所述第2半导体芯片及所述配线衬底的第2面相接的第3树脂。
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