CN1604310A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1604310A
CN1604310A CNA2004100857336A CN200410085733A CN1604310A CN 1604310 A CN1604310 A CN 1604310A CN A2004100857336 A CNA2004100857336 A CN A2004100857336A CN 200410085733 A CN200410085733 A CN 200410085733A CN 1604310 A CN1604310 A CN 1604310A
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mentioned
semiconductor chip
electrode
lead
wiring pattern
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CNA2004100857336A
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CN1309057C (zh
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盐泽雅邦
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

一种半导体装置，将第1半导体芯片(30)搭载在插接件(10)的第1面(12)上，使通孔(20)和第1电极(34)重叠，在第1半导体芯片(30)上叠放着第2半导体芯片(40)。第1导线(36)，配置在第2面(16)侧，与第1电极(34)和第2配线图案(1 8)连接。第2导线(46)，配置在第1面(12)侧，与第2电极(44)和第1配线图案(14)连接。密封部(50)包括：第1面(12)上的第1部分(52)，和第2面(16)上的第2部分(54)，和通过通孔(20)将第1和第2部分(52、54)连接在一起的第3部分(56)。该装置在应用导线接合法的层叠型半导体芯片中，实现不增加封装厚度，而且使密封部难以剥离。

Description

半导体装置及其制造方法
技术领域
本发明是涉及半导体装置及其制造方法。
背景技术
众所周知，在半导体装置的制造中，导线接合法是一种可靠性高的电气连接方法。在应用导线接合法的层叠型半导体装置中，在被层叠的半导体芯片具有相同大小(或上面的半导体芯片大)时，因为在上下两层半导体芯片间介有隔离体，所以会使封装后的厚度增大。另外，在采用面朝下焊接法将半导体芯片焊接在插接件上的结构中，众所周知，可以应用采用导线接合的技术(参照特开2000-138317号公报)。在这种结构中，在半导体芯片的背面用面朝上焊接法焊接其他的半导体芯片并应用导线接合时，因为将各个半导体芯片分别密封，所以每个密封部都有剥离的可能性。
发明内容
本发明的目的在于，在采用导线接合法制造的层叠型半导体装置中，做到不增加封装厚度，并使密封部的难以剥离。
(1)本发明的半导体装置，具有：
插接件，其中在第1面上形成有第1配线图案，在第2面上形成有第2配线图案，且形成有通孔；
第1半导体芯片，其具有第1电极，且被搭载在上述插接件的上述第1面上，使上述通孔和上述第1电极重叠；
第2半导体芯片，其具有第2电极，且以上述第2电极的朝向与上述第1半导体芯片相反的状态被叠放在上述第1半导体芯片上；
第1导线，其被配置在上述第2面侧，与上述第1电极和上述第2配线图案连接；
第2导线，其配置在上述第1面侧，与上述第2电极和上述第1配线图案连接；
密封部，其中包含：设置在上述插接件的上述第1面上的第1部分、设置在上述插接件的上述第2面上的第2部分、穿设于上述通孔的将上述第1和第2部分相连的第3部分，该密封部密封上述第1和第2半导体芯片，并密封上述第1和第2导线，还密封上述第1和第2配线图案的和上述第1及第2导线之间的连接部。
根据本发明，因为第1和第2半导体芯片被叠放成第1和第2电极朝向相反方向，所以即使不使用隔离体也能把第1导线连接在第1电极上。这样，不会增大封装的厚度。另外，因为密封部的第1和第2部分通过第3部分连接，所以很难剥离密封部。
(2)在该半导体装置中，
包含与多个上述第1电极连接的多个上述第1导线，
所有上述第1导线，也可以在除了与上述第1半导体芯片重叠的区域之外的位置上，与上述第2配线图案相连接。
(3)在该半导体装置中，
在上述第1半导体芯片的互相相反的两端部，分别设置有上述第1电极，
上述第1导线，也可以从上述第1半导体芯片的上述两端部的一侧，延伸为越过另一侧，并在上述第1半导体芯片的外侧，与上述第2配线图案相连。
(4)在该半导体装置中，
上述第1半导体芯片，包含多个上述第1电极，
上述第2半导体芯片，包含多个上述第2电极，
上述第1和第2电极，分别按照相同的排列图案排列，
被层叠的上述第1和第2半导体芯片的、位于重叠位置上的上述第1和第2电极也可以电气连接。
(5)本发明的半导体装置的制造方法包括：
(a)在第1面上形成有第1配线图案、第2面上形成有第2配线图案并且形成有通孔的插接件上，搭载具有第1电极的第1半导体芯片，使通孔和上述第1电极相重叠；
(b)将具有第2电极的第2半导体芯片，以上述第2电极的朝向与上述第1半导体芯片相反的状态叠放在上述第1半导体芯片上；
(c)在上述第2面侧，在上述第1电极和上述第2配线图案上连接第1导线；
(d)在上述第1面侧，在上述第2电极和上述第1配线图案上连接第2导线；和
(e)通过传递模塑(transfer mold)法，密封上述第1和第2半导体芯片，并密封上述第1和第2导线，密封上述第1和第2配线图案的与上述第1第2导线之间的连接部。
上述(e)工序中，从上述插接件的上述第1和第2面的一侧向另一侧，通过上述通孔注入树脂，将第1面上的第1部分、上述第2面上的第2部分、和通过上述通孔将上述第1和第2部分连接在一起的第3部分连为一个整体而形成密封部。根据本发明，因为第1和第2半导体芯片被叠放成第1和第2电极朝向相反方向，所以即使不使用隔离体也能把第1导线连接在第1电极上。因此，不会增大封装的厚度。另外，在进行密封时，因为通过通孔，将树脂从插接件的第1和第2面的一侧开始流向另一侧，所以密封部的第1、第2、第3部分的形成可以一次性地进行，能够缩短或简化工序。此外，因为通过第3部分连接第1和第2部分，所以很难剥离密封部。
附图说明
图1是图2所示的半导体装置的I-I线处剖面图。
图2是说明本发明实施方式的半导体装置的图。
图3是说明本发明的半导体装置的制造方法的图。
图4是说明本发明的半导体装置的制造方法的图。
图5是说明本发明的半导体装置的制造方法的图。
图6是说明本发明的半导体装置的制造方法的图。
图7是说明本发明的半导体装置的制造方法的图。
图8是说明本发明的半导体装置制造方法的变形例的剖面图。
图9是说明本发明的半导体装置制造方法的变形例的俯视图。
图10是表示安装了本实施方式的半导体装置的电路基板的图。
图11是表示具有本实施方式的半导体装置的电子设备的图。
图12是表示具有本实施方式的半导体芯片的电子设备的图。
具体实施方式
以下，参照附图，对本发明的实施方式进行说明。
图1和图2是说明本发明实施方式的半导体装置的图。图1是图2中所示半导体装置的I-I线剖面图。
半导体装置具有插接件10。插接件10可以是基板，也可以是极板。插接件10也可以做成矩形。插接件10，也可以用聚酰亚胺树脂等树脂构成，也可以由树脂等有机材料和无机材料的混合材料构成，也可以是金属基板或陶瓷基板。在插接件10的第1面12上，形成有第1配线图案14。在插接件10的第2面16上，形成有第2配线图案18。第1和第2配线图案14、18，也可以分别具有将多个点电连接的配线、和形成与其它部件间的电气连接部的焊盘。第1和第2配线图案14、18，也可以通过图示中没有表示的通孔等进行电气连接，也可以不构成电连接(在电气上隔离)。
在插接件10上，形成有1个或多个通孔20。通孔20贯通第1和第2面12、16。第1和第2配线图案14、18形成为不与通孔20重叠。通孔20，也可以做成长孔形状(长方形，长圆或椭圆形)。
半导体装置中，具有第1半导体芯片30。在第1半导体芯片30上，形成有集成电路32。第1半导体芯片30具有多个第1电极34。第1电极34也可以只是一个基座(pad)，也可以如图1所示，包含基座和设在其上面的凸起。第1电极34被设置在形成有集成电路32的平面上。第1半导体芯片30也可以是外围型。这种情况下，第1电极34，在第1半导体芯片30的端部设置为1列或多列。也可以在第1半导体芯片30互相相反的两端部分别排列一列或多列的第1电极34。在图2所示的例子中，在第1半导体芯片30的矩形面中，第1电极34排列在平行的两边端部，也可以排列在矩形的四边端部。作为变形例，第1电极34也可以在半导体芯片30中部排列成一列或多列。
第1半导体芯片30，被搭载在插接件10上。第1半导体芯片30通过粘着剂22粘贴在插接件10上。粘着剂22可以是树脂。粘着剂22，也可以具有能量固化性(热固化性或紫外线固化性等)。粘着剂22可以是电绝缘的材料。
第1半导体芯片30的形成有第1电极34的面，和插接件10的第1面12相对。另外，也可以是集成电路32的整体与插接件10的第1面12重叠，或也可以是集成电路32的一部分和通孔20重叠。
第1半导体芯片30，配置成第1电极34和通孔20相重叠。如图1所示，第1电极34也可以插入到通孔20内。而且第1电极34也可以通过通孔20，从插接件10的第2面16上突出来。或者，也可以不把第1电极34插入到通孔20内。如图2所示，一个通孔20也可以和在一侧端部排列两个以上的第1电极34(不是全部，而是多个第1电极34)重叠。第1半导体芯片30配置成不完全覆盖通孔20(不堵塞)。也就是说，通孔20的一部分，不与第1半导体芯片30相重叠。这样，即使搭载了第1半导体芯片30，插接件10也能维持通过通孔20的第1面和第2面12、16的连通状态。
在第1电极34和形成在插接件10上的第2配线图案18上，连接第1导线36。这样，第1电极34和第2配线图案18在电气上连通。第1导线36，配置在第2面16侧。第1导线36的和第1电极34之间的连接部位，可以位于和通孔20重叠的位置，也可以位于通孔20内，也可以位于从通孔20突出的位置。第1导线36，也可以在通孔20内沿插接件10厚度方向离第2面16较深的位置上，和第1电极34连接。在多个第1电极34上连接有多个第1导线36时，全部的第1导线36，也可以在除了和第1半导体芯片30重叠的区域之外的位置，和第2配线图案18相连接。
半导体装置，具有第2半导体芯片40。在第2半导体芯片40上形成有集成电路42。第2半导体芯片40，具有多个第2电极44。第2电极44也可以只由基座构成，也可以包括基座和设置在其上面的凸起。关于第2半导体芯片40的内容，也可以和第1半导体芯片30的内容相对应。并且多个第1电极34和多个第2电极44也可以按照相同的排列图案排列。第1和第2半导体芯片30、40，也可以具有相同的大小、相同的形状、相同的结构。而且，所谓的“相同”意味着至少在设计上相同，由制造误差造成的相异可以忽略。或者，第2半导体芯片40也可以比第1半导体芯片30大。
第2半导体芯片40，叠放在第1半导体芯片30上。另外，第2电极44(或者形成有它的面)和第1电极34(或者形成有它的面)朝向相反方向。可以是1个第1电极34和1个第2电极44相重叠。第1和第2半导体芯片30、40，也可以通过粘着剂24粘接。
在第2电极44和形成在插接件10上的第1配线图案14上，连接着第2导线46。这样，第2电极44和第1配线图案14实现电连接。第2导线46，配置在第1面12侧。在多个第2电极44上连接多个第2导线46时，全部的第2导线46，也可以在除了和第2半导体芯片40重叠的区域以外的位置上，和第1配线图案14连接。
半导体装置具有密封部50。密封部50具有设置在插接件10的第1面12上的第1部分52。密封部50还具有设置在插接件10第2面16上的第2部分54。密封部50(例如第1部分52)，密封第1和第2半导体芯片30、40。密封部50(例如第1部分52)，密封第2导线46。密封部50(例如第2部分54)，密封第1导线36。密封部50(例如第1部分52)，密封第1配线图案14的和第2导线46之间的连接部。密封部50(例如第2部分54)密封第2配线图案18的和第1导线36之间的连接部。密封部50具有贯穿通孔20并连接第1和第2部分52、54的第3部分56。密封部50(例如第3部分56)，可以密封第1半导体芯片30的第1电极34。
密封部50可以用树脂(例如模型树脂)形成。密封部50的热膨胀系数可以小于插接件10。为了减小热膨胀系数，密封部50中也可以含有二氧化硅。根据本实施方式，由于密封部50的第1和第2部分52、54通过第3部分56相连接，所以很难剥离密封部50。
半导体装置，也可以具有多个外部端子(例如焊锡球)58。外部端子58，设置在插接件10的第2面16侧(详细说是第2配线图案18(例如其焊盘)上)。外部端子58可以由软焊料(soft solder)或硬焊料(hard solder)中的任一个形成。作为软焊料也可以使用不含铅的焊锡。(下称无铅焊锡)。作为无铅焊锡可以使用锡-银(Sn-Ag)系、锡-铋(Sn-Bi)系、锡-锌(Sn-Zn)系或锡-铜(Sn-Cu)系合金，而且这些合金中可以添加银、铋、锌、铜中的至少一种。
根据本实施方式，因为第1和第2半导体芯片30、40被叠放成第1和第2电极34、44朝向相反方向，所以即使不使用隔离体，也能将第1导线36与第1电极34连接。因此，不会增大封装的厚度。
图3～图7是说明本发明的半导体装置的制造方法的图。如图3所示，在插接件10上搭载第1半导体芯片30，使通孔20和第1电极34相重叠。插接件10和第1半导体芯片30，也可以由粘着剂22粘接。另外将第2半导体芯片40以第2电极44朝向与第1半导体芯片30相反方向的状态叠放在第1半导体芯片30上。第1和第2半导体芯片30、40，也可以通过粘着剂24粘接。关于插接件10与第1和第2半导体芯片30、40之间的位置关系，与从上述的关于半导体装置的构成的说明中推出的内容相对应。
如图4所示，在插接件10的第2面16侧，第1导线36与第1电极34和第2配线图案18连接。为了进行连接，也可以以第1电极34朝上的状态，将第1和第2半导体芯片30、40放置到块60上。第2半导体芯片40可以接触到块60上。块60也可以是加热块。此时，可加热第1和第2半导体芯片30，40，进而加热第1电极34。
如图5所示，在插接件10的第1面12侧，第2导线46与第2电极44和第1配线图案14连接。为了进行连接，也可以以第2电极44朝上的状态，将第1和第2半导体芯片30、40放置到块62上。插接件10可以接触到块62上。块62也可以是加热块。此时，可加热第1和第2半导体芯片30，40，进而加热第2电极44。若预先设置有第1导线36，则形成块62时要避开第1导线36。第1导线36的和第1电极34连接部分位于通孔20内且沿插接件10的厚度方向较深的位置时，能降低第1导线36的从第2面16引出的导线环。这样，可以减小块62上的用于避开第1导线36的凹部、凹处或缺口。
对图4和图5的工序顺序没有限定，可以任意地进行。
作为与图4和图5所示例子不同的例子，在第1和第2电极34、44中，在后连接的一方，可以设在比另一方更靠近第1或第2半导体芯片30、40中央的位置。此时，在形成为可以避开之前连接的第1或第2导线36、46的块60或62的上方(正上方)，可以进行在后的连接。也就是说，可以利用块60或62支撑在后连接第1或第2导线36、46的部分，因此能够防止第1或第2半导体芯片30、40破裂。
如图6所示，利用树脂64，密封第1和第2半导体芯片30、40。另外利用树脂64，还密封第1和第2导线36、46。利用树脂64，密封第1、第2配线图案14、18的和第1、第2导线36、46之间的连接部。由树脂64密封第1和第2电极34、44的和第1、第2导线36、46之间的连接部。
在密封工序中，可以使用传递模塑法，也可以使用上模66和下模68。例如，也可以从插接件10的第1和第2面12、16的一侧向另一侧通过通孔20注入树脂64。
这样，如图7所示，将第1面12上的第1部分52、第2面16上的第2部分54、和通过通孔20将第1和第2部分52、54连接起来的第3部分连为一个整体形成密封部50。
在本实施方式中，经过以上工序可以制造半导体装置。此过程，包含从半导体结构的说明中能够推导出的内容。根据本实施方式，在进行密封时，把树脂64通过通孔20从插接件10的第1面和第2面12、16的一侧流向另一侧，所以密封部50的第1、第2、第3部分52、54、56的形成能够一次性地进行，能够缩短或简化工序。并且，因为第1和第2部分52、54通过第3部分56连接，所以密封部50很难从插接件10上剥离。
图8是说明上述实施方式的变形例的剖面图，图9是其俯视图。第1电极34被分别设置在第1半导体芯片30的相反侧的两端部上。第1半导体芯片30，包含多个第1电极34。第2半导体芯片40，包含多个第2电极44。第1和第2电极34、44，分别按照相同的排列图案排列。
在这个变形例中，第1导线70不同于上述实施方式。如图9所示，第1导线70，从第1半导体芯片30两端部的一侧，延伸至越过另一侧的位置。另外，第1导线70，在第1半导体芯片30的外侧，与第2配线图案18连接。通过以上，如图8所示，即使将第1和第2半导体芯片30、40背对背地配置，也可使在排列图案中处于相同位置的第1和第2电极34、44的与第1和第2配线图案14、18之间的连接部变得很近。并且，也可以将叠放在一起的第1和第2半导体芯片30、40的位于重叠位置的第1和第2电极34、44在电气上连接。详细说，连接在位于重叠位置上的第1和第2电极34、44上的第1和第2导线70、46，分别与第1和第2配线图案14、18连接，该第1和第2导线70、46的与第1和第2配线图案14、18之间的连接部，通过图中没有示出的通孔等在电气上保持连接。
根据本变形例，即使不使用电极相互呈面对称关系排列的2个半导体芯片(所谓镜面对称)，在排列图案上位于相同的位置的第1和第2电极34、44也能在电气上连接。对于其他内容，可以应用上述的实施方式中说明的内容。
图10表示的是安装了在上述实施方式中说明过的半导体装置1的电路基板1000。作为具有这种半导体装置的电子设备，可举出在图11表示的笔记本型个人电脑2000和图12中表示的手机3000。
本发明并不局限于上述实施方式，可以有各种变形。例如，本发明，包含与实施方式中说明过的构成实质上相同的构成(例如，功能、方法以及结果相同的构成，或者目的和结果相同的构成)。
另外，本发明，包含替换了实施方式中说明过的构成中的非本质性的部分而得到的构成。另外，本发明包含能获得和在实施方式中说明过的构成同样效果的构成或能达到同样目的的构成。另外，本发明包含在实施方式说明过的构成上附加公知技术的构成。而且，本发明包含限定性地去除在实施方式中说明过的技术事项中的任一个的内容。或者，本发明包含从上述实施方式中限定性地除去公知技术的内容。

Claims (5)

1、一种半导体装置，其特征在于，具有：
插接件，其中在第1面上形成有第1配线图案，在第2面上形成有第2配线图案，且形成有通孔；
第1半导体芯片，其具有第1电极，且被搭载在上述插接件的上述第1面上，使上述通孔和上述第1电极重叠；
第2半导体芯片，其具有第2电极，且以上述第2电极的朝向与上述第1半导体芯片相反的状态被叠放在上述第1半导体芯片上；
第1导线，其被配置在上述第2面侧，与上述第1电极和上述第2配线图案连接；
第2导线，其配置在上述第1面侧，与上述第2电极和上述第1配线图案连接；
密封部，其中包含：设置在上述插接件的上述第1面上的第1部分、设置在上述插接件的上述第2面上的第2部分、穿设于上述通孔的将上述第1和第2部分相连接的第3部分，该密封部密封上述第1和第2半导体芯片，并密封上述第1和第2导线，还密封上述第1和第2配线图案的和上述第1及第2导线的连接部。
2、根据权利要求1所述的半导体装置，其特征在于，
包含与多个上述第1电极连接的多个上述第1导线，
且所有上述第1导线，在除了与上述第1半导体芯片重叠的区域之外的位置上，与上述第2配线图案相连接。
3、根据权利要求1所述的半导体装置，其特征在于，
在上述第1半导体芯片的相反侧的两端部，分别设置有上述第1电极，
上述第1导线，从上述第1半导体芯片的上述两端部的一侧，延伸至越过另一侧的位置，在上述第1半导体芯片的外侧，与上述第2配线图案相连。
4、根据权利要求3所述的半导体装置，其特征在于，
上述第1半导体芯片包含多个上述第1电极，
上述第2半导体芯片包含多个上述第2电极，
上述第1和第2电极，分别按照相同的排列图案排列，
被层叠的上述第1和第2半导体芯片的位于重叠位置上的上述第1和第2电极在电气上连接。
5、一种半导体装置的制造方法，其特征在于，
包括：
(a)在第1面上形成有第1配线图案、第2面上形成有第2配线图案并且形成有通孔的插接件上，搭载具有第1电极的第1半导体芯片，使通孔和上述第1电极相重叠；
(b)将具有第2电极的第2半导体芯片，以上述第2电极的朝向与上述第1半导体芯片相反的状态叠放在上述第1半导体芯片上；
(c)在上述第2面侧，在上述第1电极和上述第2配线图案上连接第1导线；
(d)在上述第1面侧，在上述第2电极和上述第1配线图案上连接第2导线；和
(e)通过传递模塑法，密封上述第1和第2半导体芯片，并密封上述第1和第2导线，密封上述第1和第2配线图案的与上述第1和第2导线之间的连接部；
上述(e)工序中，从上述插接件的上述第1和第2面的一侧向另一侧，通过上述通孔注入树脂，将第1面上的第1部分、上述第2面上的第2部分、和通过上述通孔将上述第1和第2部分连接的第3部分连为一个整体而形成密封部。
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