CN108022846A - 封装基板及其制作方法 - Google Patents

封装基板及其制作方法 Download PDF

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Publication number
CN108022846A
CN108022846A CN201611099271.2A CN201611099271A CN108022846A CN 108022846 A CN108022846 A CN 108022846A CN 201611099271 A CN201611099271 A CN 201611099271A CN 108022846 A CN108022846 A CN 108022846A
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Prior art keywords
circuit element
dielectric material
connecting pin
package substrate
main body
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CN201611099271.2A
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CN108022846B (zh
Inventor
胡竹青
许诗滨
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Phoenix Pioneer Technology Co Ltd
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Phoenix and Corp
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Abstract

本发明公开了一种封装基板及其制作方法。该封装基板包括：一介电材料主体；一第一电路元件，设置于该介电材料主体内，并具有位于该第一电路元件上侧面的一第一连接端及一第二连接端；一第二电路元件，设置于该介电材料主体内，并具有位于该第二电路元件上侧面的一第三连接端；一第一导电柱，形成于该介电材料主体内并连接至该第一连接端；一第一打线接合导线，连接该第二连接端及该第三连接端；以及一重布线层，形成于该介电材料主体上，并包含一第一重布线导线，第一重布线导线连接至该第一导电柱；该第一连接端及该第二连接端位于该介电材料主体内的一第一深度，该第三连接端位于该介电材料主体内的一第二深度，且该第一深度不同于该第二深度。

Description

封装基板及其制作方法
技术领域
本发明涉及一种晶圆级封装基板及其制作方法。
背景技术
新一代电子产品不仅追求轻薄短小的高密度，更有朝向高功率发展的趋势；因此，集成电路(Integrated Circuit，简称IC)技术及其后端的芯片封装技术亦随之进展，以跟随新一代电子产品的发展趋势。
目前晶圆级封装(Wafer-Level Package，简称WLP)的制作方式如图1a、图1b和图1c所示，先在附加电路板11形成黏接层18，如图1a所示；接着将半导体芯片13或电子元件15的接脚16朝下并通过该黏接层18而黏贴于该附加电路板11，再以铸模技术使铸模化合物12包覆及封装该半导体芯片13或电子元件15，如图1b所示；在去除该附加电路板11及该黏接层18之后，将该半导体芯片13、该电子元件15及该铸模化合物12的组合结构20上下翻转，使得重布线层(ReDistribution Layer，简称RDL)17可制作于该组合结构20的上表面21之上，如图1c所示。
倘若欲以一般现有的微影蚀刻技术制作该重布线层17于该组合结构20的上表面21上，则该上表面21必须能提供很高的平坦度。然而，为了达到上述对该上表面21平坦度的要求，该附加电路板11及该黏接层18必须采用较为昂贵的，且该半导体芯片13及该电子元件15必须以精准而慢速的方式黏贴于该黏接层18；这都会提高封装元件的制造成本。因此，有必要发展新的封装基板技术，以解决上述问题。
发明内容
为达到上述目的，本发明提供一种封装基板，其包含：一介电材料主体；一第一电路元件，设置于该介电材料主体内，并具有位于该第一电路元件上侧面的一第一连接端及一第二连接端；一第二电路元件，设置于该介电材料主体内，并具有位于该第二电路元件上侧面的一第三连接端；一第一导电柱，形成于该介电材料主体内并连接至该第一连接端；一第一打线接合导线，连接该第二连接端及该第三连接端；以及一重布线层，形成于该介电材料主体上，并包含一第一重布线导线，该第一重布线导线连接至该第一导电柱；其中，该第一连接端及该第二连接端位于该介电材料主体内的一第一深度，该第三连接端位于该介电材料主体内的一第二深度，且该第一深度不同于该第二深度。
在本发明的一实施例中，该第一打线接合导线的组成材料包含金、银、铜及其组合或合金。
在本发明的一实施例中，该第一电路元件为半导体芯片或电子元件，且该第二电路元件为半导体芯片或电子元件。
在本发明的一实施例中，该第二电路元件进一步包含位于该第二电路元件上侧面的一第四连接端，该重布线层进一步包含一第二重布线导线，且该封装基板进一步包含一第二导电柱，该第二导电形成于该介电材料主体内并连接该第四连接端与该第二重布线导线。
在本发明的一实施例中，该第二电路元件进一步包含位于该第二电路元件上侧面的一第四连接端，且该封装基板进一步包含：
一第三电路元件，设置于该介电材料主体内，并具有位于该第三电路元件上侧面的一第五连接端；以及
一第二打线接合导线，连接该第四连接端及该第五连接端。
在本发明的一实施例中，封装基板进一步包含一绝缘保护层，该绝缘保护层形成于该介电材料主体下方。
根据本发明另一实施例提供一种封装基板的制作方法，其包含以下步骤：提供一附加电路板、一第一电路元件及一第二电路元件，其中，该第一电路元件具有彼此相对的一第一表面及一第二表面，且该第一电路元件具有位于该第一表面的一第一连接端及一第二连接端，该第二电路元件具有彼此相对的一第三表面及一第四表面，且该第二电路元件具有位于该第三表面的一第三连接端；将该第一电路元件的该第二表面以及该第二电路元件的该第四表面黏贴于该附加电路板上，且该第一电路元件与该第二电路元件在垂直方向上不重迭，其中，该多个第一连接端位于该附加电路板上的一第一高度，该多个第二连接端位于该附加电路板上的一第二高度，且该第一高度不同于该第二高度；采用打线接合方式，形成连接该第二连接端与该第三连接端的一打线接合导线；形成一介电材料，使该介电材料包覆该第一电路元件、该第二电路元件及该打线接合导线；对该介电材料进行开口，形成一贯孔于该第一连接端上；填充一导电材料于该贯孔而形成一导电柱；以及形成一重布线层于该介电材料上。
在本发明的一实施例中，该打线接合导线的组成材料包含金、银、铜、钯及其组合或合金。
在本发明的一实施例中，步骤(E)为通过激光钻孔方式、光微影方式或电浆蚀刻方式实现。
在本发明的一实施例中，步骤(B)为通过一绝缘黏接层实现，且该方法进一步包含以下步骤：移除该附加电路板。
附图说明
图1a、图1b、图1c为现有的晶圆级封装基板的制造过程对应的剖面图；
图2为根据本发明第一实施例的封装基板的剖面示意图；
图3为根据本发明第二实施例的封装基板的剖面示意图；
图4为本发明封装基板制造过程步骤之一的封装基板剖面图；
图5为本发明封装基板制造过程步骤之一的封装基板剖面图；
图6为本发明封装基板制造过程步骤之一的封装基板剖面图；
图7为本发明封装基板制造过程步骤之一的封装基板剖面图；
图8为本发明封装基板制造过程步骤之一的封装基板剖面图。
附图标记说明：100、200-封装基板；120-介电材料主体；121-顶面；130-第一电路元件；131、132、133-连接端；135-第一表面；136-第二表面；140、141-打线接合导线；150-第二电路元件；151、152-连接端；155-第三表面；156-第四表面；161、162-导电柱；170-重布线层；171、172-导电线路；180-黏接层；190-导电柱层；191-金属柱状物；173、193-空间；210-第三电路元件；211、212-连接端；D1、D2-深度。
具体实施方式
为使对本发明的特征、目的及功能有更进一步的认知与了解，兹配合图式详细说明本发明的实施例如后。在所有的说明书及图示中，将采用相同的元件编号以指定相同或类似的元件。
在各个实施例的说明中，当一元素被描述是在另一元素的「上方/上」或「下方/下」，指直接地或间接地在该另一元素之上或之下的情况，其可能包含设置于其间的其他元素；所谓的「直接地」指其间并未设置其他中介元素。「上方/上」或「下方/下」等的描述以图式为基准进行说明，但亦包含其他可能的方向转变。「第一」、「第二」、及「第三」用以描述不同的元素，这些元素并不因为此类谓辞而受到限制。为了说明上的便利和明确，图式中各元素的厚度或尺寸，以夸张或省略或概略的方式表示，且各元素的尺寸并未完全为其实际的尺寸。
图2为根据本发明第一实施例的封装基板100的剖面示意图。该封装基板100包含：介电材料主体120、第一电路元件130、打线接合导线140、第二电路元件150、导电柱161、162以及重布线层170；其中，该介电材料主体120作为该封装基板100的主要架构，其包覆并封装该第一电路元件130、该第二电路元件150及该打线接合导线140，并用以承载或支持该重布线层170。如图2所示，该第一电路元件130具有连接端131、132及133，其位于该第一电路元件130的上侧面，该第二电路元件150具有连接端151及152，其位于该第二电路元件150的上侧面。在该封装基板100的制作过程中，当该第一电路元件130与该第二电路元件150设置于该介电材料主体120之内时，该第一电路元件130与该第二电路元件150的接脚(pin)或连接垫(pad)(也就是连接端131～133、151～152)是朝上放置的。
以图2为例，该第一电路元件130与该第二电路元件150通过一黏接层180而黏贴于该介电材料主体120的底面，且该第一电路元件130与该第二电路元件150在垂直方向上并不重迭。在本实施例中，该第一电路元件130与该第二电路元件150可以是半导体芯片或晶粒，其以集成电路制造技术施加于半导体晶圆，并切割成晶粒及接上作为连接端131～133、151～152的外接脚垫(或称为接脚或连接垫)，例如，特殊应用集成电路(Application-Specific Integrated Circuit，简称ASIC)或内存。该第一电路元件130与该第二电路元件150亦可以是被动式电子元件，例如，积层陶瓷电容器。如果该第一电路元件130与该第二电路元件150具有不同的厚度，则该多个连接端131～133与该介电材料主体120顶面之间的距离(也就是如图所标示的深度D1)将不同于该多个连接端151～152与该介电材料主体120顶面之间的距离(也就是如图所标示的深度D2)。
该打线接合导线140可采用打线接合(wire bonding)方式形成，用以连接该第一电路元件130与该第二电路元件150；也就是说，该打线接合导线140连接该第一电路元件130的连接端133与该第二电路元件150的连接端151。藉此，不同厚度的电路元件之间，可采用低成本的打线接合技术来实现其电性连接，并同时具有导线线径加大及制造过程简单的优点。该打线接合导线140的组成材料可以是金、银、铜、钯及其组合或合金。
此外，关于该导电柱161、162的制作，我们可采用激光钻孔(laser ablation)或光微影(Photolithography)及电浆蚀刻等其他开口技术，在该连接端131及132上方形成深度为D1的贯孔，从而在该连接端152上方形成深度为D2的贯孔，并通过电镀或印刷填充技术于该多个贯孔中填充导电材料，即可形成该导电柱161及162。藉此，虽然连接端131～132与连接端152有水平高度上的差异，但可利用该多个导电柱161、162的深度差异来补偿，从而使将欲于其上制作该重布线层170的基底为平坦表面，则该重布线层170只需利用一般现有的微影蚀刻技术即可于同一水平高度的平面上制作导电布线。
该重布线层(RDL)170又称为增线层，形成于该介电材料主体120上的导电布线，用以将该多个连接端131、132及152连接到其他的位置。也就是说，当电路元件(例如，该第一电路元件130及该第二电路元件150)设置于该介电材料主体120内，其接脚或连接垫(例如，该连接端131、132与该连接端152)的位置在介电材料硬化后亦同时被固定，必须通过该重布线层170的导电布线而将这些接脚或连接垫重新连接到其他合适的位置。该重布线层170包含多个重布线导线171及172，其连接至该多个导电柱161及162。如图2所示，该导电柱161用以将该第一电路元件130的连接端131、132连接至该重布线导线171，该导电柱162则用以将该第二电路元件150的连接端152连接至该重布线导线172。
为了将重布线导线171及172向外连接至其他电路，一导电柱层190可形成于该重布线层170上；其中，该导电柱层190包含多个金属柱状物191，其分别对应该重布线导线171及172。关于该重布线层170在该重布线导线171及172之外的空间173以及该导电柱层190在该金属柱状物191之外的空间193，可填充合适的介电材料使得该封装基板100形成一完整的封装元件。在本实施例中，该黏接层180为形成于该介电材料主体120下方的绝缘层，用以保护该封装基板100在受到外部撞击时不致碎裂损伤。
图3为根据本发明第二实施例的封装基板200的剖面示意图。该封装基板200的结构基本上类似于图2的封装基板100，其差异处在于本实施例可延伸应用于三个以上的电路元件。如图3所示，该封装基板200进一步包含一位于该第一电路元件130与该第二电路元件150之间的第三电路元件210，其连接端211及212亦位于该第三电路元件210的上侧面。该打线接合导线140用以连接该第一电路元件130的连接端133与该第三电路元件210的连接端211，该打线接合导线141用以连接该第二电路元件150的连接端151与该第三电路元件210的连接端212。该导电柱161仍然用以连接该第一电路元件130的连接端131～132与该重布线导线171，该导电柱162则用以连接该第二电路元件150的连接端152与该重布线导线172。藉此，本发明可应用于多个电路元件的封装基板结构。
以下说明本发明提供的封装基板的制造过程。如图4～图8及图2(以第一实施例的封装基板100为例)所示，其分别对应上述第一实施例封装基板100各个步骤的封装基板的剖面图。本发明采用面板等级(panel-level)的制作方式，不同于晶圆等级(wafer-level)的制作方式。
首先，提供一附加电路板110，其为一导电材质的基板，例如，金属基板或是表面镀有金属层的介电材质基板，用以承载或支持该封装基板100的后续制造过程，例如，制作该封装基板100的导电线路。上述基板的金属成分包含铁(Fe)、铜(Cu)、镍(Ni)、锡(Sn)、铝(Al)、镍/金(Ni/Au)及其组合或合金，但本发明不以此为限。
接着，如图4所示，将第一电路元件130与第二电路元件150黏贴于该附加电路板110上。该第一电路元件130具有彼此相对的第一表面135及第二表面136，且该第一电路元件130包含连接端131～133，其位于该第一表面135；同样地，该第二电路元件150具有彼此相对的第三表面155及第四表面156，且该第二电路元件150包含连接端151、152，其位于该第三表面155。在本实施例中，我们可通过一黏接层180，将该第一电路元件130的该第二表面136以及该第二电路元件150的该第四表面156黏贴于该附加电路板110上，且该第一电路元件130与该第二电路元件150在垂直方向上并不重迭。倘若该第一电路元件130与该第二电路元件150选用具有不同厚度的半导体芯片或电子元件，则该多个连接端131～133与该多个连接端151～152将会位于不同的水平高度(如图所示，该多个连接端131～133位于该附加电路板110上的高度为H1，该多个连接端151～152位于该附加电路板110上的高度为H2，且H1≠H2)。
接着，如图5所示，采用打线接合方式形成一打线接合导线140，用以连接该第一电路元件130与该第二电路元件150；也就是该打线接合导线140连接该第一电路元件130的连接端133与该第二电路元件150的连接端151。藉此，不同厚度的电路元件之间，可采用低成本的打线接合技术来实现其电性连接，并同时具有制造过程简单的优点。该打线接合导线140的组成材料可以是金、银、铜及其组合或合金。
接着，如图6所示，采用封装胶体的铸模技术，例如，压缩铸模法(Compressionmolding)，形成包覆该第一电路元件130、该第二电路元件150及该打线接合导线140的介电材料120，其组成材质可以是酚醛基树脂(Novolac-based resin)、环氧基树脂(Epoxy-based resin)、或硅基树脂(Silicone-based resin)等铸模化合物材料。在该介电材料120硬化并与该第一电路元件130、该第二电路元件150及该打线接合导线140形成稳固的封装结构之后，我们可采用例如研磨的方式，自上而下移除该介电材料120的上半部，从而使该介电材料120的顶面121形成一平坦表面，以便于后续制造过程可利用一般现有的增层技术来制作重布线层的导电布线。如图所示，该多个连接端131～133与该介电材料120顶面121之间的距离(也就是如图所标示的深度D1)，将不同于该多个第二连接端151～152与该介电材料120顶面121之间的距离(也就是如图所标示的深度D2)。
接着，如图7所示，对该介电材料120进行开口，使得柱161、162形成于该多个连接端131、132、152上。由于该多个第一连接端131、132位于该介电材料120内的深度D1不同于该多个第二连接端152位于该介电材料120的深度D2，因此可采用激光钻孔或其他开口技术，使得该多个柱161、162的深度分别为D1及D2。倘若使用脉冲式激光来进行开口，则贯孔深度将视该介电材料120的光学性质、激光光波长及脉冲长度而定。在本实施例中，形成该多个贯孔161所需的激光能量会小于形成该贯孔162所需的激光能量。该多个贯孔161及162在被填充以导电材料之后，将会分别形成如图2中的该多个导电柱161及162。在本实施例中，该导电材料可以是铜、镍、锡等金属，或是铜膏、银膏或焊锡等膏类导电物。
接着，如图8所示，形成一重布线层170于该多个导电柱161及162上。该重布线层170形成于该介电材料120上的导电布线，用以将该第一电路元件130的连接端131、132与该第二电路元件150的连接端152连接到其他合适的接线位置。由于该多个导电柱161及162的深度差异的补偿效果，该重布线层170只需利用一般现有的电镀及微影蚀刻等增层技术即可于同一水平高度的平面(该介电材料120的顶面121)上制作导电线路171及172，其分别通过该多个导电柱161及162而连接该多个连接端131、132及该连接端152。
接着，如图2所示，形成一包含多个金属柱状物191的导电柱层190于该重布线层170上，并在该重布线层170的该多个导电线路171及172以及该导电柱层190的该金属柱状物191之外的空间173及193填充合适的介电材料，使得整个封装结构是完整的。由于该附加电路板110为金属基板，且该黏接层180可以是导热材质的组成，因此可用以帮助该第一电路元件130及该第二电路元件150的散热。
在另一实施例中，该黏接层180亦可以是绝缘材质的组成，则该附加电路板110可被进一步移除，如图2所示，使得该黏接层180为形成于该介电材料主体120下方的保护层，用以保护该封装基板100在受到外部撞击时不致碎裂损伤。
以上所述仅为本发明的较佳实施例，当不能以之限制本发明的范围。即大凡依本发明权利要求范围所做的均等变化及修饰，仍将不失本发明的要义所在，亦不脱离本发明的精神和范围，故都应视为本发明的进一步实施状况。

Claims (10)

1.一种封装基板，其特征在于，包含：
一介电材料主体；
一第一电路元件，设置于该介电材料主体内，并具有位于该第一电路元件上侧面的一第一连接端及一第二连接端；
一第二电路元件，设置于该介电材料主体内，并具有位于该第二电路元件上侧面的一第三连接端；
一第一导电柱，形成于该介电材料主体内并连接至该第一连接端；
一第一打线接合导线，连接该第二连接端及该第三连接端；以及
一重布线层，形成于该介电材料主体上并包含一第一重布线导线，该第一重布线导线连接至该第一导电柱；
其中，该第一连接端及该第二连接端位于该介电材料主体内的一第一深度，该第三连接端位于该介电材料主体内的一第二深度，且该第一深度不同于该第二深度。
2.根据权利要求1所述的封装基板，其特征在于，该第一打线接合导线的组成材料包含金、银、铜及其组合或合金。
3.根据权利要求1所述的封装基板，其特征在于，该第一电路元件为半导体芯片或电子元件，且该第二电路元件为半导体芯片或电子元件。
4.根据权利要求1所述的封装基板，其特征在于，该第二电路元件进一步包含位于该第二电路元件上侧面的一第四连接端，该重布线层进一步包含一第二重布线导线，且该封装基板进一步包含一第二导电柱，该第二导电形成于该介电材料主体内并连接该第四连接端与该第二重布线导线。
5.根据权利要求1所述的封装基板，其特征在于，该第二电路元件进一步包含位于该第二电路元件上侧面的一第四连接端，且该封装基板进一步包含：
一第三电路元件，设置于该介电材料主体内，并具有位于该第三电路元件上侧面的一第五连接端；以及
一第二打线接合导线，连接该第四连接端及该第五连接端。
6.根据权利要求1所述的封装基板，其特征在于，进一步包含一绝缘保护层，该绝缘保护层形成于该介电材料主体下方。
7.一种封装基板的制作方法，其特征在于，包含以下步骤：
(A)提供一附加电路板、一第一电路元件及一第二电路元件，其中，该第一电路元件具有彼此相对的一第一表面及一第二表面，且该第一电路元件具有位于该第一表面的一第一连接端及一第二连接端，该第二电路元件具有彼此相对的一第三表面及一第四表面，且该第二电路元件具有位于该第三表面的一第三连接端；
(B)将该第一电路元件的该第二表面以及该第二电路元件的该第四表面黏贴于该附加电路板上，且该第一电路元件与该第二电路元件在垂直方向上不重迭，其中，该多个第一连接端位于该附加电路板上的一第一高度，该多个第二连接端位于该附加电路板上的一第二高度，且该第一高度不同于该第二高度；
(C)采用打线接合方式，形成连接该第二连接端与该第三连接端的一打线接合导线；
(D)形成一介电材料，使该介电材料包覆该第一电路元件、该第二电路元件及该打线接合导线；
(E)对该介电材料进行开口，形成一贯孔于该第一连接端上；
(F)填充一导电材料于该贯孔；以及
(G)形成一重布线层于该介电材料上。
8.根据权利要求7所述的制作方法，其特征在于，该打线接合导线的组成材料包含金、银、铜、钯及其组合或合金。
9.根据权利要求7所述的制作方法，其特征在于，步骤(E)为通过激光钻孔方式、光微影方式或电浆蚀刻方式实现。
10.根据权利要求7所述的制作方法，其特征在于，步骤(B)为通过一绝缘黏接层实现，且该方法进一步包含以下步骤：移除该附加电路板。
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US11410982B2 (en) * 2020-03-30 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacturing

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1858908A (zh) * 2006-05-18 2006-11-08 威盛电子股份有限公司 封装元件
CN104051286A (zh) * 2013-03-12 2014-09-17 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN104332465A (zh) * 2014-09-03 2015-02-04 江苏长电科技股份有限公司 一种3d封装结构及其工艺方法
CN105097744A (zh) * 2014-05-09 2015-11-25 精材科技股份有限公司 晶片封装体及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090170241A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US8354297B2 (en) * 2010-09-03 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
TWI422079B (zh) * 2010-09-07 2014-01-01 Univ Kun Shan 半導體發光元件之散熱座的製作方法
TWI467714B (zh) * 2012-06-18 2015-01-01 矽品精密工業股份有限公司 半導體封裝件及其製法
US9478474B2 (en) * 2012-12-28 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for forming package-on-packages
US10490521B2 (en) * 2014-06-26 2019-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced structure for info wafer warpage reduction
US9659896B2 (en) * 2014-08-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for wafer level package and methods of forming same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1858908A (zh) * 2006-05-18 2006-11-08 威盛电子股份有限公司 封装元件
CN104051286A (zh) * 2013-03-12 2014-09-17 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN105097744A (zh) * 2014-05-09 2015-11-25 精材科技股份有限公司 晶片封装体及其制造方法
CN104332465A (zh) * 2014-09-03 2015-02-04 江苏长电科技股份有限公司 一种3d封装结构及其工艺方法

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