CN104882386B - 半导体器件格栅阵列封装 - Google Patents

半导体器件格栅阵列封装 Download PDF

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CN104882386B
CN104882386B CN201410137295.7A CN201410137295A CN104882386B CN 104882386 B CN104882386 B CN 104882386B CN 201410137295 A CN201410137295 A CN 201410137295A CN 104882386 B CN104882386 B CN 104882386B
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semiconductor element
insulating materials
solder deposits
solder
grid array
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CN104882386A (zh
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王志杰
白志刚
舒爱鹏
徐艳博
张虎昌
宗飞
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NXP USA Inc
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NXP USA Inc
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Abstract

本发明涉及半导体器件格栅阵列封装。格栅阵列组件由其中嵌入有焊料沉积物的电绝缘材料形成。每个焊料沉积物的第一部分暴露在该绝缘材料的第一表面上并且每个焊料沉积物的第二部分暴露在该绝缘材料的相对表面上。半导体管芯安装到该绝缘材料的第一表面并且该半导体管芯的电极用接合线连接到该焊料沉积物。该管芯、接合线和该绝缘材料的第一表面进而覆盖有保护的密封材料。

Description

半导体器件格栅阵列封装
技术领域
本申请一般涉及半导体器件封装，并特别地涉及一种半导体器件球栅阵列封装。
背景技术
封装半导体为封装管芯提供了外部电连接和物理保护。在减小半导体管芯尺寸的持续进步以及形成在管芯上的集成电路的增加的功能，增加了这样封装的半导体的外部连接的复杂性。
封装半导体的一种典型类型是半导体管芯安装到引线框封装形成的四方扁平封装(QFP)。该引线框由金属片形成，其包括管芯贴附垫或旗标以及将该旗标贴附到框的系杆。该引线框的引线电连接到具有接合线的管芯的电极。线接合之后，该半导体管芯和引线被封进诸如塑料材料的化合物(材料)中，仅留引线的一部分暴露。引线的这些暴露部分从引线框的框切开(分离)并弯曲以便于连接到电路板。然而，QFP封装固有的结构导致引线数量的限制并因此限制可被用于特殊封装尺寸的封装外部电连接的数量。进一步的，基于格栅阵列封装的引线框的外部电连接典型地由诸如铜或铝的导体材料的薄的单片制造，并且这些连接不可能足够地支持在密封化合物(材料)中并可变得损耗。
格栅阵列封装已经发展作为QFP封装的替代。格栅阵列封装在增加外部电连接数量的同时维持或甚者减小了封装尺寸。这样的格栅阵列封装包括针栅阵列(PGA)、球栅阵列(BGA)以及平面栅阵列(LGA)。这样的格栅阵列封装的制造要求在其上安装有半导体管芯的衬底。该衬底具有导电迹线和过孔并且通过其凸焊沉积被安装，典型的为焊球。然而，这样的衬底的固有厚度增加了现有的格栅阵列封装的整体尺寸。鉴于包括半导体管芯格栅阵列封装的电子器件的微型化的趋向，这是不期望的。
附图说明
本发明的目的及其优点一起可通过参考优选实施例的随后说明和附图而更好地理解。
图1是根据本发明的第一优选实施例的两部分模具的横截面侧视图；
图2是根据本发明的第一优选实施例的格栅阵列封装的横截面侧视图；
图3是根据本发明的第一优选实施例的由图2的格栅阵列组件形成的半导体管芯组件的平面图；
图4是根据本发明的第一优选实施例的由图3的半导体管芯组件形成的半导体管芯格栅阵列封装的横截面侧视图；
图5是根据本发明的第二优选实施例的两部分模具的横截面侧视图；
图6是根据本发明的第二优选实施例的格栅阵列组件的横截面侧视图；
图7是根据本发明的第二优选实施例的由图6的格栅阵列组件形成的半导体管芯组件的平面图；
图8是根据本发明的第二优选实施例的由图7的半导体管芯组件形成的半导体管芯格栅阵列封装的横截面侧视图；
图9是根据本发明的第三优选实施例的由图6的格栅阵列组件形成的半导体管芯格栅阵列封装的横截面侧视图；
图10是根据本发明的第四优选实施例的由图6的格栅阵列组件形成的半导体管芯组件的平面图；
图11是根据本发明的第四优选实施例的由图10的半导体管芯组件形成的半导体管芯格栅阵列封装的横截面侧视图；
图12是根据本发明的第五优选实施例的由图6的格栅阵列组件形成的倒装芯片格栅阵列组件的平面图；
图13是根据本发明的第五优选实施例的由图12的倒装芯片格栅阵列组件形成的半导体管芯组件的平面图；
图14是根据本发明的第五优选实施例的由图13的半导体管芯组件形成的半导体管芯格栅阵列封装的横截面侧视图；
图15是示出根据本发明的制造半导体管芯格栅阵列封装的方法的流程图。
具体实施方式
下面陈述的与附图相关的详细说明书意欲作为本发明的目前优选实施例的说明书，并不是意欲表示本发明可被实践的仅有形式。应当理解相同或等同的功能可由意欲包含在本发明的精神和范围内的不同实施例完成。在附图中，相同的数字自始至终被用于表示相同的元件。而且，术语“包括”、“包含”或其任意其他变型意欲涵盖非排他性的包容，以使得模块、电路、器件部件、结构以及包括一系列的元素或步骤的方法步骤，该一系列的元素或步骤不是仅包括那些元素而是可包括没有明确列出或这些模块、电路、器件部件或步骤固有的其它元素或步骤。除非特别限制，由“包括一个”继续描述的元素或步骤并不排除构成该元素或步骤的附加的相同元素或步骤的存在。
在一个实施例中，本发明提供了装配半导体管芯格栅阵列封装的方法。该方法包括提供由其中嵌入有焊料沉积物的电绝缘材料形成的格栅阵列组件。每个焊料沉积物的第一部分暴露在该绝缘材料的第一表面上并且每个焊料沉积物的第二部分暴露在该绝缘材料的相对表面上。半导体管芯安装到该绝缘材料的第一表面。该半导体管芯的电极进而电连接到该焊料沉积物。该管芯和该绝缘材料的第一表面进而覆盖有密封材料。
在另一个实施例中，本发明提供了半导体管芯格栅阵列封装。该格栅阵列封装包括由其中嵌入有焊料沉积物的电绝缘材料形成的格栅阵列组件。每个焊料沉积物的第一部分暴露在该绝缘材料的第一表面上并且每个焊料沉积物的第二部分暴露在该绝缘材料的相对第二表面上。半导体管芯安装到该绝缘材料的第一表面。该半导体管芯具有电连接到该焊料沉积物的电极。密封材料覆盖该半导体管芯和该绝缘材料的第一表面。
在又另一个实施例中，本发明提供了由其中嵌入有焊料沉积物的电绝缘材料形成的格栅阵列组件。每个焊料沉积物的第一部分暴露在该绝缘材料的第一表面上，并且每个焊料沉积物的第二部分暴露在该绝缘材料的相对表面上。第一和第二部分中的一个或两个可从该绝缘材料凸出并还可具有变形的表面。
现在参考图1，根据本发明的第一优选实施例的两部分模具100的横截面侧视图被示出。模具100具有彼此邻接以形成模穴115的上体105和下体110。该模穴115的上表面120具有由上部凹槽125形成的上部焊料沉积物定位阵列，上部凹槽125对准于在该模穴115的下表面135上的下部凹槽130。
如所示出的，焊球140形式的焊料沉积物放置在凹槽125、130中。在这个特定实施例中，该焊球140首先沉积在下部凹槽130中。当该上体105和下体110共同进入邻接啮合时，进而形成该模穴115，凹槽125、130的形状使焊球140变形，如示出的。
图2是根据本发明的第一优选实施例的格栅阵列组件200的横截面侧视图。在模制化合物围绕焊球140模制之后，格栅阵列组件200形成，其中模制化合物是电绝缘材料205。更特别地，格栅阵列组件200在以热流态的电绝缘材料205被移入或注入该模穴115并进而冷却之后形成，如对本领域技术人员来说显而易见的。
正如所示出的，焊球140嵌入电绝缘材料205中。还有，每个焊球140的第一部分210暴露在该绝缘材料205的第一表面215上。类似地，每个焊球140的第二部分220暴露在该绝缘材料205的相对第二表面225上。
图3是根据本发明的第一优选实施例的由格栅阵列组件200形成的半导体管芯组件300的平面图。该半导体管芯组件300包括安装到该电绝缘材料205的第一表面215上的半导体管芯305。该半导体管芯305具有通过接合线315选择性地电连接到焊球140的多个电极310。
图4是根据本发明的第一优选实施例的由半导体管芯组件300形成的半导体管芯格栅阵列封装400的横截面侧视图。该半导体管芯格栅封装400包括覆盖半导体管芯305、接合线315以及该电绝缘材料205的第一表面215的密封材料405。正如本领域技术人员所显而易见的，密封材料405典型地是模制于半导体管芯305和绝缘材料205的模制化合物。还有，为了封装400合适地安装到电路板，每个焊球140的第二部分220从电绝缘材料205的第二表面225凸出。
图5是根据本发明的第二优选实施例的两个部分模具500的横截面侧视图。该模具500具有彼此邻接以形成模穴515的上体505和下体510。该模穴515具有平坦的上表面520以及在该模穴515的下表面535上的凹槽530。
正如所示的，以焊球540形式的焊料沉积物放置在凹槽530中。在这个特定实施例中，该焊球540首先沉积在下部凹槽530中。当该上体505和下体510共同进入邻接啮合，进而形成该模穴515时，凹槽530的形状和平坦的上表面520使焊球540变形，如示出的。
图6是根据本发明的第二优选实施例的格栅阵列组件600的横截面侧视图。在模制化合物围绕焊球540模制之后，格栅阵列组件600形成，其中模制化合物是电绝缘材料605。更特别地，格栅阵列组件600在以热流态的电绝缘材料605被移入或注入该模穴515并进而冷却之后形成，如对本领域技术人员来说显而易见的。
正如所示出的，焊球540嵌入电绝缘材料605中。还有，每个焊球540的第一部分610暴露在该绝缘材料605的第一表面615上。类似地，每个焊球540的第二部分620暴露在该绝缘材料605的相对第二表面625上。
图7是根据本发明的第二优选实施例的由格栅阵列组件600形成的半导体管芯组件700的平面图。该半导体管芯组件700包括安装到该电绝缘材料605的第一表面615上的半导体管芯705。该半导体管芯705具有通过接合线715选择性地电连接到焊球540的多个电极710。
图8是根据本发明的第二优选实施例的由半导体管芯组件700形成的半导体管芯格栅阵列封装800的横截面侧视图。该半导体管芯格栅封装800包括覆盖半导体管芯705、接合线715以及该电绝缘材料605的第一表面615的密封材料805。正如本领域技术人员所显而易见的，密封材料805典型地是模制于半导体管芯705和绝缘材料605的模制化合物。还有，为了封装800合适地安装到电路板，每个焊球540的第二部分620从电绝缘材料605的第二表面625凸出。
图9是根据本发明的第三优选实施例由格栅阵列组件600形成的半导体管芯格栅阵列封装900的横截面侧视图。在这个实施例中，导电电镀区域形成沉积到每个焊球540的第一部分610上的接合焊盘905。该电镀区域典型地包括通过干法电镀工艺沉积到每个第一部分610上的镍和金合金。半导体管芯915安装到该绝缘材料605的第一表面615上。管芯915的多个电极920通过接合线925可选择性地电连接到焊球540。更特别地，接合线925可选择性地接合到接合焊盘905中的任意一个。而且，为了封装900合适地安装到电路板，每个焊球540的第二部分620从电绝缘材料605的第二表面625凸出。
半导体管芯格栅阵列封装900还包括覆盖半导体管芯915、接合线925以及绝缘材料605的第一表面615的密封材料930。正如本领域技术人员所显而易见的，密封材料930典型地是模制于半导体管芯915和绝缘材料605的模制化合物。
图10是根据本发明的第四优选实施例由格栅阵列组件600形成的半导体管芯组件1000的平面图。该半导体管芯组件1000包括安装到该电绝缘材料605的第一表面615上的半导体管芯1005。该半导体管芯1005具有通过接合焊盘1025、导电迹线1020和接合线1015选择性地电连接到焊球540的多个电极1010。在这个实施例中，导电电镀区域形成导电迹线1020并且每个迹线1020的一部分沉积到每个焊球540的第一部分610上去并且每个迹线1020的剩余部分沉积到电绝缘材料605的第一表面615上去。该迹线1020典型地包括通过干法电镀工艺沉积的镍和金合金。而且，电极1010到焊球540的电连接通过接合在导电迹线1020的接合焊盘1025处的接合线1015提供。
图11是根据本发明的第四优选实施例由半导体管芯组件1000形成的半导体管芯格栅阵列封装1100的横截面侧视图。半导体管芯格栅阵列封装1100包括覆盖半导体管芯1005、接合线1015以及绝缘材料605的第一表面615的密封材料1105。正如本领域技术人员所显而易见的，密封材料1105典型地是模制于半导体管芯1005和电绝缘材料605的模制化合物。管芯1005的多个电极1010通过接合线1015可选择性地电连接到焊球540。更特别地，接合线1015可选择地接合到接合焊盘1025中的任意一个。而且，为了封装1100合适地安装到电路板，每个焊球540的第二部分620从电绝缘材料605的第二表面625凸出。
参照图12，根据本发明的第五优选实施例由格栅阵列组件600形成的倒装芯片格栅阵列组件1200的平面图被示出。该倒装芯片格栅阵列组件1200具有形成导电迹线1220的导电电镀区域并且每个迹线1220的一部分沉积到每个焊球540的第一部分610上。每个迹线1220的剩余部分沉积到电绝缘材料605的第一表面615上去。该迹线1220典型地包括通过干法电镀工艺沉积的镍和金合金。还有，迹线1220终止在由与迹线1220集成的导电电镀区域形成的安装垫片1225处。
图13是根据本发明的第五优选实施例由倒装芯片格栅阵列组件1200形成的半导体管芯组件1300的平面图。该半导体管芯组件1300包括安装到该电绝缘材料605的第一表面615上的半导体管芯1305。半导体管芯1305的有源表面面对该电绝缘材料605的第一表面615。还有，该半导体管芯1305的电极通过介于电极和导电迹线1220的相应对准的安装垫片1225之间的焊料接点选择地电连接到焊球540。就这一点而言，电极被定尺寸和安排以与安装垫片1225的位置匹配(反之亦然)。
图14是根据本发明的第五优选实施例由半导体管芯组件1300形成的半导体管芯格栅阵列封装1400的横截面侧视图。半导体管芯格栅阵列封装1400包括覆盖半导体管芯1305以及绝缘材料605的第一表面615的密封材料1405。正如本领域技术人员所显而易见的，密封材料1405典型地是模制于半导体管芯1305和电绝缘材料605的模制化合物。还有示出的管芯1305的多个电极1410，这些电极1410焊接到导电迹线1220的相应对准的安装垫片1225。这种布置因此将电极1410可选择性地电连接到焊球540。而且，为了封装1400合适地安装到电路板，每个焊球540的第二部分620从电绝缘材料605的第二表面625凸出。
图15是示出根据本发明的制造半导体管芯格栅阵列封装的方法1500的流程图。仅为举例的方式，方法1500将参照图1到14的实施例而适当地描述。方法1500包括在方块1510，放置诸如焊球140、540的焊料沉积物在两部分模具100、500的凹槽130、530。
在方块1520处在上体105、505和下体110、510被放在一起以形成模穴115、515之后模制工艺被执行。在模穴115、515形成期间，焊球140、540通过模具100、500的压缩力变形。一旦上体105、505和下体110、510被放在一起，模制化合物被注入或压进模穴115、515中。模制化合物提供围绕焊球140、540模制的电绝缘材料205、605。
在模制工艺期间，通过模具100的焊球140的变形导致第一部分210从电绝缘材料205的第一表面215凸出和第二部分220从电绝缘材料205的第二表面225凸出。还有，变形再成形焊球140以使得第一部分210具有平坦的接合表面并且第二部分220具有平坦的安装表面。与此相反，在模制工艺期间，通过模具500的焊球540的变形导致第一部分610具有与电绝缘材料605的第一表面615同一平面(齐平)和第二部分620从电绝缘材料605的第二表面625凸出。还有，变形使焊球540成形以使得第二部分620具有平坦的安装表面。
在方块1520的模制工艺完成之后，格栅阵列组件200、600被形成并提供给安装方块1530。正如本领域技术人员所显而易见的，格栅阵列组件200、600可被加工处理，通过选择性地沉积导电电镀区域到每个焊球140、540的第一部分上去。还有，每个电镀区域可包括导电迹线1020、1220以及在绝缘材料的第一表面上的相应的接合焊盘1025、1225。
在安装模块1530处，半导体管芯305、705通过环氧树脂安装到绝缘材料的第一表面上。进而，在方块1540处，管芯305、705的电极310、710各自地电连接到焊球140、540。在某些实施例中，电极310、710通过接合线315、715选择性地连接到焊球140、540。还有，在某些实施例中焊球140、540掺杂有材料(诸如铋)以增加它们的硬度。当接合线315、715直接接合到焊球140、540时这种掺杂特别有用。在其它实施例中，选择性的电连接通过选择性地接合到诸如垫片905、1025的每个电镀区域的接合线提供。还有，在进一步的实施例中，半导体管芯的有源表面面对由组件1300这样提供的绝缘材料的第一表面。因而，选择性的电连接通过介于电极1410和相应对准的安装垫片1225之间的焊接接点提供。
在方块1550处方法1500执行用密封材料覆盖半导体管芯305、705和绝缘材料205、605的第一表面215、615。当格栅阵列组件200、600集成进这样的组件的大片中时，在方块1560处分离被执行以提供半导体管芯格栅阵列封装400、800、900、1100或1400。
有利地，本发明减轻了衬底作为半导体管芯格栅阵列封装的集成部分的要求。这样的衬底具有迹线并且通过导电过孔其安装凸出焊料沉积物并且因此增加了格栅阵列封装的厚度。因而本发明可减轻制造的复杂性并可能减小封装厚度。
本发明的优选实施例的说明书为了示例或说明的目的而被提供，但不意欲详尽地或限定发明为公开的形式。本领域技术人员应当意识到在不脱离发明宗旨的范围内能够进行变型。因此，应当理解本发明不限于公开的特定实施例，但涵盖了由附属的权利要求书限定的本发明的精神和范围内的变形。

Claims (16)

1.一种装配半导体管芯格栅阵列封装的方法，该方法包括：
提供由其中嵌入有焊料沉积物的电绝缘材料形成的格栅阵列组件，其中每个焊料沉积物的第一部分暴露在该绝缘材料的第一表面上并自第一表面凸出，并且每个焊料沉积物的第二部分暴露在该绝缘材料的相对表面上；
将半导体管芯安装到该绝缘材料的第一表面；
将该半导体管芯的电极电连接到该焊料沉积物；以及
用密封材料覆盖该半导体管芯和该绝缘材料的第一表面；
其中半导体管芯的电极与焊料沉积物之间的电连接通过接合线提供。
2.根据权利要求1所述的方法，其中提供格栅阵列组件包括：
将该焊料沉积物放置在模具中；以及
在该焊料沉积物的周围模制该电绝缘材料。
3.根据权利要求2所述的方法，其中该焊料沉积物是焊球。
4.根据权利要求3所述的方法，进一步包括使该焊料沉积物的第一部分和第二部分中的至少一个变形。
5.根据权利要求2所述的方法，其中每个焊料沉积物的第二部分从该绝缘材料的第二表面凸出。
6.根据权利要求2所述的方法，其中模具包括第一部分，第一部分具有多个凹槽，其中多个凹槽的每一个容纳每个焊料沉积物的第一部分。
7.根据权利要求2所述的方法，进一步包括选择性地沉积导电电镀区域到每个焊料沉积物的第一部分上。
8.根据权利要求7所述的方法，其中每个电镀区域包括在绝缘材料的第一表面上的导电迹线。
9.根据权利要求8所述的方法，其中该接合线选择性也接合到每一个所述电镀区域。
10.根据权利要求8所述的方法，其中在执行安装之后，半导体管芯的有源表面面对绝缘材料的第一表面，并且该选择性的电连接通过介于电极和导电迹线的相应的对准的安装垫片之间的焊料接合点提供。
11.一种半导体管芯格栅阵列封装，包括：
由其中嵌入有焊料沉积物的电绝缘材料形成的格栅阵列组件，其中每个焊料沉积物的第一部分暴露在该绝缘材料的第一表面上并自第一表面凸出，并且每个焊料沉积物的第二部分暴露在该绝缘材料的相对第二表面上；
安装到该绝缘材料的第一表面的半导体管芯，该半导体管芯具有选择性地电连接到该焊料沉积物的多个电极，其中半导体管芯的电极与焊料沉积物之间的电连接通过接合线提供；以及
覆盖该半导体管芯和该绝缘材料的第一表面的密封材料。
12.根据权利要求11所述的半导体管芯格栅阵列封装，其中电绝缘材料是在该焊料沉积物周围模制的模制化合物。
13.根据权利要求12所述的半导体管芯格栅阵列封装，其中每个焊料沉积物的第二部分从该绝缘材料的第二表面凸出。
14.根据权利要求12所述的半导体管芯格栅阵列封装，包括沉积在每个焊料沉积物的第一部分上的导电电镀区域。
15.根据权利要求14所述的半导体管芯格栅阵列封装，其中每个导电电镀区域包括在绝缘材料的第一表面上的导电迹线。
16.根据权利要求15所述的半导体管芯格栅阵列封装，其中半导体管芯的有源表面面对绝缘材料的第一表面，并且电极通过介于电极和导电迹线的相应的对准的安装垫片之间的焊料接合点选择性地电连接到焊料沉积物。
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