CN107768351A - 具有热机电芯片的半导体封装件及其形成方法 - Google Patents
具有热机电芯片的半导体封装件及其形成方法 Download PDFInfo
- Publication number
- CN107768351A CN107768351A CN201710587367.1A CN201710587367A CN107768351A CN 107768351 A CN107768351 A CN 107768351A CN 201710587367 A CN201710587367 A CN 201710587367A CN 107768351 A CN107768351 A CN 107768351A
- Authority
- CN
- China
- Prior art keywords
- layer
- tem
- hole
- tube core
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3738—Semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/041—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
- H01L25/043—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1094—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10252—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1027—IV
- H01L2924/10271—Silicon-germanium [SiGe]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/1033—Gallium nitride [GaN]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10337—Indium gallium arsenide [InGaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/142—HF devices
- H01L2924/1421—RF devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1432—Central processing unit [CPU]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/14335—Digital signal processor [DSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1436—Dynamic random-access memory [DRAM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
在一些实施例中,器件包括热机电(TEM)芯片,具有功能电路;第一管芯,附接至所述TEM芯片的第一侧面;第一通孔,位于所述TEM芯片的第一侧面上并且邻近所述第一管芯,所述第一通孔电连接至所述TEM芯片。所述器件还包括第一模制层,围绕所述TEM芯片、所述第一管芯和所述第一通孔,其中,所述第一管芯的上表面和所述第一通孔的上表面与所述第一模制层的上表面平齐。所述器件还包括第一再分布层,位于所述第一模制层的上表面上方并且电连接至所述第一通孔和所述第一管芯。本发明还提供了具有热机电芯片的半导体封装件及其形成方法。
Description
技术领域
本发明的实施例一般地涉及半导体技术领域,更具体地,涉及半导体封装件及其形成方法。
背景技术
由于许多电子元件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的不断提高,半导体工业经历了快速发展。在大多数情况下,这种集成度的提高源自最小特征尺寸的不断减小,这使得更多的部件集成在给定的区域内。随着最近对甚至更小的电子器件的需求增长,对于更小和更具创造性的半导体管芯的封装技术的需求也在增加。
这些封装技术的实例是叠层封装(POP)技术。在PoP封装件中,顶部半导体封装件堆叠在底部半导体封装件的顶部上,以允许高集成度和高部件密度。这种PoP技术的高集成度能够生产具有增强功能和小占用面积的半导体器件。
由于半导体封装件的不同材料的热膨胀系数(CTE)的失配,可能发生半导体封装件的翘曲。如果保持不控制,翘曲可能会损坏半导体封装件并导致半导体制造的产量降低。在本领域中需要具有减小翘曲的半导体封装件的结构和制造方法。
发明内容
根据本发明的一方面,提供了一种半导体封装器件,包括:热机电(TEM)芯片,具有功能电路;第一管芯,附接至所述TEM芯片的第一侧面;第一通孔,位于所述TEM芯片的第一侧面上并且邻近所述第一管芯,所述第一通孔电连接至所述TEM芯片;第一模制层,围绕所述TEM芯片、所述第一管芯和所述第一通孔,其中,所述第一管芯的上表面和所述第一通孔的上表面与所述第一模制层的上表面平齐;以及第一再分布层,位于所述第一模制层的上表面上方并且电连接至所述第一通孔和所述第一管芯。
根据本发明的另一方面,提供了一种半导体封装件,包括:热机电(TEM)管芯,嵌入第一模制层中,所述TEM管芯具有位于所述TEM管芯的第一侧面上的第一接合焊盘;垂直连接件,位于所述第一模制层中并且位于所述TEM管芯的第一侧面上,其中,所述垂直连接件电连接至所述第一接合焊盘并且从所述TEM管芯的第一侧面延伸至所述第一模制层的第一侧面;第一半导体管芯,位于所述第一模制层中以及位于所述TEM管芯的第一侧面上,其中,所述第一半导体管芯具有位于所述第一半导体管芯的第一侧面上的第二接合焊盘,其中,与所述第一半导体管芯的第一侧面相对的所述第一半导体管芯的第二侧面面对所述TEM管芯的第一侧面;以及第一再分布层,位于所述第一模制层的第一侧面上并且电连接至所述垂直连接件和所述第二接合焊盘。
根据本发明的又一方面,提供了一种形成封装器件的方法,包括:将热机电(TEM)管芯附接至载体,所述TEM管芯具有功能电路;在所述TEM管芯的第一表面上方形成第一通孔,所述第一通孔与所述TEM管芯电连接;将第一管芯附接至所述TEM管芯的第一表面并且邻近所述第一通孔;在所述载体上方形成第一模制层,所述第一模制层环绕所述TEM管芯、所述第一管芯和所述第一通孔,其中,所述第一模制层的第一表面与所述第一管芯的上表面和所述第一通孔的上表面平齐;以及在所述第一模制层的第一表面上方形成第一再分布层,所述第一再分布层电连接至所述第一管芯和所述第一通孔。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以最好地理解本发明的各个方面。应该注意,根据工业中的标准实践,各种部件没有被按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增加或减少。
图1A和图1B分别示出了根据实施例的处于某一制造阶段的具有热机电(TEM)芯片的半导体封装件的顶视图和截面图。
图2至图7示出了根据实施例的处于各个制造阶段的具有TEM芯片的多堆叠(MUST)封装件的截面图。
图8至图18示出了根据另一实施例的处于各个制造阶段的具有TEM芯片的MUST封装件的截面图。
图19示出了根据实施例的具有TEM芯片的多堆叠叠层封装(MUST-POP)半导体封装件的截面图。
图20示出了根据实施例的具有TEM芯片的集成扇出(InFO,又称集成多输出)封装件的截面图。
图21示出了根据实施例的具有TEM芯片的集成扇出叠层封装(InFO-POP)半导体封装件的截面图。
图22示出了根据实施例的具有TEM芯片的集成扇出多芯片(InFO-M)封装件的截面图。
图23示出了根据实施例的具有TEM芯片的集成扇出多芯片叠层封装(InFO-M POP)半导体封装件的截面图。
图24示出了根据实施例的用于形成半导体封装件的流程图。
具体实施方式
以下公开内容提供了许多不同实施例或实例,用于实现所提供主题的不同特征。以下描述组件和布置的具体实例以简化本发明。当然,这些仅仅是实例而不旨在进行限制。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例,也可以包括在第一部件和第二部件之间形成附加部件使得第一部件和第二部件不直接接触的实施例。
而且,为便于描述,在此可以使用诸如“在...之下”、“在...下方”、“下部”、“在...之上”、“上部”等的空间相对位置术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对位置术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位),并且在本文中使用的空间相对位置关系描述符可以同样地作相应地解释。
图1A和图1B分别示出了某一制造阶段的具有热机电(TEM)芯片110的半导体封装件100的顶视图和截面图。图1B是图1A所示的半导体封装件100沿线B-B的截面图,并且图1A是图1B所示的半导体封装件的顶视图。
参考图1A和图1B,管芯120(也称为半导体管芯、芯片、集成电路(IC)或IC管芯)通过诸如胶层或管芯附接膜(DAF)的介电粘合层121附接到TEM芯片110(也称为TEM管芯)的上表面110U。垂直连接件229也可被称为通孔,形成在TEM芯片110的上表面110U上并且电连接到TEM芯片110。模制层130围绕TEM芯片110、管芯120和垂直连接件229。通孔133可以形成为延伸穿过模制层130。注意,为了清楚起见,在图1A中未示出设置在TEM芯片110的上表面110U上的模制层130的部分。图1B还示出了TEM芯片110的下表面110L上的介电层111,该介电层111可以是胶层或DAF。在一些实施例中,例如再分布层(RDL)(未示出,例如参见图4中的RDL 250)的附加的层或结构可以形成在模制层130的上表面130U上方,并且电连接到管芯120、通孔133和TEM芯片110(例如,通过垂直连接件229)。
在一些实施例中,TEM芯片110是包括刚性材料(例如,Si、Ge、SiGe、GaN、GaAs或InGnAs)的半导体管芯,该刚性材料具有小CTE(例如,CTE<3ppm/℃)。如下文更详细讨论的,TEM芯片110的小CTE有助于减少半导体封装的翘曲。在本发明中,TEM芯片110具有在其中的功能电路,该功能电路包括形成在半导体衬底(例如,Si)中/上并且通过导线和/或通孔互连的电子器件(例如,有源器件和/或无源器件),以执行某些设计功能。例如,TEM芯片110可以包括有源器件(例如晶体管)和/或无源器件(例如电阻器、电容器、电感器),该有源器件和/或无源器件形成在硅(Si)衬底中/上并且通过在衬底上的金属层中所形成的互连结构连接。
例如,TEM芯片110可以是逻辑管芯(例如,中央处理单元、微控制器等)、存储器管芯(例如,动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如,电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯,微机电系统(MEMS)管芯、信号处理管芯(例如,数字信号处理(DSP)管芯)、前端管芯(例如,模拟前端(AFE)管芯),及其组合等。
在一些实施例中,TEM芯片110的厚度T在约50μm到约250μm的范围内(参见图1B)。在其它实施例中,TEM芯片110的厚度T在约50μm到约150μm的范围内,但是其它尺寸也是可能的。根据实施例,TEM芯片110的下部(例如,靠近TEM芯片110的下表面110L的部分)包括刚性块状材料,例如块状硅。在一些实施例中,TEM芯片110的下部包括TEM芯片110的总厚度T的约90%以上。在以上所示的实施例中,电子器件(例如,晶体管、电阻器、电容器、电感器)形成在TEM芯片110的顶部(靠近上表面110U的部分)中。在一些实施例中,TEM芯片110的顶部包括TEM芯片110的总厚度T的约10%以下。例如,有源器件可以形成在TEM芯片110的顶部中,该顶部的厚度可以为大约5μm到大约10μm。作为另一示例,无源器件可以形成在TEM芯片110的顶部中,该顶部可具有约20μm到约30μm的厚度。
如图1A所示,TEM芯片110的表面区域大于附接到TEM芯片110的管芯120的表面区域。例如,在图1A的顶视图中,管芯120设置在TEM芯片110的边界内。在其它实施例中,一个以上的管芯120附接到TEM芯片110的上表面110U(参见例如图17、图22和图23及其描述),在这种情况下,TEM芯片110的表面区域大于附接到TEM芯片110的表面(例如,其上形成有接合焊盘的上表面110U)的所有管芯120的表面区域之和。TEM芯片110的大表面区域可以对应于TEM芯片110的大尺寸(例如,体积),从而可以有利地减少如下所述的半导体封装100的翘曲。例如,TEM芯片110的表面区域(例如,上表面110U的面积)可以比管芯120的表面区域(例如,上表面区域或下表面区域)大约1.1至约5倍。在两个或更多管芯附接在TEM芯片110的上表面的情况下,TEM芯片110的表面区域为两个或更多管芯的表面区域的总和的约1.1至约5倍。在一些实施例中,TEM芯片的体积介于半导体封装件100的总体积的50%至约95%之间。
随着集成度的提高,芯片尺寸继续缩小,半导体封装件的扇出比(例如,半导体封装件的表面区域与半导体封装件内的半导体芯片的表面区域的比率)可能增加。这是因为随着芯片尺寸(例如体积)的减小,半导体封装件中的模制材料的相对量(例如,体积的百分比)可能必须增加以提供足够的表面区域,从而容纳互连结构(例如,RDL和模制通孔)和半导体封装件的外部连接件。由于在半导体封装件中使用大量(相对的)模制材料的以及高CTE的模制材料,大的扇出比可能引起过度的晶圆级和封装级翘曲。例如,当模制材料固化时,可能会发生显著的收缩,这可能导致晶圆级或封装级的大翘曲,甚至损坏半导体封装件。因此,利用大尺寸(例如,体积)的TEM芯片110,TEM芯片110在半导体封装件100中占据先前被模制层130占据的空间,从而减少半导体封装件100中的模制材料的量,这转而可以减少半导体封装件的翘曲。
另外,TEM芯片110由小CTE的刚性材料(例如,Si)制成。因此,大的TEM芯片110有助于减小半导体封装件100的整体CTE。此外,由于管芯120附接到TEM芯片110的上表面110U,所以TEM芯片110的刚性结构用作模板(template)并且在热循环期间迫使管芯120保持平直(例如不翘曲)。
如图1A所示,在一些实施例中,TEM芯片110具有1:1的纵横比(例如,在图1A中的X轴和Y轴方向上具有相同尺寸)。例如,在图1A的顶视图中,TEM芯片110具有正方形形状。TEM芯片110的1:1纵横比可以减轻不对称封装件的翘曲。在传统的半导体封装件中,当由半导体封装件的模制材料封装的芯片不具有1:1的纵横比(例如,在顶视图中具有矩形形状)时,由于在封装件的X方向和Y方向上不同量的模制材料,不对称封装件的翘曲可能发生。半导体封装件100中具有纵横比为1:1的TEM芯片110减小了封装件的X方向和Y方向上模制材料的不对称性,从而减小了不对称性封装件的翘曲。虽然1:1纵横比可以是目标纵横比,但是应当理解,由于诸如设计约束和制造精度的各种因素,TEM芯片110可以具有接近1:1的纵横比(例如,略大于1:1或略小于1:1)。纵横比的这些变化完全旨在包括在本发明的范围内。
如图1A和1B所示,垂直连接件229形成在TEM芯片110的上表面110U上并电连接到TEM芯片110。在一些实施例中,垂直连接件229通过TEM芯片110的上表面110U上的接合焊盘(图1A和图1B中未示出,参见图3中的接合焊盘223)电连接到TEM芯片110。在所示实施例中,在TEM芯片110的上表面110U并且沿着TEM芯片110的周边(例如,侧壁)形成垂直连接件229,并且TEM芯片110的上表面110U的中心区域没有垂直连接件229,因此保留了用于附接管芯120的中心区域的空间。
TEM芯片110通过垂直连接件229电连接到其它芯片、封装件或电源(例如,电压源和电接地)。注意,管芯120通过介电层121(例如胶层或DAF)附接到TEM芯片110的上表面110U。因此,在TEM芯片110的上表面110U和管芯120之间不形成外部连接件或焊点。在一些实施例中,管芯120的有源侧(例如,具有用于电连接的接合焊盘的侧面)与模制层130的上表面130U以及垂直连接件229和通孔133的上表面平齐。在一些实施例中,在上表面130U上随后形成的RDL(参见图4中的RDL 250)电连接到TEM芯片110(例如,通过垂直连接件229)、管芯120和通孔133。
与模制通孔133相比较,其中,该模制通孔133具有与模制层130的厚度相等的高度H(例如,通孔133从模制层130的下表面130L延伸到上表面130U),垂直连接件229具有较小的高度Hv,并且从TEM芯片110的上表面110U延伸到模制层130的上表面130U。在一些实施例中,垂直连接件229的宽度W1小于模制通孔133的宽度W6。下面参考图3描述垂直连接件229的形成方法。
例如,管芯120可以是任何合适的半导体管芯,例如逻辑管芯、存储管芯、电源管理管芯、RF管芯、传感器管芯、MEMS管芯、信号处理管芯、前端管芯及其组合。在本发明的其他实施例中,半导体封装件可以在图1A和图1B所示的管芯120的位置附接到TEM芯片110。附接到TEM芯片110的半导体封装件可以包括封装在模制材料中的一个或多个管芯,并且可以包括在半导体封装件的模制材料上的RDL和在半导体封装件的模制材料中的模制通孔。在所示实施例中,与TEM芯片110的尺寸相比,附接到TEM芯片110的半导体封装件的尺寸(例如,表面区域和/或体积)很小(例如,半导体封装件的体积在TEM芯片110的体积的约20%至约70%之间),使得TEM芯片110仍然主导(dominate,又称支配)半导体封装件100并提供减小翘曲的优点。因此,无论是晶圆120还是半导体封装件被附接到TEM芯片110,TEM芯片110的优点都适用。因此,在下文的描述中,在各种实施例中,半导体管芯(例如,图1A/1B中的管芯120,图3中的管芯230和图16中的管芯370/380)用于附接到相应的TEM芯片,应该理解,半导体封装件也可以用于代替半导体管芯以形成如本发明的各个实施例所示的各种封装件(例如,MUST封装件、MUST-PoP封装件)。
图2至图7示出了根据实施例的处于各个制造阶段的具有TEM芯片的多堆叠(MUST)封装件200的截面视图。为了简单起见,在图2至图7中仅示出了一个MUST封装件,可以理解,可以在载体210上形成数十个、数百个、甚至数千个半导体封装件200。在以下的描述中,热机电芯片明确地被称为TEM芯片。
参考图2,TEM芯片110通过载体210的第一区域中的介电粘合层211附接到载体210,并且管芯240通过载体210的第二区域中的另一介电粘合层212附接到载体210。载体210可以包含诸如硅、聚合物、聚合物复合材料、金属箔、陶瓷、玻璃、玻璃环氧树脂、氧化铍、胶带的基底材料或用于结构支撑的其它合适材料。在一些实施例中,载体210由玻璃制成。在一些实施例中,粘合层211和粘合层212可沉积或层压在载体210上。粘合层211或粘合层212可以是光敏材料,并且在随后的载体脱粘工艺(de-bonding process,又称去接合工艺)中通过紫外(UV)光照射在载体210上而容易地与载体210分离。例如,粘合层211或粘合层212可以是由圣保罗,明尼苏达州的3M公司制造的光热转换(LTHC)涂层。
如图2更详细地所示,TEM芯片110包括具有形成在其中电路的一个或多个半导体层221、与TEM芯片110的电路电连接的接合焊盘223、以及在接合焊盘223和一个或多个半导体层221上方的钝化层225。在一些实施例中,TEM芯片110还包括电连接到接合焊盘223的导电焊盘227。导电焊盘227可以附加地包括横向延伸到TEM芯片110的周边(例如,侧壁)的部分,该部分有时被称为导电路径226。
在粘合至粘合层211之前,可以根据适用的制造工艺处理TEM芯片110,以在TEM芯片110中形成集成电路。例如,有源器件(例如晶体管)和/或无源器件(例如电阻器、电容器、电感器)形成在具有低CTE(例如,小于3ppm/℃)的刚性衬底(例如,Si)中/之上,并且通过在衬底上的金属层中所形成的互连结构(例如,导线和通孔)互连,以形成集成电路。
如图2所示,TEM芯片110还包括制造为与外部电连接的接合焊盘223,例如铝焊盘或铜焊盘。接合焊盘223位于TEM芯片110的有源侧并且电连接到TEM芯片110的集成电路。钝化层225位于TEM芯片110的有源侧以及接合焊盘223的一部分上方。开口穿过钝化层225到达接合焊盘223。导电焊盘227(例如,包括诸如铜的金属)位于穿过钝化层225的开口中,并且机械地和电连接到相应的接合焊盘223。可以通过例如电镀等形成导电焊盘227。导电焊盘227通过诸如焊盘223电连接到TEM芯片110的集成电路。
在一些实施例中,钝化层225位于TEM芯片110的有源侧,并且与TEM芯片110横向具有共同边界(coterminous)。尽管钝化层225在图2中被示出为一层,但是钝化层225可以包括多个子层,并且可以包括诸如PBO、聚酰亚胺、BCB等的聚合物;诸如氮化硅等的氮化物;诸如氧化硅、PSG、BSG、BPSG的氧化物;或它们的组合,并且可以例如通过旋涂、层压、CVD等形成钝化层225。
如图2所示,半导体管芯240通过介电粘合层212附接到载体210的与TEM芯片110相同侧面。管芯240可以包括具有电子器件(例如,晶体管,电阻器,电容器和电感器)的一个或多个半导体层241、形成在其上或其中的互连结构、钝化膜243、介电材料245和管芯连接件247。例如,半导体管芯240可以是任何合适的半导体管芯,例如逻辑管芯、存储管芯、电源管理管芯、RF管芯、传感器管芯、MEMS管芯、信号处理管芯、前端管芯及其组合。
在粘合至介电粘合层212之前,可以根据适用的制造工艺处理集成电路管芯240以在集成电路管芯240中形成集成电路。例如,集成电路管芯240包括在一个或多个半导体层241中的半导体衬底。半导体衬底可以包括掺杂或未掺杂的硅,或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括:其他半导体材料,诸如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。还可以使用其他衬底,诸如多层或梯度衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底中和/或上,并且可以通过互连结构互连器件以形成集成电路,其中,通过诸如半导体衬底上的一个或多个介电层中的金属化图案来形成互连结构。
半导体管芯240还包括制造为与外部电连接的接合焊盘,诸如铝焊盘或铜焊盘。接合焊盘位于可以称为集成电路管芯240的有源侧的一侧上。钝化膜243位于集成电路管芯240上以及接合焊盘的部分上。开口穿过钝化膜243到达接合焊盘。管芯连接件247(例如,包括诸如铜的金属)位于穿过钝化膜243的开口中并且机械地和电连接至相应的接合焊盘。例如,可以通过电镀等形成管芯连接件247。管芯连接件247电连接至管芯240的集成电路。
介电材料245位于集成电路管芯240的有源侧上,例如位于钝化膜243和管芯连接件247上。介电材料245横向封装管芯连接件247,并且介电材料245与集成电路管芯240横向具有共同边界(coterminous)。介电材料245可以是诸如PBO、聚酰亚胺、BCB等的聚合物;诸如氮化硅等的氮化物;诸如氧化硅、PSG、BSG、BPSG等的氧化物;或它们的组合,并且可以例如通过旋涂、层压、CVD等形成该介电材料。
粘合层212的材料及形成方法可以类似于粘合层211的材料及形成方法。具体细节这里不再重复。
接下来,如图3所示,TEM芯片110的垂直连接件229形成在导电路径226上,并且另一个半导体管芯230通过介电粘合层228附接到TEM芯片110的有源侧。在其他实施例(未单独示出)中,垂直连接件229形成在直接位于接合焊盘223上方的导电焊盘227的部分上。尽管图3中示出一个垂直连接件229,但是可形成两个或多个垂直连接件229。作为形成垂直连接件229的实例,在钝化层225上方形成晶种层(未示出)。在一些实施例中,该晶种层是金属层,该金属层可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如,可以使用PVD等形成晶种层。然后在晶种层上形成并图案化光刻胶。可通过旋涂等形成光刻胶并且可将该光刻胶曝光于图案化的光。光刻胶的图案对应于垂直连接件229。图案化形成穿过光刻胶的开口以暴露晶种层。导电材料形成在光刻胶的开口中以及晶种层的暴露部分上。可以通过诸如电镀或化学镀等的镀敷来形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。然后,去除光刻胶以及晶种层的其上未形成导电材料的部分。可通过可接受的灰化或剥离工艺去除光刻胶,诸如使用氧等离子体等。一旦去除光刻胶,诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成垂直连接件229。在其他实施例中,不使用晶种层,并且在要形成垂直连接件229的位置处,将导电材料镀在导电焊盘227或导电路径226上(例如,当导电焊盘227或导电路径226包括铜时)。在所示实施例中,在管芯230附接到TEM芯片110之前形成垂直连接件229。在其它实施例中,在管芯230附接到TEM芯片110之后形成垂直连接件229。
例如,半导体管芯230可以是任何合适的半导体管芯,例如逻辑管芯、存储管芯、电源管理管芯、RF管芯、传感器管芯、MEMS管芯、信号处理管芯、前端管芯及其组合。半导体管芯230附接到TEM芯片110,其中管芯230的有源侧朝上(例如,远离TEM芯片110)。半导体管芯230和粘合层228的材料和形成方法可以分别类似于半导体管芯240和粘合层211的材料和形成方法。具体细节这里不再重复。
接下来,如图4所示,第一模制层215形成在载体210上方,并且包围TEM芯片110、管芯230,管芯240以及TEM芯片110的垂直连接件229。在一些实施例中,第一模制层215的厚度与TEM芯片110的厚度、管芯230的厚度、介电粘合层211的厚度和介电粘合层228的厚度之和相同,其中沿与厚度TM相同的方向测量厚度。如图4所示,第一模制层215的上表面215U与管芯230的上表面(例如,管芯230的管芯连接件237的上表面)和管芯240的上表面(例如,管芯240的管芯连接件247的上表面)平齐。随后,RDL 250形成在第一模制层215、TEM芯片110、管芯230、管芯240以及TEM芯片110的垂直连接件229上方。
第一模制层215可以是模塑料、环氧树脂等,并且可以通过压缩模制、传递模制等来施加第一模制层。在固化后,第一模制层215可以进行诸如化学机械平面化(CMP)工艺的研磨工艺,以露出垂直连接件229、管芯连接件237和管芯连接件247。在研磨工艺之后,垂直连接件229的上表面、管芯连接件237的上表面、管芯连接件247的上表面和第一模制层215的上表面是共面的。在一些实施例中,例如,如果垂直连接件229、管芯连接件237和管芯连接件247已经露出,则可以省略研磨工艺。
在图4中,在第一模制层215、垂直连接件229、管芯230和管芯240上方形成RDL250。RDL 250包括一个或多个介电层255以及形成在一个或多个介电层255内的诸如导线251和/或通孔253的导电部件。RDL 250的导电部件可以延伸超出管芯230、管芯240和TEM芯片110的边界(例如,外部周边或侧壁),从而能够实现管芯230、管芯240和TEM芯片110的扇出。在一些实施例中,RDL 250的导电部件电连接到管芯230(例如,通过管芯连接件237)、管芯240(例如,通过管芯连接件247)和TEM芯片110(例如,通过垂直连接件229),并且可以提供管芯230、管芯240和TEM芯片110之间的电连接。另外,RDL 250的导电部件可以包括靠近RDL 250的上表面的接触焊盘252,以用于与后续工艺中形成的其它导电部件(例如,图5中的通孔269)电连接。
RDL 250的介电层255可以通过诸如旋涂、CVD、等离子体增强CVD(PECVD)和/或层压的任何合适的方法,由例如低介电常数(低K)介电材料、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟化硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、PBO、聚酰亚胺、BCB及其化合物、其复合物、及其组合等形成。例如,导线251和导电通孔253可以包括诸如铜、铜合金、其它金属或合金,或其组合或其多层,并且可以使用诸如减蚀刻和/或镶嵌技术形成。例如,可以使用一个或多个溅射工艺、光刻工艺、镀工艺和光刻胶剥离工艺来形成导线251和导电通孔253。也可以使用其他方法来形成RDL 250的导电部件。
接下来,在图5中,通孔269形成在RDL 250上方并且电连接到RDL250的导电部件。通孔269的材料和形成方法可以类似于TEM芯片110的垂直连接件229的材料和形成方法。注意,与从TEM芯片110的有源侧延伸到相应模制层(例如,第一模制层215)的上表面的垂直连接件229不同,通孔269从相应的模制层的接触RDL 250的第一表面延伸(例如,图7中的第二模制层259)到相应模制层的与第一表面相对的第二表面。在一些实施例中,通孔269的高度H2与围绕通孔269的第二模制层259(见图7)的厚度H2相同。在所示的实施例中,通孔269的宽度W2大于垂直连接件229的宽度W1,但是W2根据例如形成通孔时使用的光刻胶的纵横比也可以等于或小于W1。
在图6中,半导体管芯260通过诸如粘合层257的介电层附接到RDL250,其中管芯260的有源面背离(又称背对着)RDL 250。例如,管芯260可以是任何合适的半导体管芯,例如逻辑管芯、存储管芯、电源管理管芯、RF管芯、传感器管芯、MEMS管芯、信号处理管芯、前端管芯及其组合。半导体管芯260和粘合层257的材料和形成方法可以分别类似于半导体管芯240和粘合层211的材料和形成方法。具体细节这里不再重复。
接下来,在图7中,第二模制层259形成在RDL 250上方。第二模制层259围绕通孔269和半导体管芯260。沉积的第二模制层259可以经历固化工艺和平坦化工艺以暴露通孔269和管芯260的管芯连接件267。第二模制层259的材料和形成方法可以与第一模制层215的材料和形成方法相似,具体细节这里不再赘述。
在形成第二模制层259之后,RDL 270形成在第二模制层259、通孔269和管芯260上。如图7所示,RDL 270包括诸如介电层271,介电层273和介电层275的多个介电层,以及诸如导线276和导线272的导电部件。在所示的实施例中,导线272通过诸如镀工艺共形地形成在介电层273的凹部(例如,由导线272部分填充的凹部)中。RDL 270还可以包括靠近RDL270的上表面的接触焊盘,用于与其他器件或封装件的电连接。在所示实施例中,RDL 270包括靠近RDL 270的上表面的凸块下金属化(UBM)结构278。尽管图7中示出了三个介电层271/273/275,但是在RDL 270中可以形成任何数量的介电层和任何数量的导线。
如图7所示,连接件280通过例如UBM 278电连接到RDL 270。连接件280可以放置在UBM 278上,并且可以是包括诸如焊球的共晶材料的球栅阵列(BGA),但是也可以使用任何合适的材料。在连接件280是焊球的实施例中,可以使用诸如直接落球工艺的落球法来形成连接件280。可选地,可以通过以下步骤来来形成焊球:首先通过诸如蒸发、电镀、印刷、焊料转移的任何合适的方法形成锡层,和然后实施回流以将材料成形为期望的凸块形状。一旦已经形成连接件280,就可以执行测试以确保该结构适合于进一步处理。
可以在图7所示的处理之后进行附加处理。例如,图7所示的MUST封装件200可以经受载体脱粘工艺,以从MUST封装件200移除载体210。作为另一示例,可以在载体脱粘工艺之后进行切割工艺。在一些实施例中,切割将形成在载体210上的多个半导体封装件分割为单独的封装件。
图8至图18示出了根据另一实施例的处于各个制造阶段的具有TEM芯片的多堆叠(MUST)封装件300的截面图。为了简单起见,在图8至图18中仅示出了一个MUST封装件,其中可以理解,可以在载体310上形成数十个、数百个、甚至数千个半导体封装件。
参考图8,作为示例,使用旋涂、层压或其它方法在载体310上方形成介电层313,例如粘合层或聚合物基缓冲层。通孔329形成在介电层313上方。在一些实施例中,通孔329的材料和形成方法类似于图5中通孔269的材料和形成方法。
在图9中,半导体管芯320通过例如介电粘合层315附接到介电层313。在实施例中,介电粘合层315的材料和形成方法类似于图2中的介电粘合层211的材料和形成方法。在一些实施例中,半导体管芯320设置在通孔329之间,其中管芯320的有源侧(例如,具有接合焊盘323的侧面)背离介电层313。
接下来,如图10所示,在介电层313上方形成第一模制层328。第一模制层328包围通孔329和管芯320。第一模制层328可以在沉积之后固化,并且可以进一步经受平坦化工艺(例如,CMP工艺)以获得与通孔329的上表面和管芯320的上表面平齐的平坦上表面。随后,RDL 330形成在第一模制层328、通孔329和管芯320上方。RDL 330包括形成在一个或多个介电层335中的导线331和/或导电通孔333。在实施例中,RDL 330的材料和形成方法类似于图5中的RDL 250的材料和形成方法。在各种实施例中,RDL 330电连接到通孔329和管芯320,并且可以提供管芯320和通孔329之间的电连接。
参考图11,通孔349形成在RDL 330上方。在一些实施例中,通孔349电连接到RDL330。在一个实施例中,通孔349的材料和形成方法类似于图5中的通孔269的材料和形成方法。在所示的实施例中,通孔329的宽度W3大于通孔349的宽度W4,但是根据例如用于形成通孔中的光刻胶的纵横比,W3也可以等于或小于W4。
接下来,如图12所示,管芯340和管芯346均通过介电粘合层附接到RDL 330。在实施例中,介电粘合层的材料和形成方法类似于图2中的介电粘合层211的材料和形成方法。如图12所示,管芯340和管芯346的有源面背离RDL 330。
接下来,如图13所示,第二模制层348形成在RDL 330上。第二模制层348围绕通孔349、管芯340和管芯346。第二模制层348可以在沉积之后固化,并且可以进一步经受平坦化工艺(例如,CMP工艺)以获得与通孔349的上表面、以及管芯340和管芯346的上表面平齐的平坦的上表面。随后,在第二模制层348、通孔349、管芯340和管芯346上方形成RDL 350。RDL350包括形成在一个或多个介电层中的导线和/或导电通孔。在实施例中,RDL 350的材料和形成方法类似于图5中的RDL 250的材料和形成方法。在各种实施例中,RDL 350电连接到通孔349、管芯340和管芯346,并且可以提供管芯340、管芯346和通孔349之间的电连接。
在图14中,通孔379形成在RDL 350上方并且电连接到RDL 350。在实施例中,通孔379的材料和形成方法类似于图5中的通孔269的材料和形成方法。在一些实施例中,通孔379的宽度W5小于或等于通孔349的宽度W4(W5≤W4)。在一些实施例中,通孔349的宽度W4小于或等于通孔329的宽度W3(W4≤W3)。在所示的实施例中,宽度W5小于宽度W4,宽度W4小于宽度W3。例如,随着每个模制层进一步延伸远离介电层313,每个模制层(例如,参见图17的第一模制层328、第二模制层348和第三模制层388)中通孔的宽度可以依次变得更小。作为另一示例,当通孔329用于与另一封装件(例如,图19中的封装件400)连接时,通孔329的宽度W3可以大于宽度W4或宽度W5。
在图15中,TEM芯片110通过介电粘合层355(例如DAF)附接到RDL 350。TEM芯片110设置在通孔379之间,其中TEM芯片110的有源侧背离RDL 350。垂直连接件229形成在TEM芯片110的有源侧上,并且通过例如接合焊盘223和导电焊盘227电连接到TEM芯片110。在一些实施例中,垂直连接件229的中心轴线不与接合焊盘223的中心轴线(例如,沿垂直于RDL350的上表面350U的方向延伸的中心轴线)对准,并且朝TEM芯片110的外周(例如,侧壁)偏移。这保留了TEM芯片110的上表面的中心区域中的更多空间,以用于在后续工艺中附接半导体管芯。
接下来,参考图16,半导体管芯370和半导体管芯380分别通过介电粘合层368(例如DAF)和介电粘合层369(例如DAF)附接到TEM芯片110的上表面。在实施例中,介电粘合层368和介电粘合层369的材料和形成方法类似于图2中的介电粘合层211的材料和形成方法。半导体管芯370和半导体管芯380的有源侧朝向上方(例如,远离TEM芯片110)。
接下来,在图17中,第三模制层388形成在RDL 350上方。第三模制层388包围通孔379、垂直连接件229、TEM芯片110、管芯370和管芯380。第三模制层388可以在沉积之后固化,并且可以进一步经受平坦化工艺(例如,CMP工艺),以获得与通孔379的上表面、垂直连接件229的上表面、以及管芯370和管芯380的上表面平齐的平坦的上表面。在一些实施例中,第三模制层388的厚度TM2等于TEM芯片110的厚度、附接到TEM芯片110的管芯(例如,管芯370或管芯380)的厚度、介电粘合层355的厚度、以及相应介电粘合层(例如,介电粘合层368或介电粘合层369)的厚度的总和,其中沿与TM2相同的方向测量厚度。如图17所示,第三模制层388的上表面388U与管芯370的上表面、管芯380的上表面、通孔379的上表面和垂直连接件229的上表面平齐。
随后,RDL 390形成在第三模制层388、通孔379、垂直连接件229、TEM芯片110、管芯370和管芯380的上方。RDL 390包括形成在一个或多个介电层中的导电部件,并且可以类似于图7中的RDL 270。在各种实施例中,RDL 390电连接到通孔379、TEM芯片110(例如,通过垂直连接件229)、管芯370和管芯380,并且可以提供TEM芯片110、管芯370、管芯380和通孔379之间的电连接。RDL 390可以包括靠近RDL 390的上表面的接触焊盘。在所示实施例中,RDL390包括UBM结构398。
在一些实施例中,连接件399形成在UBM结构398上并且电连接到RDL 390。此外,表面器件394还可以通过电连接到RDL 390的导电部件(例如,微型凸块焊盘或UBM结构,未示出)放置成与RDL 390接触。表面器件394可以用于向半导体管芯(例如,管芯370、管芯380、管芯340、管芯346和管芯320),TEM芯片110或整体封装件300提供附加的功能或程序。在实施例中,表面器件394可以是表面安装器件(SMD)或包括无源器件(例如电阻器、电感器、电容器、跳线及其组合等)的集成无源器件(IPD),其中,这些无源器件期望连接至半导体管芯和TEM芯片110并连同半导体管芯和TEM芯片110一起使用。
在图18中,图17中的半导体封装件300被翻转,并且连接件399附接到由框架395支撑的带393。带393可以是粘合剂的切割带,用于在后续工艺中将半导体封装件300保持在适当位置。载体310通过脱粘工艺与半导体封装件300分离(脱粘)。脱粘工艺可以使用任何合适的工艺(例如蚀刻、研磨和机械剥离)去除载体310。在一些实施例中,载体310通过激光或UV光照射载体310的表面上方脱粘。激光或UV光破坏与载体310接合的介电层(例如,粘合层)的化学键,然后可以容易地将载体310分离。尽管未示出,但是可以在载体脱粘工艺之后进行切割处理,以将形成在载体310上方的多个半导体封装件分割为独立的MUST封装件300。在载体脱粘之后,图18所示的半导体封装件300表示具有TEM芯片110的MUST封装件。
在图19中,另一半导体封装件400附接到图18所示的MUST封装件300,以形成具有TEM芯片110的MUST-PoP封装件500。参考图19,通过MUST封装件300的介电层313形成开口以暴露通孔329。例如,可以用激光钻孔、蚀刻等形成开口。在一些实施例中,可以用例如焊料印刷机将焊膏沉积在开口中。接下来,另一个半导体封装件400通过半导体封装件400的连接件430物理和电连接到MUST封装件300。可以在半导体封装件400(也可以称为顶部封装件)和半导体封装件300(也可以称为底部封装件)之间的间隙中形成底部填充材料417。在其他实施例中,为了形成图19中的MUST-PoP封装件500,在附接顶部封装件400之前,图18中的载体310上方形成的多个MUST封装件300不切割。相反,可以在顶部封装件400附接到相应的底部封装件300之后进行切割。
如图19所示,每个顶部封装件400具有安装在衬底410的上表面410U上的一个或多个管芯420。在一些实施例中,半导体管芯420包括堆叠在一起的多个管芯。半导体管芯420可以是相同类型的管芯,例如存储管芯或逻辑管芯。可选地,半导体管芯420可以具有不同的功能,例如,其中一些是DSP管芯,一些是逻辑管芯,而另一些是存储器管芯。模制层440形成在衬底410的上表面410U上以封装半导体管芯420。在一些实施例中,使用诸如接合引线、凸块或球栅阵列(BGA)球的合适的方法,将半导体管芯420的接触焊盘或接合焊盘连接到衬底410的上表面410U上的接触焊盘413。衬底410包括导电互连结构(未示出)。在一些实施例中,衬底410中的互连结构电连接到衬底410的上表面410U上的接触焊盘413,以及衬底410的与上表面410U相对的下表面上的接触焊盘415。在所示实施例中,连接件430与接触焊盘415接合。连接件430可以是任何合适的连接件,例如铜柱(具有焊料覆盖件)、焊球等。
顶部封装件400与底部封装件300对准,使得顶部封装件400的外部连接件430的位置与底部封装件300的通孔329的位置相匹配。在一些实施例中,在顶部封装件400堆叠在底部封装件300上之后,可以执行回流工艺以通过通孔329物理和电连接至连接件430。回流工艺可以形成介于连接件430和对应的通孔329之间的焊接区域(solder joint region)。在连接件430包括焊球的情况下,回流工艺可以形成介于每个接触焊盘415和对应的通孔329之间焊接区域。
底部填充材料417可以可选地放置为填充顶部封装件400和底部封装件300之间的间隙。底部填充材料417的示例性材料包括(但不限于)聚合物和其他合适的非导电材料。可以用诸如针或喷射分配器将底部填充材料417分配在顶部封装件400和底部封装件300之间的间隙中。可以进行固化工艺以固化底部填充材料417。
通过在半导体封装件中使用TEM芯片(例如,TEM芯片110),减小了半导体封装件的翘曲。此外,由于在封装件中使用的半导体管芯的高纵横比(例如,大于1:1的纵横比),TEM芯片有助于减少不对称的封装件翘曲。因此,提高了半导体封装件的电连接的可靠性和半导体制造的成品率。由于TEM芯片在内部具有功能电路,所以可以用TEM芯片实施各种设计功能,以提高半导体封装件的集成密度。在使用表面器件的实施例中(参见例如图17中的表面装置394),TEM芯片可用于实施表面器件的一些或全部功能,以减少表面器件的数量和/或面积,因此,更多的封装件的表面区域可用于外部连接件399。例如,半导体封装件上的表面器件的原始数量(例如,不使用TEM芯片110的数量)可以为约10个至约12个之间,并且每个表面器件可具有约3mm2或小于3mm2的表面积,TEM芯片110通过实施表面器件的一些或全部功能将表面器件的数量减少到原始数量的约10%至约40%。作为另一个示例,通过实现表面器件的一些或全部功能,TEM芯片将由表面器件占用的封装件300的表面积减小到约5mm2至约20mm2。
例如,图2-8、9-18和19所示的实施例示出了一个模制层(例如,图19中的第三模制层388)中的一个TEM芯片(例如,图19中的TEM芯片110)。然而,TEM芯片可用于任何模制层以减少封装翘曲。例如,图19中的第一模制层328、第二模制层348和第三模制层388中的每一个的内部可以具有一个或多个TEM芯片。此外,根据诸如TEM芯片的表面区域和附接到TEM芯片的管芯的表面区域的因素,附接到每个TEM芯片表面的管芯的数量可以是一个、两个或更多个。在不偏离本发明的精神的情况下,对本文描述的所示实施例的各种修改是可能的,并且所有这些修改完全旨在被包括在本发明的范围内。
图20示出了根据实施例的具有TEM芯片110的集成扇出(InFO)封装件600的截面图。如图20所示,InFO封装件600包括TEM芯片110和半导体管芯140,其中,半导体管芯140的无源侧附接到TEM芯片110的有源侧。模制层148围绕TEM芯片110、管芯140和TEM芯片110的垂直连接件229。通孔149可以选择性地形成在模制层148内,并且从模制层148的上表面延伸到模制层148的下表面。在一些实施例中,模制层148的厚度TM3等于TEM芯片110的厚度、管芯140的厚度、介电粘合层119的厚度和介电粘合层122的厚度之和,其中沿与TM3相同的方向测量厚度。如图20所示,模制层148的下表面148L与管芯140的下表面(例如,管芯连接件145的下表面145L)、通孔149的下表面和垂直连接件229的下表面平齐。
在一些实施例中,在TEM芯片的有源侧上方形成第一RDL层150,第一RDL层150包括形成在一个或多个介电层151中的导线153和/或通孔155。在一些实施例中,第一RDL层150电连接到TEM芯片110(例如,通过垂直连接件229)、管芯140和通孔149,并且可以在TEM芯片110、管芯140和通孔149之间提供电连接。连接件160形成在第一RDL层150的UBM结构158上。在所示实施例中,一个或多个表面器件164附接并电连接到第一RDL层150,并且设置在连接件160之间。在TEM芯片110的无源侧上形成可选的第二RDL层170。如果形成第二RDL层170,第二RDL层170可以包括形成在一个或多个介电层177中的导线173和/或通孔175,并且可以电连接到通孔149。
图21示出了根据实施例的具有TEM芯片110的集成扇出叠层封装(InFO-PoP)的封装件700的截面图。如图21所示,顶部封装件400机械地和电连接到图20所示的InFO封装件600,以形成InFO-PoP封装件700。底部填充材料246可以放置在顶部封装件400和InFO封装件600之间的间隙中。图21中的顶部封装件400可以类似于图19中的顶部封装件400,因此,其具体细节这里不再重复。
图22示出了根据实施例的具有TEM芯片110的集成扇出多芯片(InFO-M)封装件800的截面图。图21中的INFO-M封装件800类似于图20中的InFO封装件600,但是具有附接到TEM芯片110的两个半导体管芯(例如管芯140和管芯144),而不是附接到TEM芯片110的一个管芯。具体细节类似于图20描述的具体细节,因此这里不再重复。对图21的实施例的各种修改是可能的,例如,可以将两个以上的管芯附接到TEM芯片110。
图23示出了根据实施例的具有TEM芯片110的集成扇出多芯片叠层封装(InFO-MPoP)900的截面图。如图23所示,顶部封装件400机械地和电连接到图22所示的INFO-M封装件800以形成InFO-M PoP封装件900。底部填充材料246可以放置在顶部封装件400和InFO-M封装件800之间的间隙中。图23中的顶部封装件400可以类似于图19中的顶部封装件400,因此具体细节这里不再重复。
图24示出了根据一些实施例的用于制造半导体结构的方法1000的流程图。应当理解,图24所示的实施例方法仅仅是许多可能的实施例方法的一个示例。本领域普通技术人员将认识到许多变化、替代和修改。例如,可以添加、删除、替换、重新排列和重复图24中示出的多个步骤。
如图24所示,在步骤1010中,将热机电(TEM)管芯附接到载体上,TEM管芯具有功能电路。在步骤1020中,将第一管芯附接到TEM管芯的第一表面。在步骤1030中,第一通孔形成在TEM管芯的第一表面上方并邻近第一管芯,第一通孔电连接到TEM管芯。在步骤1040中,在载体上方形成第一模制层,第一模制层围绕TEM管芯、第一管芯和第一通孔,其中第一模制层的第一表面与第一管芯的上表面和第一通孔的上表面平齐。在步骤1050,在第一模制层的第一表面上方形成第一再分布层,第一再分布层电连接到第一管芯和第一通孔。
本文描述的一些实施例的有利特征可以包括减轻不对称翘曲和改进控制部件翘曲的能力。具有低CTE的大刚性TEM芯片(例如,图1A/1B中的TEM芯片110)在半导体封装件的晶圆翘曲中起主要作用(例如,补偿、减轻或甚至防止)。由于TEM芯片占据了半导体封装件的空间并且降低了模制层的体积,并且由于模制层可能具有大的CTE,所以TEM芯片可以通过减小封装件中模制层的体积来减小翘曲。对于具有不对称尺寸(诸如矩形的非方形形状)的管芯(例如,图1A/1B中的管芯120),可能发生不对称封装件翘曲。具有对称尺寸(例如,正方形)的TEM芯片可以用于半导体封装件中,以用于附接具有不对称尺寸的管芯,从而减少不对称封装件翘曲。由于TEM芯片包括功能电路,更多的功能可以集成到半导体封装件中,从而提高集成密度并降低成本。一些实施例的另一些有利特征可以包括提供调整初始翘曲的能力。作为另一示例,TEM芯片可以用于集成先前由表面器件集成的无源元件。这减少了半导体封装件中使用的表面器件的数量和/或区域,从而保留更多的空间用于更多的外部连接件(例如,表面区域)。
在一些实施例中,器件包括热机电(TEM)芯片,具有功能电路;第一管芯,附接至所述TEM芯片的第一侧面;第一通孔,位于所述TEM芯片的所述第一侧面上并且邻近所述第一管芯,所述第一通孔电连接至所述TEM芯片。所述器件还包括第一模制层,围绕所述TEM芯片、所述第一管芯和所述第一通孔,其中,所述第一管芯的上表面和所述第一通孔的上表面与所述第一模制层的上表面平齐。所述器件还包括第一再分布层,位于所述第一模制层的上表面上方并且电连接至所述第一通孔和所述第一管芯。
在实施例中,自上而下观看时,所述第一管芯设置在所述TEM芯片的横向边界内,并且所述TEM芯片具有1:1的纵横比。
在实施例中,半导体封装器件还包括:第二管芯,位于所述第一再分布层上方并且附接至所述第一再分布层;第二模制层,位于所述第一再分布层上方并且环绕所述第二管芯;第二再分布层,位于所述第二模制层和所述第二管芯上方,所述第二再分布层电连接至所述第二管芯;以及多个通孔,位于所述第二模制层中,所述多个通孔从所述第二模制层的第一侧面延伸至所述第二模制层的第二侧面,所述第二模制层的第二侧面与所述所述第二模制层的第一侧面相对,其中,所述第二模制层的第一侧面接触所述第一再分布层,并且所述多个通孔电连接至所述第一再分布层和所述第二再分布层。
在实施例中,半导体封装器件还包括:第二通孔,位于所述第一模制层中,并且从所述第一模制层的上表面延伸至所述第一模制层的与所述上表面相对的下表面,其中,所述第二通孔电连接至所述第一再分布层。
在实施例中,半导体封装器件,还包括:第二再分布层,位于所述TEM芯片的第二侧面上,所述TEM芯片的第二侧面与所述TEM芯片的第一侧面相对,其中,所述第二通孔电连接至所述第二再分布层。
在实施例中,半导体封装器件还包括:半导体封装件,位于所述TEM芯片的第二侧面上并且通过所述半导体封装件的外部连接件电连接至所述第二再分布层;以及多个导电凸块,位于所述第一再分布层上方并且电连接至所述第一再分布层。
在实施例中,半导体封装器件还包括:第二管芯,电连接至所述第二再分布层,其中,所述第二再分布层位于所述第二管芯和所述TEM芯片之间;第二模制层,围绕所述第二管芯;以及第三通孔,位于所述第二模制层中,并且电连接至所述第二再分布层。
在实施例中,半导体封装器件还包括:半导体封装件,具有外部连接件,其中,所述半导体封装件的所述外部连接件电连接至所述第三通孔,其中,所述第二模制层位于所述半导体封装件和所述第二再分布层之间;以及导电凸块,位于所述第一再分布层上方并且电连接至所述第一再分布层。
在实施例中,半导体封装器件还包括:第三再分布层,位于所述第二模制层上,并且介于所述第二半导体封装件和所述第二模制层之间,所述第三再分布层电连接至所述第三通孔,其中,所述半导体封装件的所述外部连接件通过所述第三再分布层与所述第三通孔电连接。
在实施例中,半导体封装器件还包括:半导体封装件,位于所述TEM芯片的第二侧面上,所述TEM芯片的第二侧面与所述TEM芯片的第一侧面相对,并且通过所述半导体封装件的外部连接件电连接至所述第二通孔;以及多个导电凸块,位于所述第一再分布层上方并且电连接至所述第一再分布层。
在实施例中,半导体封装器件还包括:第二管芯,附接至所述TEM芯片的第一侧面,其中,所述第二管芯电连接至所述第一再分布层。
在实施例中,半导体封装器件还包括:第二再分布层,位于所述TEM芯片的第二侧面上,所述TEM芯片的第二侧面与所述TEM芯片的第一侧面相对,其中,所述第二通孔电连接至所述第二再分布层。
在实施例中,半导体封装器件还包括:半导体封装件,位于所述TEM芯片的第二侧面上,所述TEM芯片的第二侧面与所述TEM芯片的第一侧面相对,其中,所述半导体封装件的外部连接件电连接至所述第二通孔;以及多个外部连接件,位于所述第一再分布层上方并且电连接至所述第一再分布层。
在其他实施例中,半导体封装件包括热机电(TEM)管芯,嵌入第一模制层中,所述TEM管芯具有位于所述TEM管芯的第一侧面上的第一接合焊盘;垂直连接件,位于所述第一模制层中并且位于所述TEM管芯的第一侧面上,其中,所述垂直连接件电连接至所述第一接合焊盘,并且从所述TEM管芯的第一侧面延伸至所述第一模制层的第一侧面。半导体封装件还包括第一半导体管芯,位于所述第一模制层中以及位于所述TEM管芯的第一侧面上,其中,所述第一半导体管芯在所述第一半导体管芯的第一侧面上具有第二接合焊盘,其中,与所述第一半导体管芯的第一侧面相对的所述第一半导体管芯的第二侧面面对所述TEM管芯的第一侧面。半导体封装件还包括第一再分布层,位于所述第一模制层的第一侧面并且电连接至所述垂直连接件和所述第二接合焊盘。
在实施例中,半导体封装件还包括:第一通孔,位于所述第一模制层中并且邻近所述TEM管芯,其中,所述第一通孔从所述第一模制层的第一侧面延伸至所述第一模制层的第二侧面,所述第一模制层的第二侧面与所述第一模制层的第一侧面相对;以及第二再分布层,位于所述第一模制层的第二侧面上,其中,所述第一通孔电连接至所述第一再分布层和所述第二再分布层。
在实施例中,半导体封装件,还包括位于所述第一模制层的第二侧面上方的第二半导体封装件,其中,所述第二半导体封装件通过所述第二半导体封装件的一个或多个外部连接件电连接至所述第二再分布层。
在实施例中,半导体封装件,还包括:第二半导体管芯,位于所述第二再分布层上方并且电连接至所述第二在分布层;第二模制层,位于所述第二再分布层上方并且围绕所述第二半导体管芯;以及第二通孔,位于所述第二模制层中并且与所述第二半导体管芯邻近,其中,所述第二通孔的高度与所述第二模制层的厚度相等。
在另一个实施例中,一种方法包括附接热机电(TEM)管芯至载体,所述TEM管芯具有功能电路;在所述TEM管芯的第一表面上方形成第一通孔,所述第一通孔与所述TEM管芯电连接;将第一管芯附接至所述TEM管芯的第一表面并且邻近所述第一通孔。该方法还包括在所述载体上方形成第一模制层,所述第一模制层环绕所述TEM管芯、所述第一管芯和所述第一通孔,其中,所述第一模制层的第一表面与所述第一管芯的上表面和所述第一通孔的上表面平齐。该方法还包括在所述第一模制层的第一表面上方形成第一再分布层,所述第一再分布层电连接至所述第一管芯和所述第一通孔。
在实施例中,形成封装器件的方法还包括在所述第一模制层中形成所述第二通孔并且将所述第二通孔电连接至所述第一再分布层,其中,所述第二通孔的高度与所述第一模制层的厚度相等。
在实施例中,形成封装器件的方法还包括:所述第一模制层的第二表面上形成第二再分布层,所述第一模制层的第二表面与所述第一模制层的第一表面相对;以及将半导体封装件机械地和电连接至所述第二再分布层。
以上论述了若干实施例的部件,使得本领域的技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍的实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中可以对其进行多种变化、替换以及改变。
Claims (10)
1.一种半导体封装器件,包括:
热机电(TEM)芯片,具有功能电路;
第一管芯,附接至所述TEM芯片的第一侧面;
第一通孔,位于所述TEM芯片的第一侧面上并且邻近所述第一管芯,所述第一通孔电连接至所述TEM芯片;
第一模制层,围绕所述TEM芯片、所述第一管芯和所述第一通孔,其中,所述第一管芯的上表面和所述第一通孔的上表面与所述第一模制层的上表面平齐;以及
第一再分布层,位于所述第一模制层的上表面上方并且电连接至所述第一通孔和所述第一管芯。
2.根据权利要求1所述的半导体封装器件,其中,自上而下观看时,所述第一管芯设置在所述TEM芯片的横向边界内,并且所述TEM芯片具有1:1的纵横比。
3.根据权利要求2所述的半导体封装器件,还包括:
第二管芯,位于所述第一再分布层上方并且附接至所述第一再分布层;
第二模制层,位于所述第一再分布层上方并且环绕所述第二管芯;
第二再分布层,位于所述第二模制层和所述第二管芯上方,所述第二再分布层电连接至所述第二管芯;以及
多个通孔,位于所述第二模制层中,所述多个通孔从所述第二模制层的第一侧面延伸至所述第二模制层的第二侧面,所述第二模制层的第二侧面与所述所述第二模制层的第一侧面相对,其中,所述第二模制层的第一侧面接触所述第一再分布层,并且所述多个通孔电连接至所述第一再分布层和所述第二再分布层。
4.根据权利要求1所述的半导体封装器件,还包括:
第二通孔,位于所述第一模制层中,并且从所述第一模制层的上表面延伸至所述第一模制层的与所述上表面相对的下表面,其中,所述第二通孔电连接至所述第一再分布层。
5.根据权利要求4所述的半导体封装器件,还包括:
第二再分布层,位于所述TEM芯片的第二侧面上,所述TEM芯片的第二侧面与所述TEM芯片的第一侧面相对,其中,所述第二通孔电连接至所述第二再分布层。
6.根据权利要求5所述的半导体封装器件,还包括:
半导体封装件,位于所述TEM芯片的第二侧面上并且通过所述半导体封装件的外部连接件电连接至所述第二再分布层;以及
多个导电凸块,位于所述第一再分布层上方并且电连接至所述第一再分布层。
7.根据权利要求5所述的半导体封装器件,还包括:
第二管芯,电连接至所述第二再分布层,其中,所述第二再分布层位于所述第二管芯和所述TEM芯片之间;
第二模制层,围绕所述第二管芯;以及
第三通孔,位于所述第二模制层中,并且电连接至所述第二再分布层。
8.根据权利要求7所述的半导体封装器件,还包括:
半导体封装件,具有外部连接件,其中,所述半导体封装件的所述外部连接件电连接至所述第三通孔,其中,所述第二模制层位于所述半导体封装件和所述第二再分布层之间;以及
导电凸块,位于所述第一再分布层上方并且电连接至所述第一再分布层。
9.一种半导体封装件,包括:
热机电(TEM)管芯,嵌入第一模制层中,所述TEM管芯具有位于所述TEM管芯的第一侧面上的第一接合焊盘;
垂直连接件,位于所述第一模制层中并且位于所述TEM管芯的第一侧面上,其中,所述垂直连接件电连接至所述第一接合焊盘并且从所述TEM管芯的第一侧面延伸至所述第一模制层的第一侧面;
第一半导体管芯,位于所述第一模制层中以及位于所述TEM管芯的第一侧面上,其中,所述第一半导体管芯具有位于所述第一半导体管芯的第一侧面上的第二接合焊盘,其中,与所述第一半导体管芯的第一侧面相对的所述第一半导体管芯的第二侧面面对所述TEM管芯的第一侧面;以及
第一再分布层,位于所述第一模制层的第一侧面上并且电连接至所述垂直连接件和所述第二接合焊盘。
10.一种形成封装器件的方法,包括:
将热机电(TEM)管芯附接至载体,所述TEM管芯具有功能电路;
在所述TEM管芯的第一表面上方形成第一通孔,所述第一通孔与所述TEM管芯电连接;
将第一管芯附接至所述TEM管芯的第一表面并且邻近所述第一通孔;
在所述载体上方形成第一模制层,所述第一模制层环绕所述TEM管芯、所述第一管芯和所述第一通孔,其中,所述第一模制层的第一表面与所述第一管芯的上表面和所述第一通孔的上表面平齐;以及
在所述第一模制层的第一表面上方形成第一再分布层,所述第一再分布层电连接至所述第一管芯和所述第一通孔。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662376726P | 2016-08-18 | 2016-08-18 | |
US62/376,726 | 2016-08-18 | ||
US15/366,654 | 2016-12-01 | ||
US15/366,654 US10672741B2 (en) | 2016-08-18 | 2016-12-01 | Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107768351A true CN107768351A (zh) | 2018-03-06 |
CN107768351B CN107768351B (zh) | 2021-04-27 |
Family
ID=61192109
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710587367.1A Active CN107768351B (zh) | 2016-08-18 | 2017-07-18 | 具有热机电芯片的半导体封装件及其形成方法 |
Country Status (3)
Country | Link |
---|---|
US (2) | US10672741B2 (zh) |
CN (1) | CN107768351B (zh) |
TW (1) | TWI719189B (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110364505A (zh) * | 2018-04-10 | 2019-10-22 | 台湾积体电路制造股份有限公司 | 多芯片半导体封装件 |
CN112490129A (zh) * | 2019-09-11 | 2021-03-12 | 华邦电子股份有限公司 | 半导体封装及其制造方法 |
CN112820722A (zh) * | 2019-11-15 | 2021-05-18 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
CN113811804A (zh) * | 2019-04-04 | 2021-12-17 | 洛克利光子有限公司 | 光学引擎 |
US20230060520A1 (en) * | 2021-08-27 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and semiconductor device |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11069734B2 (en) | 2014-12-11 | 2021-07-20 | Invensas Corporation | Image sensor device |
US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
US11469215B2 (en) * | 2016-07-13 | 2022-10-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip package structure with molding layer and method for forming the same |
US9825007B1 (en) * | 2016-07-13 | 2017-11-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip package structure with molding layer and method for forming the same |
US11625523B2 (en) | 2016-12-14 | 2023-04-11 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips |
CN108288616B (zh) | 2016-12-14 | 2023-04-07 | 成真股份有限公司 | 芯片封装 |
US10879212B2 (en) | 2017-05-11 | 2020-12-29 | Invensas Bonding Technologies, Inc. | Processed stacked dies |
US10217720B2 (en) * | 2017-06-15 | 2019-02-26 | Invensas Corporation | Multi-chip modules formed using wafer-level processing of a reconstitute wafer |
US10447274B2 (en) | 2017-07-11 | 2019-10-15 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells |
US10957679B2 (en) | 2017-08-08 | 2021-03-23 | iCometrue Company Ltd. | Logic drive based on standardized commodity programmable logic semiconductor IC chips |
US10636757B2 (en) * | 2017-08-29 | 2020-04-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit component package and method of fabricating the same |
US10630296B2 (en) | 2017-09-12 | 2020-04-21 | iCometrue Company Ltd. | Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells |
US10957672B2 (en) * | 2017-11-13 | 2021-03-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of manufacturing the same |
US10608642B2 (en) | 2018-02-01 | 2020-03-31 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells |
US10692996B1 (en) * | 2018-02-05 | 2020-06-23 | United States Of America As Represented By The Secretary Of The Air Force | Systems, methods and apparatus for radio frequency devices |
US10623000B2 (en) | 2018-02-14 | 2020-04-14 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips |
US10573573B2 (en) * | 2018-03-20 | 2020-02-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package and package-on-package structure having elliptical conductive columns |
US11735570B2 (en) * | 2018-04-04 | 2023-08-22 | Intel Corporation | Fan out packaging pop mechanical attach method |
US11276676B2 (en) | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
US10608638B2 (en) | 2018-05-24 | 2020-03-31 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips |
WO2020010136A1 (en) | 2018-07-06 | 2020-01-09 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
US11462419B2 (en) | 2018-07-06 | 2022-10-04 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
US10573618B1 (en) * | 2018-07-31 | 2020-02-25 | Delta Electronics, Inc. | Package structures and methods for fabricating the same |
US11309334B2 (en) | 2018-09-11 | 2022-04-19 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells |
US10892011B2 (en) | 2018-09-11 | 2021-01-12 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells |
US10937762B2 (en) | 2018-10-04 | 2021-03-02 | iCometrue Company Ltd. | Logic drive based on multichip package using interconnection bridge |
US11616046B2 (en) | 2018-11-02 | 2023-03-28 | iCometrue Company Ltd. | Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip |
US11211334B2 (en) | 2018-11-18 | 2021-12-28 | iCometrue Company Ltd. | Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip |
WO2020150159A1 (en) | 2019-01-14 | 2020-07-23 | Invensas Bonding Technologies, Inc. | Bonded structures |
US11600590B2 (en) * | 2019-03-22 | 2023-03-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package |
US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
CN112151516A (zh) * | 2019-06-28 | 2020-12-29 | 台湾积体电路制造股份有限公司 | 封装 |
US10985154B2 (en) | 2019-07-02 | 2021-04-20 | iCometrue Company Ltd. | Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits |
US11227838B2 (en) | 2019-07-02 | 2022-01-18 | iCometrue Company Ltd. | Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits |
US11887930B2 (en) | 2019-08-05 | 2024-01-30 | iCometrue Company Ltd. | Vertical interconnect elevator based on through silicon vias |
WO2020123001A1 (en) * | 2019-09-05 | 2020-06-18 | Futurewei Technologies, Inc. | Multi-side power delivery in stacked memory packaging |
US11088125B2 (en) * | 2019-09-17 | 2021-08-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | IPD modules with flexible connection scheme in packaging |
US11637056B2 (en) | 2019-09-20 | 2023-04-25 | iCometrue Company Ltd. | 3D chip package based on through-silicon-via interconnection elevator |
US11251119B2 (en) * | 2019-09-25 | 2022-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure, package-on-package structure and method of fabricating the same |
US11515224B2 (en) * | 2020-01-17 | 2022-11-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Packages with enlarged through-vias in encapsulant |
US11600526B2 (en) | 2020-01-22 | 2023-03-07 | iCometrue Company Ltd. | Chip package based on through-silicon-via connector and silicon interconnection bridge |
US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
KR20220117032A (ko) * | 2021-02-16 | 2022-08-23 | 삼성전자주식회사 | 반도체 패키지 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009022991A1 (en) * | 2007-08-14 | 2009-02-19 | Agency For Science, Technology And Research | Die package and method for manufacturing the die package |
CN102593110A (zh) * | 2012-01-05 | 2012-07-18 | 三星半导体(中国)研究开发有限公司 | 超细间距焊盘的叠层倒装芯片封装结构及底填充制造方法 |
CN102931173A (zh) * | 2011-08-10 | 2013-02-13 | 台湾积体电路制造股份有限公司 | 多芯片晶圆级封装 |
CN103730434A (zh) * | 2012-10-11 | 2014-04-16 | 台湾积体电路制造股份有限公司 | Pop结构及其形成方法 |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003023138A (ja) * | 2001-07-10 | 2003-01-24 | Toshiba Corp | メモリチップ及びこれを用いたcocデバイス、並びに、これらの製造方法 |
US20080174008A1 (en) * | 2007-01-18 | 2008-07-24 | Wen-Kun Yang | Structure of Memory Card and the Method of the Same |
US8759964B2 (en) | 2007-07-17 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level package structure and fabrication methods |
US9985150B2 (en) | 2010-04-07 | 2018-05-29 | Shimadzu Corporation | Radiation detector and method of manufacturing the same |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US8361842B2 (en) | 2010-07-30 | 2013-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded wafer-level bonding approaches |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8884431B2 (en) | 2011-09-09 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures for semiconductor devices |
US9905520B2 (en) * | 2011-06-16 | 2018-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Solder ball protection structure with thick polymer layer |
US8829676B2 (en) | 2011-06-28 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for wafer level package |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US8680647B2 (en) | 2011-12-29 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with passive devices and methods of forming the same |
US9111949B2 (en) | 2012-04-09 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of wafer level package for heterogeneous integration technology |
US9991190B2 (en) | 2012-05-18 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging with interposer frame |
US8703542B2 (en) | 2012-05-18 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level packaging mechanisms |
US8809996B2 (en) | 2012-06-29 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with passive devices and method of forming the same |
US8785299B2 (en) | 2012-11-30 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with a fan-out structure and method of forming the same |
US8803306B1 (en) | 2013-01-18 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package structure and methods for forming the same |
US8778738B1 (en) | 2013-02-19 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices and packaging devices and methods |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US20140264831A1 (en) * | 2013-03-14 | 2014-09-18 | Thorsten Meyer | Chip arrangement and a method for manufacturing a chip arrangement |
US8877554B2 (en) | 2013-03-15 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US8669140B1 (en) | 2013-04-04 | 2014-03-11 | Freescale Semiconductor, Inc. | Method of forming stacked die package using redistributed chip packaging |
US9972602B2 (en) * | 2015-02-23 | 2018-05-15 | Marvell World Trade Ltd. | Method and apparatus for interconnecting stacked dies using metal posts |
US9806063B2 (en) * | 2015-04-29 | 2017-10-31 | Qualcomm Incorporated | Reinforced wafer level package comprising a core layer for reducing stress in a solder joint and improving solder joint reliability |
US9761534B2 (en) * | 2015-09-21 | 2017-09-12 | Mediatek Inc. | Semiconductor package, semiconductor device using the same and manufacturing method thereof |
US10490528B2 (en) * | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
TWI576928B (zh) * | 2015-10-21 | 2017-04-01 | 力成科技股份有限公司 | 模封互連基板及其製造方法 |
US9773757B2 (en) * | 2016-01-19 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices, packaged semiconductor devices, and semiconductor device packaging methods |
-
2016
- 2016-12-01 US US15/366,654 patent/US10672741B2/en active Active
-
2017
- 2017-04-07 TW TW106111643A patent/TWI719189B/zh active
- 2017-07-18 CN CN201710587367.1A patent/CN107768351B/zh active Active
-
2018
- 2018-07-31 US US16/051,311 patent/US10720409B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009022991A1 (en) * | 2007-08-14 | 2009-02-19 | Agency For Science, Technology And Research | Die package and method for manufacturing the die package |
CN102931173A (zh) * | 2011-08-10 | 2013-02-13 | 台湾积体电路制造股份有限公司 | 多芯片晶圆级封装 |
CN102593110A (zh) * | 2012-01-05 | 2012-07-18 | 三星半导体(中国)研究开发有限公司 | 超细间距焊盘的叠层倒装芯片封装结构及底填充制造方法 |
CN103730434A (zh) * | 2012-10-11 | 2014-04-16 | 台湾积体电路制造股份有限公司 | Pop结构及其形成方法 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110364505A (zh) * | 2018-04-10 | 2019-10-22 | 台湾积体电路制造股份有限公司 | 多芯片半导体封装件 |
US10847505B2 (en) | 2018-04-10 | 2020-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip semiconductor package |
US11495590B2 (en) | 2018-04-10 | 2022-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip semiconductor package |
US11848319B2 (en) | 2018-04-10 | 2023-12-19 | Taiwan Semiconductor Manufacturing Company, Ltd | Multi-chip semiconductor package |
CN113811804A (zh) * | 2019-04-04 | 2021-12-17 | 洛克利光子有限公司 | 光学引擎 |
CN112490129A (zh) * | 2019-09-11 | 2021-03-12 | 华邦电子股份有限公司 | 半导体封装及其制造方法 |
CN112820722A (zh) * | 2019-11-15 | 2021-05-18 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
US20230060520A1 (en) * | 2021-08-27 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US10720409B2 (en) | 2020-07-21 |
US20180374824A1 (en) | 2018-12-27 |
CN107768351B (zh) | 2021-04-27 |
US20180053746A1 (en) | 2018-02-22 |
TW201826466A (zh) | 2018-07-16 |
US10672741B2 (en) | 2020-06-02 |
TWI719189B (zh) | 2021-02-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107768351A (zh) | 具有热机电芯片的半导体封装件及其形成方法 | |
US11239157B2 (en) | Package structure and package-on-package structure | |
KR101885036B1 (ko) | 반도체 패키지 및 그 형성 방법 | |
CN108074828A (zh) | 封装结构及其形成方法 | |
TWI538145B (zh) | 半導體裝置及其製造方法 | |
CN104037153B (zh) | 3d封装件及其形成方法 | |
TWI482261B (zh) | 三維系統級封裝堆疊式封裝結構 | |
TW201836066A (zh) | 半導體封裝體及其形成方法 | |
CN108122861A (zh) | 具有虚设管芯的扇出型封装结构 | |
CN109786268A (zh) | 半导体封装件中的金属化图案及其形成方法 | |
CN109786266A (zh) | 半导体封装件及其形成方法 | |
CN109860136A (zh) | 集成扇出封装件及其形成方法 | |
US20110209908A1 (en) | Conductor package structure and method of the same | |
US20140210080A1 (en) | PoP Device | |
US9418922B2 (en) | Semiconductor device with reduced thickness | |
US9548220B2 (en) | Method of fabricating semiconductor package having an interposer structure | |
US9269693B2 (en) | Fabrication method of semiconductor package | |
US20220384355A1 (en) | Semiconductor Devices and Methods of Manufacture | |
KR102524244B1 (ko) | 반도체 패키지들에서의 방열 및 그 형성 방법 | |
CN115394768A (zh) | 一种多层高带宽存储器及其制造方法 | |
CN220873557U (zh) | 半导体封装 | |
CN210516718U (zh) | 一种封装结构 | |
CN210692483U (zh) | 一种封装结构 | |
TW202410342A (zh) | 半導體封裝及其製造方法 | |
TW202347662A (zh) | 積體電路封裝及其形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |