CN110364505A - 多芯片半导体封装件 - Google Patents

多芯片半导体封装件 Download PDF

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Publication number
CN110364505A
CN110364505A CN201910089343.2A CN201910089343A CN110364505A CN 110364505 A CN110364505 A CN 110364505A CN 201910089343 A CN201910089343 A CN 201910089343A CN 110364505 A CN110364505 A CN 110364505A
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CN
China
Prior art keywords
tube core
redistribution structure
conductive column
conductive
electrically coupled
Prior art date
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Pending
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CN201910089343.2A
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English (en)
Inventor
赖昱嘉
潘国龙
郭鸿毅
郭庭豪
蔡豪益
刘重希
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to CN202210898247.4A priority Critical patent/CN115274610A/zh
Publication of CN110364505A publication Critical patent/CN110364505A/zh
Pending legal-status Critical Current

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Abstract

半导体封装件包括：第一管芯；第一再分布结构，位于第一管芯上，第一再分布结构与第一管芯共末端；第二管芯，位于第一管芯上，第一管芯的第一部分延伸超出第二管芯的横向范围；导电柱，位于第一管芯的第一部分上并且与第二管芯横向相邻，导电柱电耦合到第一管芯；模制材料，位于第一管芯、第二管芯和导电柱周围；以及第二再分布结构，位于模制材料上，第二再分布结构电耦合到导电柱和第二管芯。本发明的实施例还涉及多芯片半导体封装件。

Description

多芯片半导体封装件
技术领域
本发明的实施例涉及多芯片半导体封装件。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体工业经历了快速增长。在大多数情况下，集成密度的这种改进来自于最小部件尺寸的反复减小，这允许将更多组件集成到给定区域中。随着最近对更小电子器件的需求增长，对半导体管芯的更小和更有创意的封装技术的需求不断增长。
随着半导体技术的进一步发展，堆叠半导体器件(例如，3D集成电路(3DIC)封装件)已经成为进一步减小半导体器件的物理尺寸的有效替代方案。在堆叠半导体器件中，在不同的半导体晶圆上制造诸如逻辑、存储器、处理器电路等的有源电路。两个或多个半导体组件可以彼此叠置地安装，以进一步减小半导体器件的形状因数。
先进封装技术的高度集成使得能够生产具有增强功能和小的占用面积的半导体器件，这对于诸如移动电话、平板电脑和数字音乐播放器的小型器件是有利的。另一个优点是连接半导体器件内的互操作部分的导电路径的长度缩短。这改善了半导体器件的电性能，因为电路之间的互连的较短路由产生了更快的信号传播并且降低了噪声和串扰。
发明内容
本发明的实施例提供了一种半导体封装件，包括：第一管芯；第二管芯，附接到所述第一管芯，所述第一管芯的第一部分延伸超出所述第二管芯的横向范围；导电柱，位于所述第一管芯的第一部分上并且与所述第二管芯横向相邻，所述导电柱电耦合到所述第一管芯；模制材料，位于所述第一管芯、所述第二管芯和所述导电柱周围；以及第一再分布结构，位于所述模制材料上，所述第一再分布结构电耦合到所述导电柱和所述第二管芯。
本发明的另一实施例提供了一种半导体封装件，包括：第一管芯；第二管芯，位于所述第一管芯上；第一再分布结构，位于所述第一管芯和所述第二管芯之间，所述第一再分布结构电耦合到所述第一管芯，所述第一再分布结构的侧壁与所述第一管芯的侧壁对准；导电柱，位于所述第一再分布结构上并且与所述第一再分布结构电耦合；以及模制材料，围绕所述第一管芯、所述第二管芯、所述第一再分配结构和所述导电柱，其中，所述第一管芯的第一部分位于所述第二管芯下方，并且所述第一管芯的第二部分位于所述模制材料的部分下方。
本发明的又一实施例提供了一种形成半导体器件的方法，包括：在第一管芯的第一侧上形成第一再分布结构；在所述第一再分布结构上形成导电柱，所述导电柱电耦合到所述第一再分布结构；将所述第一管芯的与第一侧相对的第二侧附接到载体；将第二管芯附接到所述第一再分配结构，其中，在附接所述第二管芯之后，所述第二管芯的部分延伸超出所述第一管芯的横向范围；以及在所述载体上与所述第一管芯、所述第二管芯、所述第一再分配结构和所述导电柱周围形成模制材料。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A和图1B示出了一些实施例中的各种半导体管芯的输入/输出(I/O)焊盘的布局。
图2至图10、图11A和图11B示出了根据一个实施例的处于各个制造阶段的半导体器件的各个截面图。
图12示出了一个实施例中的半导体器件的截面图。
图13至图19示出了根据一个实施例的处于各个制造阶段的半导体器件的截面图。
图20示出了一个实施例中的半导体器件的截面图。
图21A和图21B示出了一个实施例中的半导体器件的截面图。
图22至图26示出了根据一个实施例的处于各个制造阶段的半导体器件的截面图。
图27至图29示出了各个实施例中的各个半导体器件的截面图。
图30示出了一些实施例中的形成半导体器件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然这些仅是实例而不旨在限制。例如，元件的尺寸不限于所公开的范围或值，但可能依赖于工艺条件和/或器件所需的性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的，各个部件可以以不同的比例任意地绘制。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
在一些实施例中，第一再分布结构形成在第一管芯上并且电耦合到第一管芯。第一再分布结构的再分布层将第一管芯的I/O焊盘从第一位置重新路由电连接到第二位置，例如在具有焊盘区的再分布层的区域内。导电柱形成在焊盘区上并且电耦合到焊盘区。然后将第一管芯的背面附接到载体。可选的第二管芯(可以是伪管芯)附接到与第一管芯相邻的载体。接下来，将第三管芯附接到第一管芯的上表面，并且附接到第二管芯的上表面(如果形成)。接下来，在载体上并且围绕第一管芯、第二管芯、第三管芯和导电柱形成模制材料。在形成模制材料之后，在模制材料上形成第二再分布结构，并且第二再分布结构电耦合到第三管芯和导电柱。
图1A示出了一些实施例中的半导体管芯10的输入/输出(I/O)焊盘13的布局。半导体管芯10可以是存储器管芯并且可以与另一管芯堆叠以形成3DIC封装件。在图1A所示的顶视图中，半导体管芯10的I/O焊盘13沿着半导体管芯10的边缘(例如，周边或侧壁)设置并且形成U形。在本文的讨论中，半导体管芯也可以称为管芯或集成电路(IC)管芯。
图1B示出了一些实施例中的两个半导体管芯20(例如，存储器管芯)的I/O焊盘23的布局。图1B中的每个半导体管芯20的I/O焊盘23沿着一条线形成并且沿着相应的半导体管芯20的边缘(例如，周边或侧壁)设置。半导体管芯20可以是存储器管芯并且可以与另一个管芯耦合以形成3DIC封装件。
在一些实施例中，信号处理管芯堆叠在一个或多个存储器管芯(例如，10或20)上以形成半导体器件(例如，3DIC封装件)。信号处理管芯可以是例如用于无线通信的基带管芯，并且可以包括微控制器、中央处理单元(CPU)、数字信号处理器(DSP)，并且可以包括I/O外围设备和附加硬件块，诸如快速傅立叶变换(FFT)块、滤波器、数字均衡器等，以实施各种设计功能。在一些应用中，在3DIC封装件中集成在一起的信号处理管芯和存储器管芯由不同的制造商制造，并且存储器芯片的I/O焊盘的位置可能不利于信号处理管芯在存储器管芯上的垂直堆叠。本文公开的各个实施例提供了能够适应具有不同I/O焊盘位置的管芯的集成的结构和方法。
图2至图10、图11A和图11B示出了根据一个实施例的处于各个制造阶段的半导体器件100(例如，3DIC半导体封装件)的各个截面图。图2示出了管芯101的截面图，管芯101可以是存储器管芯，例如动态随机存取存储器(DRAM)管芯。为简单起见，在图2(和随后的附图)中仅示出了一个半导体管芯101，然而，应当理解，在半导体制造期间可以在单个衬底上同时形成数十、数百或甚至更多的半导体管芯，并且在之后可以分割以形成多个单独的器件。
在一些实施例中，半导体管芯101包括半导体衬底102，例如掺杂或未掺杂的硅、或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其他半导体材料，例如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、氮化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用其他衬底，例如多层或梯度衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底102中和/或上，并且可以通过互连结构互连以形成集成电路，互连结构例如由半导体衬底102上的一个或多个介电层中的金属化图案形成。
管芯101还包括焊盘103(也可以称为接合焊盘)，例如铝焊盘，其上形成有外部连接。焊盘103位于所谓的集成电路管芯101的有源侧(或正面)上。钝化膜105形成在集成电路管芯101的有源侧处和焊盘103的部分上。如图2所示，在钝化膜105中形成开口以暴露焊盘103。焊盘103可以对应于图1A中的I/O焊盘13，或图1B中的I/O焊盘23。
图3至图5示出了在管芯101上形成再分布结构106(参见图5中的标号)。参考图3，在管芯101上形成介电层107。介电层107位于集成电路管芯101的有源侧上，例如在钝化膜105和焊盘103上。介电层107与集成电路管芯101横向共末端。介电层107可以是聚合物，例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等；氮化物，例如氮化硅等；氧化物，例如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等；或它们的组合，并且可以例如通过旋涂、层压、化学气相沉积(CVD)等形成。在介电层107中形成开口104以暴露焊盘103。可以使用光刻和蚀刻技术形成开口104。
接下来，在图4中，在介电层107上形成再分布层(RDL)109。RDL109可以由导电材料(例如，铜)形成，并且可以包括诸如通孔和导线的导电部件。可以通过例如在介电层107上和开口104中形成晶种层，在晶种层上形成具有设计图案的图案化的光刻胶，在所设计的图案中和晶种层上镀(例如，电镀或化学镀)导电材料，以及去除光刻胶和其上未形成导电材料的晶种层的部分来形成RDL109。用于形成RDL 109的其他方法是可能的，并且完全旨在包括在本发明的范围内。如图4所示，RDL 109可以包括位于焊盘103上并且耦合到焊盘103的通孔109V，并且还可以包括导线109L，导线109L耦合到通孔109V并且基本上平行于衬底102的上表面延伸。在一些实施例中，RDL 109包括用于耦合到随后形成的导电柱113(参见图6)的焊盘区109P(参见图6和图11B)。
接下来，在图5中，在介电层107上和RDL 109上形成介电层111。介电层111可以使用相同或相似的形成方法由与介电层107相同或相似的材料形成，因此不再重复细节。介电层111、RDL 109和介电层107形成图5的再分布结构106。在一些实施例中，由于再分布结构106将管芯101的电连接重新路由到管芯101的边界(例如，周边或侧壁)内的不同位置，再分布结构106也称为扇入再分布结构。接下来，在所示实施例中，在介电层111中形成开口112以暴露RDL 109的部分。
接下来参考图6，导电柱113(例如，铜柱)形成在由开口112暴露的RDL 109的部分(例如，焊盘区109P)上，并且电耦合到RDL 109和管芯101。可以通过例如在介电层111上和开口112中形成晶种层，在晶种层上形成具有设计图案的图案化的光刻胶，在设计图案中和晶种层上镀(例如，电镀或化学镀)导电材料(例如，铜)，以及去除光刻胶和其上未形成导电材料的晶种层的部分来形成导电柱113。用于形成导电柱113的其他方法是可能的，并且完全旨在包括在本发明的范围内。
在一些实施例中，在形成导电柱113之后，使用例如研磨工艺实施减薄工艺，以减小半导体管芯101的厚度。在一些实施例中，使用厚切割带(例如，厚于导电柱113的高度)来附接导电柱113和管芯101以用于减薄工艺，使得导电柱113在减薄工艺期间沉入厚切割带中。研磨工艺可以从半导体管芯101的背面去除半导体衬底102的部分。
接下来，在图7中，将图6的半导体器件100附接到由框架115支撑的带117(例如，切割带)。粘合层119(例如，管芯附接膜(DAF))可以用于将半导体器件100附接到带117。接着，沿着切割线121使用例如切割刀片、激光等实施切割工艺，以将半导体器件100与形成在同一衬底上的相邻半导体器件100分离，从而形成多个单独的半导体器件100。可以在切割工艺之后实施可选的清洁工艺，例如擦洗器清洁工艺，以从半导体器件中冲洗掉由切割工艺产生的残留物。如图7所示，在切割工艺之后，再分布结构106与管芯101共末端。换句话说，再分布结构106的侧壁与管芯101的侧壁对准。
接下来，在图8中，半导体器件100从带117上去除，并且附接到载体127。载体127可以由诸如硅、聚合物、聚合物复合物、金属箔、陶瓷、玻璃、玻璃环氧树脂、氧化铍、胶带的材料或其他合适的材料制成以用于结构支撑。可以使用诸如DAF的粘合层将半导体器件100附接到载体127。另外，管芯123也附接到载体127并且邻近管芯101。诸如DAF的粘合层可以用于将管芯123附接到载体127。
在一些实施例中，管芯123是伪管芯(例如，不具有功能电路的管芯)，并且伪管芯用于为随后附接的管芯131(参见图9)提供机械支撑。伪管芯可以由例如半导体材料制成，例如块状硅，但是也可以使用其他合适的材料，例如玻璃或氮化铝(AlN)。管芯123的上表面可以与介电层111的上表面齐平。在其他实施例中，管芯123是另一个存储器管芯(参见例如图21A)。例如，管芯123可以是与管芯101相同类型的存储器管芯。
接下来，在图9中，管芯131的背面通过介电膜125附接到管芯123的上表面并且附接到介电层111的上表面。图9还示出了管芯131的管芯连接件133，管芯连接件133是位于管芯131的有源侧上的导电柱(例如，铜柱)，并且电耦合到管芯131的集成电路。管芯131可以是信号处理管芯，例如基带管芯。介电膜125可以是粘合层，例如DAF。管芯131可以使用与管芯101类似的形成方法形成，并且包括与管芯101类似的部件。
如图9所示，管芯131的部分131R位于管芯101上面(例如，直接设置在管芯101上或与管芯101重叠)，并且管芯131的另一部分131L设置在管芯101的横向延伸范围外侧。换句话说，管芯131的部分131R横向地设置在管芯101的相对侧壁之间，并且管芯131的部分131L横向地设置在管芯101的相对侧壁外侧。在附接管芯131之后，导电柱113与管芯131横向相邻。在图9的示例中，管芯101和管芯123在半导体器件100内处于相同的层级(例如，较低的层级)，并且管芯131和导电柱113处于半导体器件100内的相同的层级(例如，在较低层级上的较高层级)。
接下来，在图10中，在载体127上并且围绕导电柱113和管芯101/123/131形成模制材料135。作为示例，模制材料135可以包括环氧树脂、有机聚合物、添加或不添加基于二氧化硅或玻璃填料的聚合物或其他材料。在一些实施例中，模制材料135包括液体模制化合物(LMC)，其在施加时是凝胶型液体。当施加时，模制材料135还可以包括液体或固体。或者，模制材料135可以包括其他绝缘和/或包封材料。在一些实施例中，使用晶圆级模制工艺来施加模制材料135。例如，可以使用压缩模制、传递模制或其他方法来模制模制材料135。
接下来，在一些实施例中，使用固化工艺来固化模制材料135。固化工艺可以包括使用退火工艺或其他加热工艺将模制材料135加热至预定温度达预定时间段。固化工艺还可以包括紫外(UV)曝光工艺、红外(IR)能量曝光工艺、其组合或它们与加热工艺的组合。或者，可以使用其他方法固化模制材料135。在一些实施方案中，不包括固化工艺。可以实施平坦化工艺，例如化学机械抛光(CMP)，以获得模制材料135的水平上表面，并且暴露管芯连接件133和导电柱113的上表面。在图10的示例中，模制材料135是一体的连续模制材料。
接下来，在图11A中，在模制材料135上形成包括导电部件(例如，通孔和导线)的再分布结构140。在一些实施例中，再分布结构140的导电部件电耦合到管芯连接件133和导电柱113。凸块下金属(UBM)结构147形成在再分布结构140上并且电耦合到再分布结构140，并且外部连接件149(例如，导电凸块)形成在UBM结构147上。
如图11A所示，再分布结构140包括导电部件，例如形成在一个或多个介电层141中的一层或多层导线143和通孔145。在一些实施例中，一个或多个介电层141由聚合物形成，例如PBO、聚酰亚胺、BCB等。在其他实施例中，一个或多个介电层141由诸如氮化硅的氮化物；诸如氧化硅、PSG、BSG、BPSG等的氧化物；等等形成。一个或多个介电层141可以通过任何可接受的沉积工艺形成，例如旋涂、CVD、层压等或它们的组合。
在一些实施例中，再分布结构140的导电部件包括由合适的导电材料(例如铜、钛、钨、铝等)形成的导线143和/或导电通孔145。可以通过例如在介电层141中形成开口以暴露下面的导电部件，在介电层141上和开口中形成晶种层，在晶种层上形成具有设计图案的图案化的光刻胶，在设计的图案中和晶种层上镀(例如，电镀或化学镀)导电材料，以及去除光刻胶和其上未形成导电材料的晶种层的部分来形成导电部件。可以重复上述工艺以形成多层导线和/或通孔。
仍然参考图11A，在形成再分布结构140之后，UBM结构147形成在再分布结构140上并且电耦合到再分布结构140的导电部件(例如，最上面的金属化层)。在一个实施例中，UBM结构147包括三层导电材料，例如钛层、铜层和镍层。然而，存在适合于形成UBM结构147的许多合适的材料和层的布置，例如铬/铬铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于UBM结构147的任何合适的材料或材料层完全旨在包括在本发明的范围内。
接下来，外部连接件149形成在UBM结构147上。在一个实施例中，外部连接件149是导电凸块，例如可控塌陷芯片连接(C4)凸块，并且包括诸如锡的材料或其他合适材料，例如银或铜。在外部连接件149是锡焊料凸块的实施例中，可以通过最初通过任何合适的方法(例如蒸发、电镀、印刷、焊料转移、球放置等)形成锡层来形成外部连接件149。一旦在结构上形成锡层，就实施回流以将材料成形为具有例如约80μm的直径的凸块形状。
然而，虽然上面已经将外部连接件149描述为C4凸块，但是这些仅仅是说明性的而不是用于限制实施例。相反，可以可选地利用任何合适类型的外部接触件，例如球栅阵列(BGA)、微凸块、铜柱、铜层、镍层、无铅(LF)层、化学镀镍化学镀钯浸金(ENEPIG)层、Cu/LF层、Sn/Ag层、Sn/Pb、这些的组合等。任何合适的外部连接件和用于形成外部连接件的任何合适的工艺可以用于外部连接件149，并且所有这些外部连接件完全旨在包括在实施例的范围内。
在图11A的处理步骤之后可以进行额外的处理。例如，可以实施载体脱粘工艺以从半导体器件100去除载体127。此外，可以实施切割工艺以将半导体器件100与相邻器件分离。在切割工艺之后，半导体器件100的再分布结构140与半导体器件100的模制材料135共末端。为简单起见，未示出这些额外的处理。
图11B示出了图11A的半导体器件100沿着横截面A-A的截面图(例如，平面图)。注意，为清楚起见，图11B中未示出半导体器件100的所有部件。另外，为了说明各个部件的相对位置，在图11B中还示出了在横截面A-A处不可见的一些部件。
如图11B所示，管芯101(例如，存储器管芯)具有沿管芯101的三个侧面设置的U形焊盘103(例如，I/O焊盘)。RDL 109(例如，导线和/或通孔)电耦合到焊盘103，并且将到每个焊盘103的电连接重新路由到由相应焊盘区109P示出的新位置。RDL 109的焊盘区109P可以具有圆形形状，如图11B所示，但是也可以使用其他合适的形状，例如椭圆形、矩形、正方形等。在一些实施例中，每个焊盘区109P具有形成在其上的导电柱113。
图11B还示出了管芯123和管芯131(以虚线示出)。焊盘区109P(以及因此导电柱113)形成在管芯131的边缘137和管芯101的边缘138之间的区域中。在一些实施例中，管芯101的边缘138与相邻的(例如，直接相邻的)焊盘区109P之间的距离为D在约40μm和约500μm之间，但是其他尺寸也是可能的。在所示实施例中，焊盘区109P的位置在管芯101/123上留下足够的空间用于附接管芯131，并且允许导电柱113(见图11A)形成在管芯101上(例如，与管芯131横向相邻)而不干扰管芯131的附接。在没有再分布结构106的情况下，设置在管芯131的边界内的管芯101的一些I/O焊盘(例如，103')的电连接可能是不可能的。换句话说，通过将到管芯101的每个焊盘(例如，103、103')的电连接重新路由到新位置，再分布结构106能够适应具有半导体器件100中的不同I/O焊盘位置的各种管芯(例如，101)的使用。
图12示出了一个实施例中的半导体器件100A的截面图。在本文的整个说明书中，除非另有说明，否则不同附图中的相同标号表示由相同或相似的工艺形成的相同或相似的元件，因此可以不重复细节。半导体器件100A类似于图11A的半导体器件100，但没有管芯131下面的管芯123。半导体器件100A的制造工艺可以类似于图2至图10和图11A中所示的那些，但是没有形成管芯123，因此不再重复细节。如图12所示，介电膜125(例如，DAF)与集成电路管芯131横向共末端，因此，位于管芯101的横向范围之外的管芯131的部分(例如，左部分)具有附接到其下表面的介电膜125。
图13至图19示出了根据一个实施例的处于各个制造阶段的半导体器件200(例如，3DIC封装件)的截面图。参照图13，在管芯101(例如，存储器管芯)上形成介电层107，并且在介电层107中形成开口以暴露管芯101的焊盘103。接着，在介电层107和暴露的焊盘103上形成晶种层108。晶种层108可以包括铜(Cu)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)等或它们的组合，并且可以通过原子层沉积(ALD)、溅射、物理气相沉积(PVD)等沉积。在一些实施例中，晶种层108是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。例如，晶种层108可以包括钛层和位于钛层上的铜层。
接下来，在晶种层108上方形成RDL 109。在一些实施例中，通过在晶种层108上形成具有设计图案的图案化的光刻胶，在设计图案中和晶种层108上镀(例如，电镀或化学镀)导电材料(例如，铜)，以及去除光刻胶来形成RDL 109。注意，在该阶段形成RDL 109之后，不去除晶种层108。相反，在形成导电柱113(参见图14)之后，在随后的蚀刻工艺中去除晶种层108。RDL 109包括通孔109V和导线109L。RDL109还可以包括焊盘区109P(参见例如图11B和图14)，焊盘区109P耦合到随后形成的导电柱113。
图13中的介电层107、晶种层108和RDL 109形成半导体器件200的再分布结构106(也称为扇入再分布结构)。注意，半导体器件200的再分布结构106具有RDL 109作为最上层，因此，RDL 109(例如，导线、通孔)未被再分布结构106的介电层覆盖。尽管晶种层108在图13中示出为单独的层，晶种层108和RDL 109之间可能没有可见界面。
接下来，在图14中，导电柱113形成在RDL 109的部分上，例如，在焊盘区109P上。在一些实施例中，由于在图13的处理之后没有蚀刻晶种层108，所以在RDL 109和/或晶种层108上形成导电柱113，而不需要在RDL 109上形成另一晶种层。这有利地降低了制造工艺的成本和处理时间。
可以通过例如在RDL 109(例如，焊盘区109P)上形成具有设计图案的图案化的光刻胶，在设计图案中并且在RDL 109和/或晶种层108上镀(例如，电镀或化学镀)导电材料(例如，铜)，以及去除光刻胶来形成导电柱113。在去除光刻胶之后，实施蚀刻工艺以去除其上未形成RDL109或导电柱113的晶种层108的部分。用于形成导电柱113的其他方法是可能的，并且完全旨在包括在本发明的范围内。
在一些实施例中，RDL 109包括铜，因此，导电柱113形成(例如，镀)在RDL 109上而不在其间使用晶种层，该晶种层(如果使用的话)可以包括阻挡层的子层(例如，钛、氮化钛等)。换句话说，导电柱113直接形成在RDL 109(例如，焊盘区109P)上(例如，与RDL 109物理接触)，因此RDL109与导电柱113之间的界面是铜至铜界面(例如，其间没有任何阻挡层材料)。铜至铜界面有利地降低了导电柱113的电阻，从而减小了所形成的半导体器件的电阻电容(RC)延迟。
接下来，使用减薄工艺减薄管芯101的背面。在减薄工艺之后，将管芯101的背面附接到由框架115支撑的带117上，如图15所示。可以使用诸如DAF的粘合层119将管芯101附接到带117。接下来，沿着切割线121实施切割工艺，以将半导体器件200与其他相邻的半导体器件分离。在切割工艺之后，可以实施可选的清洁工艺，例如擦洗器清洁工艺。如图15所示，在切割工艺之后，再分布结构106与管芯101共末端。换句话说，再分布结构106的侧壁与管芯101的侧壁对准。
接下来，在图16中，图15中的半导体器件200从带117去除并且附接到载体127。此外，管芯123也附接到载体127并且与管芯101相邻。粘合层(例如DAF)可以用于附接管芯101和管芯123。在一些实施例中，管芯123是伪管芯(例如，没有任何功能电路)，并且用于为随后附接的管芯131(见图17)提供机械支撑。在其他实施例中，管芯123是存储器管芯，并且可以是与管芯101相同类型的存储器管芯。
接下来，在图17中，可以是信号处理管芯(例如，基带管芯)的管芯131附接到管芯123和管芯101(例如，通过再分布结构106)。在附接之后，管芯131位于管芯123上面，并且位于管芯101的部分上面。换句话说，管芯131的部分设置在管芯101的横向范围之外。导电柱113设置为与管芯131横向相邻。
在所示实施例中，介电膜125(例如DAF)用于将管芯131附接到管芯101/123。由于RDL 109是再分布结构106的最上层，所以介电膜125与RDL 109物理接触。介电膜125还物理接触管芯131下面的介电层107。通过在再分配结构106的RDL109上不形成额外的介电层，减少了材料成本和处理时间。另外，可以改善管芯101的散热，这改善了所形成的半导体器件200的性能。
接下来，在图18中，模制材料135形成在载体127上，并且围绕导电柱113和管芯101/123/131。可以实施诸如CMP的平坦化工艺以实现模制材料135的水平上表面，并且暴露管芯连接件133和导电柱113的上表面。
接下来，在图19中，包括导电部件(例如，通孔和导线)的再分布结构140形成在模制材料135上。在所示实施例中，再分布结构140的导电部件电耦合到管芯连接件133和导电柱113。UBM结构147形成在再分布结构140上并且电耦合到再分布结构140，并且外部连接件149(例如，导电凸块)形成在UBM结构147上。
可以在图19的处理步骤之后进行额外的处理。例如，可以实施载体脱粘工艺以从半导体器件200去除载体127。此外，可以实施切割工艺以将半导体器件200与相邻器件分离。在切割工艺之后，半导体器件200的再分布结构140与半导体器件200的模制材料135共末端。为简单起见，未示出这些额外的处理。
图20示出了一个实施例中的半导体器件200A的截面图。半导体器件200A类似于图19的半导体器件200，但没有管芯131下面的管芯123。半导体器件200A的制造工艺可以与图13至图19中所示的相同或相似，但没有形成管芯123，因此不再重复细节。
图21A和图21B示出了半导体器件300的截面图。半导体器件300类似于图20的半导体器件200A，但在管芯131(例如，基带管芯)下面具有两个管芯101(例如，两个DRAM管芯)。特别地，每个管芯101具有形成在其上的再分布结构106，以将至管芯101的I/O焊盘的电连接重新路由到管芯101的周边(例如，侧壁)，从而为管芯131的附接提供空间。管芯131的I/O焊盘的位置可以对应于图1B的那些。
图21B示出了沿着横截面B-B的图21A中的半导体器件300的截面图。注意，为清楚起见，图21B中未示出半导体器件300的所有部件。另外，为了示出各个部件的相对位置，在图21B中还示出了在横截面B-B处不可见的一些部件。
如图21B所示，管芯101的I/O焊盘103通过RDL 109的导线电耦合到再分布结构106的焊盘区109P。焊盘区109P更靠近管芯101的周边(例如，边缘、侧壁)，从而为在管芯101上附接管芯131(以虚线示出)留下更多空间。在没有本发明的再分布结构106的情况下，管芯101可能必须进一步间隔开以为管芯131的附接腾出空间，这将导致半导体器件300的更大的封装件尺寸，使用更多的模制材料135，以及可能更多的翘曲。
图22至图26示出了在一个实施例中处于各个制造阶段的半导体器件400的截面图。图22中所示的是管芯101A。管芯101A类似于图2的管芯101，但是管芯连接件153(例如，铜柱)形成在焊盘103上并且电耦合到焊盘103。管芯连接件153可以延伸穿过介电层(例如，151、107)以与焊盘103连接。管芯101A的介电层151/107可以包括与钝化膜105相同或相似的材料，并且管芯连接件153可以通过镀或任何其他合适的方法形成。
图22还示出了耦合到管芯连接件153(例如，铜连接件)的导电迹线155(例如，铜线)。在一些实施例中，导电迹线155包括与管芯连接件153相同的导电材料(例如，铜)，并且可以在与管芯连接件153相同的处理步骤中形成。换句话说，在工艺期间形成导电迹线155以形成管芯101A。在图22所示的示例中，导电迹线155的上表面与管芯连接件153的上表面齐平，这可能是由于用于形成导电迹线155和管芯连接件153的制造工艺，例如镀工艺和随后的CMP工艺。在其他实施例中，导电迹线155的上表面比管芯连接件153的上表面更高(例如，更远离衬底102延伸)。如图22所示，导电迹线155沿着管芯101A的上表面延伸，并且将至焊盘103(例如，铝焊盘)的电连接从管芯101A的上表面处的第一位置重新路由至第二位置。由于第一位置和第二位置在管芯101A的边界(例如，周边或侧壁)内，因此在所示实施例中，导电迹线155用作扇入再分布层。导电迹线155允许每个随后形成的导电柱113(参见图25)形成在不直接位于相应的焊盘103上的位置处，从而为管芯131(参见图25)的附接腾出空间。
接下来，在图23中，管芯101A通过例如DAF附接到载体127。管芯123(例如，可以是伪管芯或另一个存储器管芯)也通过例如DAF附接到载体127。在图23所示的示例中，管芯123的上表面与管芯101A的上表面齐平。
接下来，在图24中，模制材料135形成在载体127上并且围绕管芯101A和123。在一些实施例中，可以实施诸如CMP的平坦化工艺以实现模制材料135的水平上表面，并且暴露管芯连接件153和导电迹线155。接下来，在模制材料135、管芯123和管芯101A上形成介电层157，介电层157可以是聚合物层。
接下来，在图25中，导电柱113形成在介电层157上并且电耦合到管芯101A的导电迹线155。导电柱113可以通过以下步骤形成：在介电层157中形成开口以暴露下面的导电迹线155，在介电层157上和开口中形成晶种层，在晶种层上形成具有设计图案的图案化的光刻胶，在设计图案中和晶种层上镀(例如，电镀或化学镀)导电材料，以及去除光刻胶和其上未形成导电材料的晶种层的部分。用于形成导电柱113的其他方法是可能的，并且完全旨在包括在本发明的范围内。
接下来，通过介电膜125(例如，DAF)将管芯131附接到介电层157。可以包括与模制材料135相同的材料的另一模制材料136形成在介电层157上、管芯131周围以及导电柱113周围。可以在形成模制材料136之后实施诸如CMP的平坦化工艺，以实现模制材料136的水平上表面，并且暴露管芯连接件133和导电柱113。
接下来，在图26中，包括导电部件(例如，通孔和导线)的再分布结构140形成在模制材料136上。如图26所示，再分布结构140的导电部件电耦合到管芯连接件133和导电柱113。凸块下金属(UBM)结构147形成在再分布结构140上并且电耦合到再分布结构140，并且外部连接件149(例如，导电凸块)形成在UBM结构147上。
可以实施额外的处理，例如使载体127与半导体器件400脱粘。为简单起见，未示出额外的处理。
图27示出了一个实施例中的半导体器件400A的截面图。半导体器件400A类似于图26的半导体器件400，但没有管芯131下面的管芯123。
图28示出了一个实施例中的半导体器件400B的截面图。半导体器件400B类似于图26的半导体器件400，但是没有形成介电层157。结果，在将管芯131附接到管芯123/101A之后，可以在单个工艺中形成模制材料135以围绕导电柱113和管芯101A/123/131。
图29示出了一个实施例中的半导体器件400C的截面图。半导体器件400C类似于图28的半导体器件400B，但没有管芯131下面的管芯123。
实施例可以实现优点。例如，在管芯101(或管芯101A的导电迹线155)上形成的再分布结构106允许具有不同I/O焊盘位置的管芯(例如，存储器管芯)与管芯131(例如，基带管芯)集成，因此，在用于集成在半导体器件(例如，100、200、300、400)中的管芯的选择中提供了灵活性。另外的优点包括：对于RDL 109是再分布结构106的最上层的实施例(参见例如图19和图20)，改善了散热。另外，导电柱113和例如半导体器件200和200A中的RDL 109之间的铜至铜界面降低了导电柱113的电阻，从而减小了所形成的器件的RC延迟。此外，在一些实施例中，模制材料135可以通过单个模制工艺形成以围绕管芯101/123/131和导电柱113，从而减少半导体器件的成本和生产时间。
图30示出了在一些实施例中形成半导体器件的方法1000的流程图。应该理解，图30中所示的实施例方法仅仅是许多可能的实施例方法的示例。本领域普通技术人员将认识到许多变化、替代和修改。例如，可以添加，去除、替换、重新布置和重复如图30所示的各个步骤。
参考图30，在步骤1010中，在第一管芯的第一侧上形成第一再分布结构。在步骤1020中，导电柱形成在第一再分布结构上并且电耦合到第一再分布结构。在步骤1030中，将第一管芯的与第一侧相对的第二侧附接到载体。在步骤1040中，将第二管芯附接到第一再分配结构，其中在附接第二管芯之后，第二管芯的部分延伸超出第一管芯的横向范围。在步骤1050中，在载体上并且围绕第一管芯、第二管芯、第一再分布结构和导电柱形成模制材料。
在一个实施例中，半导体封装件包括：第一管芯；第二管芯，附接到第一管芯，第一管芯的第一部分延伸超出第二管芯的横向范围；导电柱，位于第一管芯的第一部分上并且与第二管芯横向相邻，导电柱电耦合到第一管芯；模制材料，位于第一管芯、第二管芯和导电柱周围；以及第一再分布结构，位于模制材料上，第一再分布结构电耦合到导电柱和第二管芯。在一个实施例中，半导体封装件还包括与第一管芯横向相邻并且位于第二管芯下面的第三管芯。在一个实施例中，第三管芯是伪管芯。在一个实施例中，半导体封装件还包括位于第一管芯和第二管芯之间的第二再分布结构，第二再分布结构与第一管芯共末端，导电柱通过第二再分布结构电耦合到第一管芯。在一个实施例中，第二再分布结构包括设置在第一管芯的第一部分上的焊盘区，其中每个焊盘区电耦合到第一管芯的输入/输出(IO)焊盘。在一个实施例中，导电柱位于焊盘区上并且电耦合到焊盘区。在一个实施例中，半导体封装件还包括位于第二管芯和第二再分布结构之间的介电层。在一个实施例中，第二再分配结构的最上层包括导电部件，其中介电层接触导电部件。在一个实施例中，第一管芯具有管芯连接件和电耦合到管芯连接件的导电迹线，导电迹线的上表面与管芯连接件的上表面齐平，其中导电柱电耦合到第一管芯的导电迹线。在一个实施例中，半导体封装件还包括位于导电迹线和第二管芯之间的介电层，导电柱延伸穿过介电层以与第一管芯的导电迹线电耦合。在一个实施例中，模制材料包括位于介电层下方和第一管芯周围的第一模制材料；以及位于介电层上与第二管芯和导电柱周围的第二模制材料。
在一个实施例中，半导体封装件包括：第一管芯；第二管芯，位于第一管芯上；第一再分布结构，位于第一管芯和第二管芯之间，第一再分布结构电耦合到第一管芯，第一再分布结构的侧壁与第一管芯的侧壁对准；导电柱，位于第一再分布结构上并且与第一再分布结构电耦合；以及模制材料，围绕第一管芯、第二管芯、第一再分配结构和导电柱，其中第一管芯的第一部分位于第二管芯下方，并且第一管芯的第二部分位于模制材料的部分下方。在一个实施例中，第一再分布结构的导电部件设置在第一管芯的第二部分上，其中导电部件电耦合到第一管芯的输入/输出(IO)焊盘，IO焊盘位于第二管芯下方，其中导电柱电耦合到导电部件。在一个实施例中，半导体封装件还包括第二再分布结构，位于第二管芯、导电柱和模制材料上，第二再分布结构电耦合到第二管芯和导电柱。在一个实施例中，半导体封装件还包括与第一管芯横向相邻的第三管芯，其中第二管芯位于第一管芯和第三管芯上面。在一个实施例中，半导体封装件还包括介电膜，位于第二管芯和第一管芯之间以及第二管芯和第三管芯之间。
在一个实施例中，一种形成半导体器件的方法包括：在第一管芯的第一侧上形成第一再分布结构；在第一再分布结构上形成导电柱，导电柱电耦合到第一再分布结构；将第一管芯的与第一侧相对的第二侧附接到载体；将第二管芯附接到第一再分配结构，其中在附接第二管芯之后，第二管芯的部分延伸超出第一管芯的横向范围；以及在载体上与第一管芯、第二管芯、第一再分配结构和导电柱周围形成模制材料。在一个实施例中，该方法还包括：在附接第二管芯之前，将第三管芯附接到载体并且与第一管芯相邻，其中附接第二管芯包括将第二管芯附接到第一再分布结构和第三管芯。在一个实施例中，形成第一再分布结构包括在第一管芯的第一侧上形成第一介电层；以及在第一介电层上形成导电层，其中附接第二管芯包括使用粘合层将第二管芯附接到导电层，其中粘合层接触第一再分布结构的导电层。在一个实施例中，该方法还包括在模制材料上形成第二再分布结构，第二再分布结构电耦合到第二管芯和导电柱；以及在第二再分布结构上形成导电凸块，并且导电凸块电耦合到第二再分布结构。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并且不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体封装件，包括：
第一管芯；
第二管芯，附接到所述第一管芯，所述第一管芯的第一部分延伸超出所述第二管芯的横向范围；
导电柱，位于所述第一管芯的第一部分上并且与所述第二管芯横向相邻，所述导电柱电耦合到所述第一管芯；
模制材料，位于所述第一管芯、所述第二管芯和所述导电柱周围；以及
第一再分布结构，位于所述模制材料上，所述第一再分布结构电耦合到所述导电柱和所述第二管芯。
2.根据权利要求1所述的半导体封装件，还包括与所述第一管芯横向相邻并且位于所述第二管芯下面的第三管芯。
3.根据权利要求2所述的半导体封装件，其中，所述第三管芯是伪管芯。
4.根据权利要求1所述的半导体封装件，还包括位于所述第一管芯和所述第二管芯之间的第二再分布结构，所述第二再分布结构与所述第一管芯共末端，所述导电柱通过所述第二再分布结构电耦合到所述第一管芯。
5.根据权利要求4所述的半导体封装件，其中，所述第二再分布结构包括设置在所述第一管芯的第一部分上的焊盘区，其中，每个所述焊盘区电耦合到所述第一管芯的输入/输出(IO)焊盘。
6.根据权利要求5所述的半导体封装件，其中，所述导电柱位于所述焊盘区上并且电耦合到所述焊盘区。
7.根据权利要求4所述的半导体封装件，还包括位于所述第二管芯和所述第二再分布结构之间的介电层。
8.根据权利要求7所述的半导体封装件，其中，所述第二再分配结构的最上层包括导电部件，其中，所述介电层接触所述导电部件。
9.一种半导体封装件，包括：
第一管芯；
第二管芯，位于所述第一管芯上；
第一再分布结构，位于所述第一管芯和所述第二管芯之间，所述第一再分布结构电耦合到所述第一管芯，所述第一再分布结构的侧壁与所述第一管芯的侧壁对准；
导电柱，位于所述第一再分布结构上并且与所述第一再分布结构电耦合；以及
模制材料，围绕所述第一管芯、所述第二管芯、所述第一再分配结构和所述导电柱，其中，所述第一管芯的第一部分位于所述第二管芯下方，并且所述第一管芯的第二部分位于所述模制材料的部分下方。
10.一种形成半导体器件的方法，包括：
在第一管芯的第一侧上形成第一再分布结构；
在所述第一再分布结构上形成导电柱，所述导电柱电耦合到所述第一再分布结构；
将所述第一管芯的与第一侧相对的第二侧附接到载体；
将第二管芯附接到所述第一再分配结构，其中，在附接所述第二管芯之后，所述第二管芯的部分延伸超出所述第一管芯的横向范围；以及
在所述载体上与所述第一管芯、所述第二管芯、所述第一再分配结构和所述导电柱周围形成模制材料。
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