TW201836066A - 半導體封裝體及其形成方法 - Google Patents

半導體封裝體及其形成方法 Download PDF

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TW201836066A
TW201836066A TW106135959A TW106135959A TW201836066A TW 201836066 A TW201836066 A TW 201836066A TW 106135959 A TW106135959 A TW 106135959A TW 106135959 A TW106135959 A TW 106135959A TW 201836066 A TW201836066 A TW 201836066A
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die
package
integrated circuit
layer
back side
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TW106135959A
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TWI669785B (zh
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余振華
葉德強
普翰屏
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台灣積體電路製造股份有限公司
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Abstract

實施例是一種封裝體，所述封裝體包括第一封裝結構。所述第一封裝結構包括：第一積體電路晶粒，具有主動側及背側，所述主動側包括晶粒連接件；第一電性連接件，相鄰第一積體電路晶粒；包封體，在側向上包封第一積體電路晶粒及第一電性連接件；第一重佈線結構，位於第一積體電路晶粒的晶粒連接件及第一電性連接件上且電性連接至所述第一積體電路晶粒的所述晶粒連接件及所述第一電性連接件；以及熱元件，位於第一積體電路晶粒的背側上。所述封裝體更包括第二封裝結構，所述第二封裝結構藉由第一組導電連接件接合至第一電性連接件及熱元件。

Description

半導體封裝體及其形成方法
由於各種電子組件（例如，電晶體、二極體、電阻器、電容器等）的積集密度持續提高，半導體工業經歷了快速發展。在大部分的情況下，積集密度的提高是源自於最小特徵尺寸（minimum feature size）的持續減小，此使得能夠將更多的組件整合於一定區域中。隨著縮小電子裝置的需求增加，對更小且更具創造性的半導體晶粒封裝技術的需要已然出現。此種封裝系統的一個實例為堆疊式封裝（Package-on-Package，PoP）技術。在堆疊式封裝裝置中，頂部半導體封裝體被堆疊於底部半導體封裝體的頂部上，以提供高階的積集及組件密度。堆疊式封裝技術通常能夠生產具有增強的功能性在印刷電路板（printed circuit board，PCB）上具有小的佔用面積（footprint）的半導體裝置。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用標號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「之下（beneath）」、「下面（below）」、「下部的（lower）」、「上方（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向（旋轉90度或處於其他定向）且本文中使用的空間相對性描述語可同樣相應地進行解釋。
本文所論述實施例可在特定上下文中進行論述，所述特定上下文即一種在半導體晶粒的背側上形成熱元件的封裝結構。所揭露實施例中的熱元件不是用於電性連接封裝結構中的裝置或金屬化圖案，而是用於發散來自所述封裝結構的熱能。在一些實施例中，熱元件不連接至散熱路徑，而在一些實施例中，熱元件連接至半導體晶粒中的散熱路徑。舉例而言，熱元件可連接至與半導體晶粒中的一個或多個電晶體熱耦合/熱連接的通孔，以發散由所述電晶體產生的熱能。相較於不在半導體晶粒的背側上形成熱元件的封裝結構，本發明的實施例可將所述封裝結構的熱阻（℃/瓦（℃/Watt））提高達約8%。
此外，此揭露內容的教示內容適用於包括一個或多個半導體晶粒的任何封裝結構。其他實施例考慮了其他應用，例如不同封裝類型或不同配置，此在本領域技術中具有通常知識者藉由閱讀本揭露內容將是顯而易見的。應注意，本文所論述的實施例可能未必說明結構中可存在的每個組件或特徵。舉例而言，例如當對一個組件的論述可足以傳達實施例的各態樣時，可自圖中省略多個所述組件。此外，本文所論述方法實施例可被論述為以特定順序來執行；然而，可以任何邏輯順序來執行其他方法實施例。
圖1至圖12說明根據一些實施例的在形成第一封裝結構的製程期間的各中間步驟的剖視圖。圖1說明載體基底100及形成於載體基底100上的離型層102。將說明分別用於形成第一封裝體及第二封裝體的第一封裝區600及第二封裝區602。
載體基底100可為玻璃載體基底、陶瓷載體基底等。載體基底100可為晶圓，使得可在載體基底100上同時形成多個封裝體。離型層102可由聚合物系材料形成，所述聚合物材料可與載體基底100一起從將在後續的步驟中所形成的上覆結構移除。在一些實施例中，離型層102為一種環氧樹脂系熱釋放材料（epoxy-based thermal-release material），例如是例如光熱轉換（light-to-heat-conversion，LTHC）釋放塗層等，其會在受熱時失去其附著性質。在其他實施例中，離型層102可以是一種紫外膠（UV glue），其會在暴露至紫外光時失去其附著性質。離型層102可如液體般分散並固化，可以是疊層於載體基底100上的疊層膜（laminate film），或者可為類似元件。離型層102的頂表面可為水平的且可具有高的共面度（degree of coplanarity）。
此外，在圖1中，形成電性連接件112。作為形成電性連接件112的實例，在離型層102之上形成晶種層。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沈積（physical vapor deposition，PVD）等形成。在晶種層上形成光阻並將所述光阻圖案化。圖案化可藉由旋轉塗佈（spin coating）等形成光阻並可將所述光阻暴露至光來進行。所述光阻的圖案對應於電性連接件112。所述圖案化會形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及在晶種層所暴露出的部分上形成導電材料。導電材料可藉由例如電鍍（electroplating）或無電鍍覆（electroless plating）等鍍覆方式來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。將光阻以及晶種層的上面未形成有導電材料的部分移除。光阻可藉由例如使用氧電漿等的合適的灰化製程（ashing process）或剝除製程（stripping process）來移除。一旦光阻被移除，則例如使用合適的蝕刻製程（例如，濕蝕刻（wet etching）或乾蝕刻（dry etching））移除晶種層所暴露出的部分。晶種層的其餘部分與導電材料則形成電性連接件112。
在圖2中，藉由黏合劑116將積體電路晶粒114黏合至離型層102。如圖2中所示，在第一封裝區600及第二封裝區602中的每一者中黏合一個積體電路晶粒114，且在其他實施例中，可在每一區中黏合更多個積體電路晶粒114。舉例而言，在實施例中，可在每一區中黏合兩個積體電路晶粒114或四個積體電路晶粒114。積體電路晶粒114可為邏輯晶粒（例如，中央處理單元（central processing unit）、微控制器等）、記憶體晶粒（例如，動態隨機存取記憶體（dynamic random access memory，DRAM）晶粒、靜態隨機存取記憶體（static random access memory，SRAM）晶粒等）、電力管理晶粒（例如，電力管理積體電路（power management integrated circuit，PMIC）晶粒）、射頻（radio frequency，RF）晶粒、感測器晶粒、微機電系統（micro-electro-mechanical-system，MEMS）晶粒、訊號處理晶粒（例如，數位訊號處理（digital signal processing，DSP）晶粒）、前端晶粒（例如，類比前端（analog front-end，AFE）晶粒）等或其組合。此外，在每一區具有多個晶粒的實施例中，積體電路晶粒114可為不同大小（例如，不同高度及/或表面積），且在其他實施例中，積體電路晶粒114可為相同大小（例如，相同高度及/或表面積）。
在將積體電路晶粒114黏合至離型層102之前，積體電路晶粒114可根據適用的製造製程以於積體電路晶粒114中形成積體電路來進行製程。舉例而言，積體電路晶粒114各自包括半導體基底118，例如是經摻雜或未經摻雜的矽、或者絕緣體上半導體（semiconductor-on-insulator，SOI）基底的主動層。半導體基底可包括：其他半導體材料，例如鍺；化合物半導體，包括碳化矽、鎵砷、磷化鎵、磷化銦、砷化銦以及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP以及/或GaInAsP；或其組合。亦可使用其他基底，例如多層式基底（multi-layered substrate）或梯度基底（gradient substrate）。在半導體基底118中及/或半導體基底118上可形成例如電晶體、二極體、電容器、電阻器等裝置，且所述裝置可藉由內連結構120對各所述裝置進行內連，藉此形成積體電路，所述內連結構120可例如是由半導體基底118上的一個或多個介電層中的金屬化圖案所形成。
積體電路晶粒114更包括用於進行外部連接的接墊122（例如，鋁接墊）。接墊122位於積體電路晶粒114的可被稱作相應主動側上。保護膜124位於積體電路晶粒114上及部分接墊122上。開口穿過保護膜124而到達接墊122。晶粒連接件126，例如導電柱（例如，包括例如銅等金屬）等，位於穿過保護膜124的開口中，並且機械地耦合至以及電性耦合至相應的接墊122。晶粒連接件126可藉由例如鍍覆等來形成。晶粒連接件126電性耦合至積體電路晶粒114的相應的積體電路。
介電材料128位於積體電路晶粒114的主動側上，例如位於保護膜124及晶粒連接件126上。介電材料128在側向上包封晶粒連接件126，且介電材料128在側向上毗鄰相應的積體電路晶粒114。介電材料128可為例如聚苯並噁唑（polybenzoxazole，PBO）、聚醯亞胺、苯並環丁烯（benzocyclobutene，BCB）等聚合物。在其他實施例中，介電材料128是由氮化物（例如是氮化矽）、氧化物（例如是氧化矽、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻雜硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG））等、類似材料或其組合形成，且介電材料128可例如藉由旋轉塗佈、疊層、化學氣相沈積（chemical vapor deposition，CVD）等來形成。
黏合劑116位於積體電路晶粒114的背側上且將積體電路晶粒114黏合至離型層102。黏合劑116可為任何適合的黏合劑、環氧樹脂（epoxy）、晶粒貼合膜（die attach film，DAF）等。在一些實施例中，黏合劑具有介於約5微米（μm）至約30微米範圍內的厚度，所述厚度是在垂直於相應的積體電路晶粒114的背側的方向上量測。黏合劑116可塗覆至積體電路晶粒114的背側，例如塗覆至相應半導體晶圓的背側，或可塗覆於載體基底100的表面之上。積體電路晶粒114可例如藉由切割（sawing）或切割（dicing）來將單體化，並使用例如拾取及放置工具（pick-and-place tool）以藉由黏合劑116而將積體電路晶粒114黏合至離型層102。
在圖3中，在各種組件上形成包封體130。包封體130可為模塑化合物、環氧樹脂等，且可藉由壓縮模塑（compression molding）、轉移模塑（transfer molding）等來塗覆包封體130。在固化之後，包封體130可經歷研磨製程（grinding process）以暴露出電性連接件112及晶粒連接件126。在研磨製程之後，電性連接件112的頂表面、晶粒連接件126的頂表面以及包封體130的頂表面為水平的。在一些實施例中，舉例而言，若電性連接件112及晶粒連接件126已暴露出，則可省略磨製。在下文中可將電性連接件112稱作通孔112。
在圖4中，形成前側重佈線結構160。前側重佈線結構160包括介電層132、140、148及156以及金屬化圖案138、146及154。
所述形成前側重佈線結構160可始於在包封體130、通孔112及晶粒連接件126上沈積介電層132。在一些實施例中，介電層132是由聚合物所形成，所述聚合物可以是感光性材料（例如，聚苯並噁唑、聚醯亞胺、苯並環丁烯等），其可使用微影罩幕來進行圖案化。在其他實施例中，介電層132是由氮化物（例如是氮化矽）、氧化物（例如是氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃等）來形成。介電層132可藉由旋轉塗佈、疊層、化學氣相沈積等或其組合來形成。
接下來，接著將介電層132圖案化。所述圖案化會形成開口，以暴露出通孔112的多個部分及晶粒連接件126的多個部分。所述圖案化可藉由以下合適的製程來進行：當介電層132為感光性材料時藉由將介電層132暴露在光下來圖案化，或者使用例如非等向性蝕刻（anisotropic etch）進行蝕刻來圖案化。若介電層132為感光性材料，則可在曝光之後對介電層132進行顯影。
接下來，在介電層132上形成具有通孔的金屬化圖案138。作為形成金屬化圖案138的實例，在介電層132之上及穿過介電層132的開口中形成晶種層（圖中未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沈積等來形成。接著在晶種層上形成光阻並將所述光阻圖案化。圖案化可藉由旋轉塗佈等來形成光阻並可將所述光阻暴露至光來進行。光阻的圖案對應於金屬化圖案138。所述圖案化會形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆等鍍覆方式來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。光阻可藉由例如使用氧電漿等的合適的灰化製程或剝除製程來移除。一旦光阻被移除，則例如使用合適的蝕刻製程（例如，藉由濕蝕刻或乾蝕刻）移除晶種層所暴露出的部分。晶種層的其餘部分與導電材料形成金屬化圖案138及通孔。所述通孔形成在穿過介電層132而到達例如是通孔112及/或晶粒連接件126的開口中。
可以介電層140及148以及包括通孔的金屬化圖案146及154重複製程，以繼續形成重佈線結構160。用於形成重佈線結構160的該些層的材料及製程可相似於介電層132以及包括通孔的金屬化圖案138，本文不再贅述。
在形成包括通孔的金屬化圖案154之後，在金屬化圖案154及介電層148上沈積介電層156。在一些實施例中，介電層156是由聚合物所形成，所述聚合物可以是感光性材料（例如，聚苯並噁唑、聚醯亞胺、苯並環丁烯等），其可使用微影罩幕來進行圖案化。在其他實施例中，介電層156是由氮化物（例如是氮化矽）、氧化物（例如是氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃等）來形成。介電層156可藉由旋轉塗佈、疊層、化學氣相沈積等或其組合來形成。
接下來，接著將介電層156圖案化。所述圖案化會形成開口，以暴露出金屬化圖案154的多個部分。所述圖案化可藉由以下合適的製程來進行：當介電層156為感光性材料時可藉由將所述介電層暴露在光下來圖案化，或者使用例如非等向性蝕刻進行蝕刻來圖案化。若介電層156為感光性材料，則可在曝光之後對介電層156進行顯影。
前側重佈線結構160為一實例。在前側重佈線結構160中可形成更多個或更少個介電層及金屬化圖案。若將形成更少個介電層及金屬化圖案，則可省略以上所述的步驟及製程。若將形成更多個介電層及金屬化圖案，則可重複以上所述的步驟及製程。此項技術中具有通常知識者將易於理解應省略或重複哪些步驟及製程。
接下來，在前側重佈線結構160的外側上形成接墊162。接墊162用於耦合至導電連接件166（參照圖5）且可被稱作凸塊下金屬（under bump metallurgy，UBM）162。在所示實施例中，接墊162是經由穿過介電層156而到達金屬化圖案154的開口來形成。作為形成接墊162的實例，在介電層156之上形成晶種層（圖中未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沈積等來形成。接著，在晶種層上形成光阻，並將所述光阻圖案化。圖案化可藉由旋轉塗佈等來形成光阻並可將所述光阻暴露至光來進行。光阻的圖案對應於接墊162。所述圖案化會形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及在晶種層所暴露出的部分上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆等鍍覆方式來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上未形成有導電材料的部分。光阻可藉由例如使用氧電漿等的合適的灰化製程或剝除製程來移除。一旦光阻被移除，則例如使用合適的蝕刻製程（例如，藉由濕蝕刻或乾蝕刻）移除晶種層所暴露出的部分。晶種層的其餘部分與導電材料形成接墊162。以不同方式形成接墊162的實施例中，可使用更多個光阻及圖案化步驟。
在圖5中，在凸塊下金屬162上形成導電連接件166。導電連接件166可為球格陣列（ball grid array，BGA）連接件、焊料球、金屬柱、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、微凸塊、無電鍍鎳鈀浸金技術（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）形成的凸塊等。導電連接件166可包括例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合等導電材料。在一些實施例中，導電連接件166藉由例如蒸鍍（evaporation）、電鍍、印刷、焊料轉移、植球（ball placement）等常用方法初步地形成焊料層來形成。在所述結構上形成焊料層後，則可執行回焊（reflow）以將材料塑型成所期望的凸塊形狀。在另一實施例中，導電連接件166為藉由濺鍍、印刷、電鍍、無電鍍覆、化學氣相沈積等而形成的金屬柱（例如，銅柱）。金屬柱可不含有焊料且具有實質上垂直的側壁。在一些實施例中，在金屬柱連接件166的頂部上形成金屬頂蓋層（圖中未示出）。金屬頂蓋層可包括鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合，且所述金屬頂蓋層可藉由鍍覆製程來形成。
在圖6中，執行載體基底剝離，以將積體電路晶粒114、通孔112及包封體130從載體基底100分離（剝離）。根據一些實施例，所述剝離包括在離型層102上投射例如雷射光或紫外光等光，以使離型層102在所述光的熱能下分解，使得載體基底100可被移除。接著將所述結構翻轉並放置於膠帶190上。
如圖6中所進一步示出，暴露出通孔112的端點。在一些實施例中，可執行蝕刻或清潔（cleaning）以移除通孔112的端點上的殘餘物。
在圖7中，移除黏合劑116以暴露出積體電路晶粒114的背側（例如，積體電路晶粒114的基底118的背側）。黏合劑116可藉由例如以下等任何適合的製程來移除：將黏合劑116剝落、在黏合劑層116上投射例如雷射光或紫外光等光以使黏合劑層116在所述光的熱能下分解、蝕刻黏合劑116等。
移除黏合劑層116會在積體電路晶粒114的背側之上形成凹陷180。凹陷180具有深度D1，深度D1是量測自包封體130的頂表面至相應積體電路晶粒114的基底118的暴露出的表面。在一些實施例中，凹陷180的深度D1介於約5微米至約30微米範圍內。
在圖8中，在積體電路晶粒114的基底118的暴露出的表面上形成接墊182。接墊182不是用於電性連接積體電路晶粒114或封裝結構中的裝置或金屬化圖案，而是用於發散來自積體電路晶粒114及/或封裝結構的熱能。在一些實施例中，可將接墊182稱作熱接墊182，熱接墊182用於發散來自積體電路晶粒114的熱能。在一些實施例中，熱接墊182不連接至積體電路晶粒114中的散熱路徑；而在一些實施例中，熱接墊182連接至積體電路晶粒114中的散熱路徑（參照例如圖12）。
熱接墊182亦用於熱連接至連接件316（參見圖9）且可被稱作凸塊下金屬（UBM）182。在所示實施例中，在積體電路晶粒114的基底118的背側上形成熱接墊182。作為形成熱接墊182的實例，在基底118的背側之上形成晶種層（圖中未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沈積等來形成。接著在晶種層上形成光阻並將所述光阻圖案化。圖案化可藉由旋轉塗佈等來形成光阻並可將所述光阻暴露至光來進行。光阻的圖案對應於熱接墊182。所述圖案化會形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆等鍍覆方式來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。光阻可藉由例如使用氧電漿等的合適的灰化製程或剝除製程來移除。一旦光阻被移除，則例如使用合適的蝕刻製程（例如，藉由濕蝕刻或乾蝕刻）移除晶種層的所暴露出的部分。晶種層的其餘部分與導電材料形成熱接墊182。以不同方式形成熱接墊182的實施例中，可使用更多個光阻及圖案化步驟。
舉例而言，在另一實施例中，在基底118的背側之上形成晶種層，並在所述晶種層上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆等鍍覆方式來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。在形成導電材料之後，可在與熱接墊182的位置相對應的導電材料之上形成罩幕，並將所述罩幕圖案化。在一些實施例中，使用光阻或硬罩幕作為所述罩幕。在將罩幕圖案化之後，例如使用合適的蝕刻製程（例如，藉由濕蝕刻或乾蝕刻）移除導電材料及晶種層的暴露出的部分（例如，不位於罩幕下方的部分導電材料及晶種層）。晶種層及導電材料的其餘部分形成熱接墊182。在此實施例中，熱接墊182可具有側壁182A，其自所述接墊的頂表面至所述接墊的底表面傾斜（例如，加寬的側壁）。如圖8中所示，熱接墊182的傾斜側壁182A意味著在此實施例中，熱接墊182具有較頂表面大的底表面。儘管在圖8中僅在熱接墊182中的一者上示出傾斜側壁182A，然而在此實施例中，所有熱接墊182將具有傾斜側壁182A。
在上述實施例中，所述導電材料形成在光阻的開口內，熱接墊182的側壁可實質上垂直於基底118的背側。
在一些實施例中，可在通孔112的暴露出的端點上形成凸塊下金屬或接墊（圖中未示出）。此凸塊下金屬或接墊的形成方式可與上述熱接墊182及/或接墊162相似，本文中不再贅述。
在圖9中，分別在通孔112及熱接墊182之上形成導電連接件314及316，並將導電連接件314及316連接至通孔112及熱接墊182。導電連接件314用於將圖9所示封裝結構電性連接至其他封裝結構（例如，圖10中的封裝結構300）。與熱接墊182相似，導電連接件316不是用於電性連接積體電路晶粒114或封裝結構中的裝置或金屬化圖案，而是用於發散來自積體電路晶粒114及/或封裝結構的熱能。因此，在下文中可將導電連接件316稱作熱連接件316。相較於不包括熱接墊及熱連接件的封裝結構，使用熱接墊182及熱連接件316使得所述封裝結構的熱阻（℃/瓦）可提高達約8%。
導電連接件314及熱連接件316可為球格陣列（BGA）連接件、焊料球、金屬柱、受控塌陷晶片連接（C4）凸塊、微凸塊、無電鍍鎳鈀浸金技術（ENEPIG）形成的凸塊等。導電連接件314及熱連接件316可包括例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合等導電材料。在一些實施例中，導電連接件314及熱連接件316藉由例如蒸鍍、電鍍、印刷、焊料轉移、植球等常用方法初步地形成焊料層來形成。在所述結構上形成焊料層後，則可執行回焊，以將材料塑型成所期望的凸塊形狀。在另一實施例中，導電連接件314及熱連接件316為藉由濺鍍、印刷、電鍍、無電鍍覆、化學氣相沈積等而形成的金屬柱（例如，銅柱）。金屬柱可不含有焊料且具有實質上垂直的側壁。在一些實施例中，在金屬柱連接件314及316的頂部上形成金屬頂蓋層（圖中未示出）。金屬頂蓋層可包括鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合，且所述金屬頂蓋層可藉由鍍覆製程來形成。
在圖10中，將封裝結構300藉由導電連接件314及熱連接件316接合至圖9所示封裝結構。封裝結構300包括基底302及耦合至基底302的一個或多個堆疊晶粒308（308A及308B）。基底302可由例如矽、鍺、金剛石等半導體材料製成。在一些實施例中，亦可使用例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、該些的組合等化合物材料。另外，基底302可為絕緣體上矽（silicon-on-insulator，SOI）基底。一般而言，絕緣體上矽基底包括例如磊晶矽、鍺、矽鍺、絕緣體上矽、絕緣體上矽鍺（silicon germanium on insulator，SGOI）或其組合等半導體材料的層。在一個替代性實施例中，基底302是基於例如玻璃纖維加強型樹脂芯（fiberglass reinforced resin core）等絕緣芯。一種示例性芯材料為例如FR4等玻璃纖維樹脂。芯材料的替代形式包括雙馬來醯亞胺三嗪（bismaleimide-triazine，BT）樹脂，或作為另一選擇為其他印刷電路板（PCB）材料或膜。基底302可使用例如味之素增層膜（Ajinomoto build-up film，ABF）等增層膜或其他疊層體。
基底302可包括主動裝置及被動裝置（圖10中未示出）。如此項技術中具有通常知識者所將認識到，可使用各式各樣的裝置（例如電晶體、電容器、電阻器、該些的組合）等來產生對半導體封裝體300的設計的結構性及功能性要求。所述裝置可使用任何適合的方法來形成。
基底302亦可包括金屬化層（圖中未示出）及通孔306。在主動裝置及被動裝置之上可形成金屬化層並將所述金屬化層設計成連接各種裝置以形成功能性電路系統。金屬化層可由交替的介電質（例如，低介電常數介電材料（low-k dielectric material））層與導電材料（例如，銅）層形成，且所述金屬化層可藉由任何適合的製程（例如，沈積、鑲嵌（damascene）、雙重鑲嵌（dual damascene）等）來形成。所述導電材料層具有對各所述導電材料層進行內連的通孔。在一些實施例中，基底302實質上不含有主動裝置及被動裝置。
基底302可在基底302的第一側上具有耦合至堆疊晶粒308的接合墊303，並且在基底302的第二側上具有耦合至連接件314及316的接合墊304及熱接墊305，基底302的所述第二側與基底302的所述第一側相對。在一些實施例中，省略熱接墊305。在一些實施例中，接合墊303及304以及熱接墊305可藉由在基底302的第一側及第二層上的介電層（圖中未示出）中形成凹陷（圖中未示出）來形成。凹陷可形成為使得接合墊303及304以及熱接墊305能夠嵌置於介電層中。在其他實施例中，當接合墊303及304以及熱接墊305可形成於介電層上時可省略凹陷。在一些實施例中，接合墊303及304以及熱接墊305包括由銅、鈦、鎳、金、鈀等或其組合製成的薄的晶種層（圖中未示出）。在薄的晶種層之上可沈積接合墊303及304以及熱接墊305的導電材料。導電材料可藉由電化學鍍覆製程、無電鍍覆製程、化學氣相沈積、原子層沈積（atomic layer deposition，ALD）、物理氣相沈積等或其組合來形成。在實施例中，接合墊303及304以及熱接墊305的導電材料為銅、鎢、鋁、銀、金等或其組合。
在實施例中，接合墊303及304以及熱接墊305為包括三個導電材料層（例如，鈦層、銅層以及鎳層）的凸塊下金屬。然而，此項技術中具有通常知識者將認識到，多種適合的材料及層的排列形式適合形成凸塊下金屬303、304、及305，其可例如為鉻/鉻-銅合金/銅/金的排列形式、為鈦/鈦鎢/銅的排列形式、或為銅/鎳/金的排列形式。任何可用於凸塊下金屬303、304、及305的適合的材料或材料層將完全涵蓋於本申請案的範圍內。在一些實施例中，通孔306延伸穿過基底302，並將至少一個接合墊303耦合至至少一個接合墊304。
在所示實施例中，儘管可使用其他連接形式（例如導電凸塊等），然而亦可藉由導線接合件310將堆疊晶粒308耦合至基底302。在一實施例中，堆疊晶粒308為堆疊記憶體晶粒。舉例而言，堆疊記憶體晶粒308可包括低功率（low-power，LP）雙倍資料速率（double data rate，DDR）記憶體模組或者類似的記憶體模組，例如是LPDDR1、LPDDR2、LPDDR3、LPDDR4等。
在一些實施例中，堆疊晶粒308及導線接合件310可藉由模塑材料312來包封。模塑材料312可例如使用壓縮模塑法模塑於堆疊晶粒308及導線接合件310上。在一些實施例中，模塑材料312為模塑化合物、聚合物、環氧樹脂、氧化矽填料材料等或其組合。可執行固化步驟以將模塑材料312固化，其中所述固化可為熱固化（thermal curing）、紫外固化（UV curing）等或其組合。
在一些實施例中，堆疊晶粒308及導線接合件310被埋置於模塑材料312中，且在將模塑材料312固化之後，執行例如磨製等平坦化步驟（planarization step），以移除模塑材料312的過量部分，並為第二封裝體300提供實質上為平坦的表面。
在形成第二封裝體300之後，藉由導電連接件314、接合墊304以及通孔112而將封裝體300接合至第一封裝體200。在一些實施例中，堆疊記憶體晶粒308可經由導線接合件310、接合墊303及304、通孔306、導電連接件314、通孔112以及重佈線結構160而耦合至積體電路晶粒114。
在一些實施例中，在接合導電連接件314及熱連接件316之前，使用例如免清潔焊劑（no-clean flux）等焊劑（圖中未示出）來塗佈導電連接件314及熱連接件316。導電連接件314及熱連接件316可浸入於焊劑中，或可將所述焊劑噴射至導電連接件314及熱連接件316上。在另一實施例中，可將焊劑塗覆至通孔112的暴露出的表面。
在一些實施例中，在將上部封裝體300貼合至下部封裝體之後，且在對導電連接件314及熱連接件316的剩餘的環氧樹脂焊劑的至少一些環氧樹脂部分進行回焊之前，在導電連接件314及熱連接件316上可形成有環氧樹脂焊劑（圖中未示出）。此剩餘的環氧樹脂部分可充當底部填充劑（underfill）以減小應力並保護因對導電連接件314及熱連接件316進行回焊而得到的接點（joint）。在一些實施例中，可在上部封裝體300與下部封裝體之間形成環繞導電連接件314及熱連接件316的底部填充劑（圖10中未示出但參見圖11中的底部填充劑320）。底部填充劑320可為例如聚合物、環氧樹脂、模塑底部填充劑等任何合適的材料。底部填充劑320可以是在貼合上部封裝體300之後藉由毛細流動製程（capillary flow process）來形成，或可以是在貼合上部封裝體300之前藉由適合的沈積方法來形成。
上部封裝體300與下部封裝體之間的接合可為焊料接合或直接金屬-金屬（例如，銅-銅或錫-錫）接合。在實施例中，藉由回焊製程將上部封裝體300接合至下部封裝體。在此回焊製程期間，導電連接件314接觸接合墊304及通孔112，以將上部封裝體300物理性地連接至且電性連接至下部封裝體。另外，在回焊製程期間，熱連接件316接觸熱接墊305（若存在）及熱接墊182，以物理性地連接且熱連接積體電路晶粒114以及熱接墊182、熱連接件316及熱接墊305。在接合製程之後，可在通孔112與導電連接件314及熱接墊182與熱連接件316的界面處形成金屬間化合物（intermetallic compound，IMC）（圖中未示出）。另外，亦可在導電連接件314與接合墊304及熱連接件316與熱接墊305之間的界面處形成金屬間化合物（圖中未示出）。
在圖11中，將下部封裝體單體化成多個下部封裝體200。單體化製程可藉由沿例如位於相鄰區600與602之間的切割道（scribe line）進行切割來執行。在一些實施例中，單體化製程包括切割、雷射單體化（laser singulation）、蝕刻等。單體化製程將第一封裝區600與第二封裝區602隔開。圖11說明可來自第一封裝區600或第二封裝區602中的一者所得之單體化封裝體200。亦可將封裝體200稱作整合扇出型（integrated fan-out，InFO）封裝體200。
圖12說明包括封裝體200（可被稱作第一封裝體200）、封裝體300（可被稱作第二封裝體300）以及基底400的半導體封裝體500。
半導體封裝體500包括安裝至基底400的封裝體200及300。基底400可稱作封裝基底400。封裝體200可以使用導電連接件166安裝至封裝基底400。
封裝基底400可由例如矽、鍺、金剛石等半導體材料製成。作為另一選擇，亦可使用例如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、該些的組合等化合物材料。另外，封裝基底400可為絕緣體上矽基底。一般而言，絕緣體上矽基底包括例如磊晶矽、鍺、矽鍺、絕緣體上矽、絕緣體上矽鍺或其組合等半導體材料的層。在一個替代性實施例中，封裝基底400是基於例如玻璃纖維加強型樹脂芯等絕緣芯。一種示例性芯材料為例如FR4等玻璃纖維樹脂。芯材料的替代形式包括雙馬來醯亞胺三嗪BT樹脂，或作為另一選擇為其他印刷電路板材料或膜。封裝基底400可以是使用例如味之素增層膜等增層膜或其他疊層體。
封裝基底400可包括主動裝置及被動裝置（圖12中未示出）。如此項技術中具有通常知識者所將認識到，可使用例如電晶體、電容器、電阻器、該些的組合等各種各樣的裝置來產生對半導體封裝體500的設計的結構性及功能性要求。所述裝置可使用任何適合的方法來形成。
封裝基底400亦可包括金屬化層及通孔（圖中未示出）以及位於所述金屬化層及通孔之上的接合墊402。在主動裝置及被動裝置之上可形成金屬化層並將所述金屬化層設計成連接各種裝置以形成功能性電路系統。金屬化層可由交替的介電質（例如，低介電常數介電材料）層與導電材料（例如，銅）層形成且所述金屬化層可藉由任何適合的製程（例如，沈積、鑲嵌、雙重鑲嵌等）來形成。所述導電材料層具有對各所述導電材料層進行內連的通孔。在一些實施例中，封裝基底400實質上不含有主動裝置及被動裝置。
在一些實施例中，可對導電連接件166進行回焊以將封裝體200貼合至接合墊402。導電連接件166將基底400（包括基底400中的金屬化層）電性耦合至及物理性地耦合至第一封裝體200。
在封裝體200貼合至基底400之後，且在對導電連接件166的剩餘的環氧樹脂焊劑的至少一些環氧樹脂部分進行回焊之前，導電連接件166上可形成有環氧樹脂焊劑（圖中未示出）。此剩餘的環氧樹脂部分可充當底部填充劑以減小應力並保護因對導電連接件166進行回焊而得到的接點。在一些實施例中，可在第一封裝體200與基底400之間形成環繞導電連接件166的底部填充劑（圖中未示出）。所述底部填充劑可在貼合封裝體200之後藉由毛細流動製程來形成，或可在貼合封裝體200之前藉由適合的沈積方法來形成。
圖13A及圖13B說明根據一些實施例的另一封裝結構的剖視圖及平面圖。除了圖13A及圖13B中的實施例包括位於封裝體200與300之間的區域330不含有導電連接件314之外，圖13A及圖13B中的此實施例相似於圖1至圖12中所示實施例。本文中將不再贅述與此實施例有關的和前面所述實施例的細節相似的細節。
在此實施例中，封裝體200與300之間的區域330不含有導電連接件314。如圖13B所示平面圖中所示，區域330位於封裝體300的晶粒308中的一者或多者的佔用面積（footprint）308內。由於晶粒308不會接收來自於封裝體200的晶粒114所發散的熱能，因此有助於降低晶粒308在運作期間的溫度。在平面圖中，區域330可位於封裝體的中心區中。在一些實施例中，在平面圖中，區域330位於封裝體的周邊區中，而在一些實施例中，區域330位於中心區與周邊區二者中。藉由移除處於晶粒308中的一者或多者中的佔用面積308內的一些導電連接件314，可降低晶粒308在運作期間的溫度。
本發明的其他所揭露實施例的封裝體中可包括此實施例的不含有導電連接件314的區域330。
圖14說明根據一些實施例的封裝結構的剖視圖。除了圖14中的實施例在積體電路晶粒114的基底118中包括通孔702之外，圖14的實施例相似於圖1至圖12中所示的實施例。本文中將不再贅述與此實施例有關的和前面所述實施例的細節相似的細節。
在此實施例中，積體電路晶粒114可具有形成於基底118中的一個或多個通孔702，其有助於發散來自所述積體電路晶粒內的裝置的熱能。舉例而言，通孔702可熱連接至積體電路晶粒114中的電晶體，以使得由所述電晶體所產生的熱可以更輕易地自積體電路晶粒114移除。通孔702可進一步改善本發明的其他實施例的散熱。熱接墊182可物理性地連接至通孔702，以幫助發散來自積體電路晶粒114內的裝置的熱能。在一些實施例中，通孔702被形成為局部地穿過積體電路晶粒114的基底118，而在一些實施例中，通孔702被形成為實質上穿過積體電路晶粒114的基底118。
在積體電路晶粒114貼合至載體（參見例如圖2）之前，可在積體電路晶粒114中形成通孔702。通孔702可藉由在積體電路晶粒114的基底118中形成開口，並接著以導電材料填充所述開口來形成。開口可藉由合適的微影（photolithography）技術及蝕刻技術來形成。在形成開口之後，在所述開口中形成襯墊（例如擴散阻障層、黏著層等）以及導電材料。襯墊可包括鈦、氮化鈦、鉭、氮化鉭等。導電材料可為銅、銅合金、銀、金、鎢、鋁、鎳、鈷等。可執行例如化學機械研磨製程（chemical mechanical polishing process，CMP）等平坦化製程，以移除基底118的表面上過量的材料。其餘襯墊及導電材料在開口中形成通孔702。
熱接墊182接著形成於積體電路晶粒114的基底118的背側上，且物理性地接觸通孔702。熱接墊182可如上述實施例中所述般形成且本文中不再贅述。
本發明的其他所揭露實施例的晶粒及虛擬晶粒中可包括此實施例的通孔702。
圖15至圖18說明根據一些實施例的在第三封裝結構的製程期間的各中間步驟的剖視圖。除了在圖15至圖18中的實施例中熱接墊712會在積體電路晶粒114貼合至載體基底100之前形成於積體電路晶粒114的基底118的背側上以外，圖15至圖18中的此實施例相似於圖1至圖12中所示實施例。本文中將不再對與此實施例有關的和前面所述實施例的細節相似的細節予以贅述。
圖15說明與如上述圖2的等效的中間製程階段且本文中不再贅述。在圖15中，將熱接墊712形成為積體電路晶粒114的形成製程的一部分。舉例而言，在將黏合劑116形成於積體電路晶粒114的基底118的背側之上之前，可將熱接墊712形成為相似於積體電路晶粒114的背側重佈線結構。
熱接墊712形成在積體電路晶粒114的基底118的背側表面上。熱接墊712不是用於電性連接至積體電路晶粒114或封裝結構中的裝置或金屬化圖案，而是用於發散來自積體電路晶粒114及/或封裝結構的熱能。在一些實施例中，熱接墊712不連接至積體電路晶粒114中的散熱路徑，而在一些實施例中，熱接墊182連接至積體電路晶粒114（參照例如圖12）中的散熱路徑。
熱接墊712亦用於物理性地連接至及熱連接至連接件316（參照例如圖18）且可被稱作凸塊下金屬712。在所示實施例中，在積體電路晶粒114的基底118的背側上形成熱接墊712。作為形成熱接墊712的實例，在基底118的背側之上形成晶種層（圖中未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沈積等來形成。接著在晶種層上形成光阻並將所述光阻圖案化。圖案化可藉由旋轉塗佈等來形成光阻並可將所述光阻暴露至光來進行。光阻的圖案對應於熱接墊712。所述圖案化會形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆等鍍覆方式來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。光阻可藉由例如使用氧電漿等的合適的灰化製程或剝除製程來移除。一旦光阻被移除，則例如使用合適的蝕刻製程（例如，藉由濕蝕刻或乾蝕刻）移除晶種層的暴露出的部分。晶種層的其餘部分與導電材料形成熱接墊712。在以不同方式形成熱接墊712的實施例中，可使用更多個光阻及圖案化步驟。
圖16說明對圖15所示結構的進一步製程。所述兩個圖之間的製程相似於以上參照圖3至圖6所說明及所闡述的製程，圖6是與圖16等效的中間階段，本文中不再贅述圖16。
在圖17中，移除黏合劑116以暴露出熱接墊712及積體電路晶粒114的背側（例如，積體電路晶粒114的基底118的背側）。黏合劑116可藉由例如以下等任何適合的製程來移除：將黏合劑116剝落、在黏合劑層116上投射例如雷射光或紫外光等光以使黏合劑層116在所述光的熱能下分解、蝕刻黏合劑116等。
移除黏合劑層116會在積體電路晶粒114的背側之上形成凹陷714。凹陷714具有深度D2，深度D2是量測自包封體130的頂表面至相應積體電路晶粒114的基底118的暴露出的表面。在一些實施例中，凹陷714的深度D2介於約5微米至約30微米範圍內。
圖18說明對圖17所示結構的進一步製程。所述兩個圖之間的製程相似於以上參照圖9至圖12所說明及所闡述的製程，圖12是與圖18等效的中間階段，本文中不再贅述圖18。
圖19至圖21說明根據一些實施例的在另一封裝結構的製程期間的各中間步驟的剖視圖。除了在圖19至圖21中的實施例中將積體電路晶粒114貼合至虛擬晶粒且在所述虛擬晶粒的背側上形成熱接墊808以外，圖19至圖21中的此實施例相似於圖1至圖12中所示實施例。本文中將不再對與此實施例有關的和前面所述實施例的細節相似的細節予以贅述。
圖19說明與上述圖2等效的中間製程階段且本文中不再贅述。在圖19中，藉由黏合劑804將虛擬晶粒802黏合至離型層102，且藉由黏合劑806將積體電路晶粒114黏合至虛擬晶粒802。在一些實施例中，虛擬晶粒802是由剛性材料（rigid material）形成，所述剛性材料的楊氏係數（Young’s modulus）可等於或大於矽的楊氏係數（約165吉帕（GPa）至約179吉帕）。因此，虛擬晶粒802的楊氏係數可等於或大於約165吉帕。
在將虛擬晶粒802黏合至離型層102之前，可根據適用於虛擬晶粒802的製造製程來處理虛擬晶粒802。舉例而言，虛擬晶粒802可藉由製備虛擬晶圓並將所述虛擬晶圓單體化來形成。虛擬晶圓可為半導體晶圓，例如矽晶圓。在一些實施例中，虛擬晶圓可為金屬晶圓。可例如在研磨製程中將虛擬晶圓薄化。虛擬晶圓的所得厚度足夠大而使得所述虛擬晶圓可對在後續步驟中形成的上覆結構提供充足的機械支撐。
虛擬晶粒802可具有良好導熱係數（thermal conductivity）。虛擬晶粒802的導熱係數可接近於上覆積體電路晶粒114中的半導體基底（例如，矽基底）的導熱係數（例如，大於所述半導體基底的導熱係數的90%）。舉例而言，矽具有等於約148瓦/(米·度)（W/(m*K)）的導熱係數，且因此虛擬晶圓24的導熱係數可大於約135 W/(m*K)或更高。由於虛擬晶粒802具有高的導熱係數，因此所得結構中的散熱得到改善。
根據本發明的一些實施例，虛擬晶粒802由金屬或金屬合金、半導體材料、或介電材料形成。舉例而言，當虛擬晶粒802包括金屬時，虛擬晶粒802可由銅、鋁、鎳等形成，且因此根據一些實施例，虛擬晶粒802為金屬膜/金屬板。當虛擬晶粒802由半導體材料形成時，虛擬晶粒802可為單體化矽晶圓，所述單體化矽晶圓可與上面形成有積體電路晶粒114的晶圓相同類型的晶圓。當虛擬晶粒802由介電材料形成時，虛擬晶粒802可由陶瓷形成。另外，虛擬晶粒802的材料可為均質的（homogenous）。舉例而言，虛擬晶粒802中的每一者的整體可由相同的材料形成，所述材料包括相同的元素，且在所有虛擬晶粒802中各所述元素的原子百分比（atomic percentage）可為均勻的。根據一些示例性實施例，虛擬晶粒802是由矽形成，在虛擬晶粒802中摻雜有p型或n型雜質。根據替代性實施例，虛擬晶粒802中可不摻雜p型雜質及n型雜質。
在圖19中，藉由黏合劑806將積體電路晶粒114黏合至虛擬晶粒802。在一些實施例中，黏合劑806為導電層（在下文中可稱作導電層806），導電層806是與熱接墊712相似的方式形成，只是導電層806可跨越積體電路晶粒114的整個背側。
導電層806並不是用於電性連接積體電路晶粒114或封裝結構中的裝置或金屬化圖案，而是用於發散來自積體電路晶粒114及/或封裝結構的熱能。在一些實施例中，可將導電層806稱作熱層806，熱層806用以將來自積體電路晶粒114的熱能發散至虛擬晶粒802。在一些實施例中，導電層806不連接至積體電路晶粒114中的散熱路徑，而在一些實施例中，熱層806藉由通孔（參照例如圖14）而連接至積體電路晶粒114中的散熱路徑。
熱層806亦用於熱連接至虛擬晶粒802。在所示實施例中，在積體電路晶粒114的基底118的背側上形成熱層806。作為形成熱層806的實例，在基底118的背側之上形成晶種層（圖中未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沈積等來形成。在晶種層上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆等鍍覆方式來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。晶種層與導電材料形成熱層806。
圖20說明對圖19所示結構的進一步製程。所述兩個圖之間的製程相似於以上參照圖3至圖8所說明及所闡述的製程，圖8是與圖20等效的中間階段，本文中不再贅述圖20。
在圖20中，在虛擬晶粒802的背側上形成熱接墊808。熱接墊808具有與形成圖8所示熱接墊182相似的材料及方法且本文中不再贅述。
圖21說明對圖20所示結構的進一步製程。所述兩個圖之間的製程相似於以上參照圖8至圖12所說明及所闡述的製程，圖12是與圖21等效的製程階段，本文中不再贅述圖21。
本發明的其他所揭露實施例的封裝體中可包括此實施例的虛擬晶粒802。
圖22至圖25說明根據一些實施例的在另一封裝結構的製程期間的各中間步驟的剖視圖。除了在圖22至圖25中的實施例中積體電路晶粒114具有背側重佈線結構以外，圖22至圖25中的此實施例相似於圖1至圖12中所示實施例。本文中將不再對與此實施例有關的和前面所述實施例的細節相似的細節予以贅述。
圖22說明與以上所述圖7等效的中間製程階段且本文中不再贅述。在形成晶種層902之前，位於積體電路晶粒114的基底118的暴露出的表面之上的凹陷具有深度D3，深度D3是量測自包封體130的頂表面至相應積體電路晶粒114的基底118的暴露出的表面。在一些實施例中，凹陷714的深度D3介於約5微米至約30微米範圍內。
在圖22中，在圖7所示結構的積體電路晶粒114的基底118的暴露出的表面上形成晶種層902。在一些實施例中，晶種層902為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層902包括鈦層及位於所述鈦層之上的銅層。晶種層902可使用例如物理氣相沈積等來形成。
在圖23及圖24中，形成背側重佈線結構920。背側重佈線結構920包括介電層904、908、912以及金屬化圖案906、910、及914。
形成背側重佈線結構920可開始於在晶種層902上沈積介電層904。在一些實施例中，介電層904是由聚合物所形成，所述聚合物可以是感光性材料（例如，聚苯並噁唑、聚醯亞胺、苯並環丁烯等），其可使用微影罩幕來進行圖案化。在其他實施例中，介電層904是由氮化物（例如是氮化矽）、氧化物（例如是氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃等）來形成。介電層904可藉由旋轉塗佈、疊層、化學氣相沈積等或其組合來形成。
接下來，接著將介電層904圖案化。所述圖案化會形成開口，以暴露出晶種層902的多個部分。所述圖案化可藉由例如以下等合適的製程來進行：當介電層904為感光性材料時將介電層904暴露在光下，或者使用例如非等向性蝕刻來進行蝕刻。若介電層904為感光性材料，則可在曝光之後對介電層904進行顯影。
接下來，在介電層904中形成通孔906。作為形成通孔906的實例，在介電層904的開口中及在晶種層902的暴露出的部分上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆等鍍覆方式來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。晶種層的其餘部分與導電材料形成金屬化圖案138及通孔。在穿過介電層132而到達例如通孔112及/或晶粒連接件126的開口中形成所述通孔。可執行例如化學機械研磨等平坦化製程以自介電層904的表面移除過量導電材料。其餘導電材料形成通孔906。在化學機械研磨之後，通孔906的表面、介電層904的表面、包封體130的表面及通孔112的表面可為水平的。
通孔906並不是用於電性連接積體電路晶粒114或封裝結構中的裝置或金屬化圖案，而是用於發散來自積體電路晶粒114及/或封裝結構的熱能。在一些實施例中，可將通孔906稱作熱通孔906，熱通孔906用於發散來自積體電路晶粒114的熱能。在一些實施例中，熱通孔906不連接至積體電路晶粒114中的散熱路徑；而在一些實施例中，熱通孔906連接至積體電路晶粒114（參照例如圖14）中的散熱路徑。熱通孔906亦用於熱連接至背側重佈線結構920（參見圖24）中的金屬化圖案。如所示，熱通孔906具有自熱通孔906的頂表面至熱通孔906的底表面漸縮的側壁。
在圖24中，在包封體130、通孔112、介電層904及熱通孔906上形成介電層908。在一些實施例中，介電層908是由聚合物所形成，所述聚合物可為可以是感光性材料（例如，聚苯並噁唑、聚醯亞胺、苯並環丁烯等），其可使用微影罩幕來進行圖案化。在其他實施例中，介電層908是由氮化物（例如是氮化矽）、氧化物（例如是氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃等）來形成。介電層908可藉由旋轉塗佈、疊層、化學氣相沈積等或其組合來形成。
接下來，接著將介電層908圖案化。所述圖案化會形成開口，以暴露出通孔112的多個部分及熱通孔906的多個部分。所述圖案化可藉由例如以下等合適的製程來進行：當介電層908為感光性材料時將介電層908暴露在光下，或者使用例如非等向性蝕刻來進行蝕刻。若介電層908為感光性材料，則可在曝光之後對介電層908進行顯影。
接下來，在介電層908上形成具有通孔的金屬化圖案910。作為形成金屬化圖案910的實例，在介電層908之上及在穿過介電層908的開口中形成晶種層（圖中未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沈積等來形成。接著在晶種層上形成光阻並將所述光阻圖案化。圖案化可藉由旋轉塗佈等來形成光阻並可將所述光阻暴露至光來進行。光阻的圖案對應於金屬化圖案910。所述圖案化會形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆等鍍覆方式來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。光阻可藉由例如使用氧電漿等的合適的灰化製程或剝除製程來移除。一旦光阻被移除，則例如使用合適的蝕刻製程（例如，藉由濕蝕刻或乾蝕刻）移除晶種層的暴露出的部分。晶種層的其餘部分與導電材料形成金屬化圖案910及通孔。在穿過介電層908而到達例如通孔112及/或熱通孔906的開口中形成所述通孔。
在形成包括通孔的金屬化圖案910之後，在金屬化圖案910及介電層908上沈積介電層912。在一些實施例中，介電層912是由聚合物所形成，所述聚合物可為可以是感光性材料（例如，聚苯並噁唑、聚醯亞胺、苯並環丁烯等），其可使用微影罩幕來進行圖案化。在其他實施例中，介電層912是由氮化物（例如是氮化矽）、氧化物（例如是氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃等）來形成。介電層912可藉由旋轉塗佈、疊層、化學氣相沈積等或其組合來形成。
接下來，接著將介電層912圖案化。所述圖案化會形成開口，以暴露出金屬化圖案910的多個部分。所述圖案化可藉由例如以下等合適的製程來進行：當介電層912為感光性材料時將所述介電層暴露在光下，或者使用例如非等向性蝕刻來進行蝕刻。若介電層912為感光性材料，則可在曝光之後對介電層912進行顯影。
示出背側重佈線結構920作為實例。可在背側重佈線結構920中形成更多個或更少個介電層及金屬化圖案。若將形成更少個介電層及金屬化圖案，則可省略以上所述的步驟及製程。若將形成更多個介電層及金屬化圖案，則可重複以上所述的步驟及製程。此項技術中具有通常知識者將易於理解應省略或重複哪些步驟及製程。
接下來，在前側重佈線結構160的外側上形成接墊914。接墊914用於耦合至導電連接件316及314（參照圖25）且可被稱作凸塊下金屬（UBM）914。在所示實施例中，經由穿過介電層912而到達金屬化圖案910的開口來形成接墊914。作為形成接墊914的實例，在介電層912之上形成晶種層（圖中未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沈積等來形成。接著在晶種層上形成光阻並將所述光阻圖案化。圖案化可藉由旋轉塗佈等來形成光阻並可將所述光阻暴露至光來進行。光阻的圖案對應於接墊914。所述圖案化會形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆等鍍覆方式來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。光阻可藉由例如使用氧電漿等的合適的灰化製程或剝除製程來移除。一旦光阻被移除，則例如使用合適的蝕刻製程（例如，藉由濕蝕刻或乾蝕刻）移除晶種層所暴露出的部分。晶種層的其餘部分與導電材料形成接墊914。以不同方式形成接墊914的實施例中，可使用更多個光阻及圖案化步驟。
背側重佈線結構920及接墊914藉由導電連接件314而將通孔112及封裝體900電性耦合至隨後接合的封裝體300。
圖25說明對圖24所示結構的進一步製程。所述兩個圖之間的製程相似於以上參照圖8至圖12所說明及所闡述的製程，圖12是與圖25等效的製程階段，本文中不再贅述圖25。
本發明的其他所揭露實施例的封裝體中可包括此實施例的背側重佈線結構920及熱通孔906。
圖26至圖29說明根據一些實施例的在另一封裝結構的製程期間的各中間步驟的剖視圖。除了在圖26至圖29中的實施例中在形成通孔906之前執行平坦化製程以移除凹陷以外，圖26至圖29中的此實施例相似於圖22至圖25中所示實施例。本文中將不再對與此實施例有關的和前面所述實施例的細節相似的細節予以贅述。
圖26說明與圖7等效的中間製程階段，本文中不再贅述。在此實施例中，位於積體電路晶粒114的基底118的暴露出的表面之上的凹陷具有深度D3，深度D3是量測自包封體130的頂表面至相應積體電路晶粒114的基底118的暴露出的表面。在一些實施例中，凹陷714的深度D3介於約5微米至約30微米範圍內。
在圖27中，可執行例如化學機械研磨等平坦化製程，以使積體電路晶粒114的基底118的表面、包封體130的表面以及通孔112的表面為水平的。換言之，平坦化製程會移除凹陷。
在圖28中，在積體電路晶粒114的基底118的平坦化表面、包封體130的平坦化表面以及通孔112的平坦化表面之上形成晶種層902、介電層904以及通孔906。該些結構的材料及形成已在前面的實施例中進行了闡述，本文中不再贅述。在此實施例中，通孔906中的一些通孔電性連接至且物理性地連接至通孔112，以將通孔112電性耦合至隨後接合的封裝體300。通孔906中的另一些通孔則用作熱通孔（例如，直接上覆於積體電路晶粒114的基底118上的通孔906）。
圖29說明對圖28所示結構的進一步製程。所述兩個圖之間的製程相似於以上參照圖23至圖25所說明及所闡述的製程，圖25是與圖29等效的製程階段，本文中不再贅述圖29。在圖29中，背側重佈線結構930與前面的實施例的背側重佈線結構920相似且已說明過，故不再贅述。
本發明的其他所揭露實施例的封裝體中可包括此實施例的背側重佈線結構930及熱通孔906。
圖30至圖35說明根據一些實施例的在另一封裝結構的製程期間的各中間步驟的剖視圖。除了在圖30至圖35中的實施例中在將積體電路晶粒114貼合至載體之前，在所述載體之上形成背側重佈線結構以外，圖30至圖35中的此實施例相似於圖1至圖12中所示實施例。本文中將不再對與此實施例有關的和前面所述實施例的細節相似的細節予以贅述。
圖30說明如上述在圖1中所述的載體基底100及位於所述載體基底之上的離型層102且本文中不再贅述。在圖30中，進一步在離型層102之上形成介電層1001、金屬化圖案1004及1005、介電層1002、以及通孔112。
在離型層102上形成介電層1001。介電層1001的底表面可接觸離型層102的頂表面。在一些實施例中，介電層1001是由例如聚苯並噁唑、聚醯亞胺、苯並環丁烯等聚合物形成。在其他實施例中，介電層1001是由氮化物（例如是氮化矽）、氧化物（例如是氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃等）類似材料來形成。介電層1001可藉由例如旋轉塗佈、化學氣相沈積疊層等或其組合等可接收沈積製程來形成。
在介電層1001上形成金屬化圖案1004及1005。作為形成金屬化圖案1004及1005的實例，在介電層1001之上形成晶種層（圖中未示出）。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沈積等來形成。接著在晶種層上形成光阻並將所述光阻圖案化。圖案化可藉由旋轉塗佈等來形成光阻並可將所述光阻暴露至光來進行。光阻的圖案對應於金屬化圖案1004及1005。所述圖案化會形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆等鍍覆方式來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。接著，移除光阻以及晶種層的上面未形成有導電材料的部分。光阻可藉由例如使用氧電漿等的合適的灰化製程或剝除製程來移除。一旦光阻被移除，則例如使用合適的蝕刻製程（例如，藉由濕蝕刻或乾蝕刻）移除晶種層的暴露出的部分。晶種層的其餘部分與導電材料形成金屬化圖案1004及1005。
在金屬化圖案1004及1005以及介電層1001上形成介電層1002。在一些實施例中，介電層1002是由聚合物所形成，所述聚合物可以是感光性材料（例如，聚苯並噁唑、聚醯亞胺、苯並環丁烯等），其可使用微影罩幕來進行圖案化。在其他實施例中，介電層1002是由由氮化物（例如是氮化矽）、氧化物（例如是氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃等）來形成。介電層1002可藉由旋轉塗佈、疊層、化學氣相沈積等或其組合來形成。
介電層1001及1002以及金屬化圖案1004及1005可稱作背側重佈線結構。如圖所示，背側重佈線結構包括所述兩個介電層1001及1002以及一個金屬化圖案1004。在其他實施例中，背側重佈線結構可包括任意數目的介電層、金屬化圖案、以及通孔。可藉由重複用於形成金屬化圖案1004及介電層1002的製程，以在背側重佈線結構中形成一個或多個其他金屬化圖案及介電層。通孔可在藉由在底下介電層的開口中形成金屬化圖案的晶種層及導電材料來形成所述金屬化圖案的過程期間形成。所述通孔可因此對各種金屬化圖案進行內連及電性耦合。
將介電層1002圖案化以形成開口1006，以暴露出金屬化圖案1004及1005的多個部分。所述圖案化可藉由例如以下等合適的製程來進行：當介電層1002為感光性材料時將所述介電層暴露在光下，或者使用例如非等向性蝕刻來進行蝕刻。如圖30中所示，將介電層1002圖案化以暴露出金屬化圖案1004及1005中的一部分，而非金屬化圖案1004及1005中的所有。舉例而言，開口1006暴露出一些金屬化圖案1005，其將位於後續貼合的積體電路晶粒114之下，且開口1006亦將暴露出上面將形成通孔112的其他金屬化圖案1004，而另外的金屬化圖案1004仍被介電層1002覆蓋。
此外，在圖30中，形成通孔112。作為形成通孔112的實例，在背側重佈線結構（例如，介電層1002以及金屬化圖案1004的暴露出的部分）之上形成晶種層。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沈積等來形成。在晶種層上形成光阻並將所述光阻圖案化。圖案化可藉由旋轉塗佈等來形成光阻並可將所述光阻暴露至光來進行。光阻的圖案對應於通孔。所述圖案化會形成穿過光阻的開口，以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。導電材料可藉由例如電鍍或無電鍍覆等鍍覆方式來形成。導電材料可包括金屬，如銅、鈦、鎢、鋁等。移除光阻以及晶種層的上面未形成有導電材料的部分。光阻可藉由例如使用氧電漿等的合適的灰化製程或剝除製程來移除。一旦光阻被移除，則例如使用合適的蝕刻製程（例如，藉由濕蝕刻或乾蝕刻）移除晶種層的暴露出的部分。晶種層的其餘部分與導電材料形成通孔112。
在圖31中，藉由層1010而將積體電路晶粒114黏合至背側重佈線結構。前面闡述了積體電路晶粒114且本文中不再贅述。如圖31中所示，在第一封裝區600及第二封裝區602中的每一者中黏合一個積體電路晶粒114，且在其他實施例中，可在每一區中黏合更多個積體電路晶粒114。舉例而言，在實施例中，可在每一區中黏合兩個積體電路晶粒114或四個積體電路晶粒114。
層1010位於積體電路晶粒114的背側上且將積體電路晶粒114黏合至背側重佈線結構。層1010可為高介電常數晶粒貼合膜（high-k DAF）、導電膏（例如，銀膏）等。如圖31中所示，層1010向下延伸至位於積體電路晶粒114之下的開口1006中的一些開口中，以接觸該些開口1006所暴露出的金屬化圖案1005。層1010可施於積體電路晶粒114的背側，例如施於相應半導體晶圓的背側或可施加在載體基底100的表面之上。可藉由例如切割或切割來將積體電路晶粒114單體化並使用例如拾取及放置工具，以藉由層1010而將積體電路晶粒114黏合至背側重佈線結構。
層1010（例如，高介電常數晶粒貼合膜或導電膏）不是用於電性連接積體電路晶粒114或封裝結構中的裝置或金屬化圖案，而是用於發散來自積體電路晶粒114及/或封裝結構的熱能。在一些實施例中，可將層1010稱作熱膏1010，熱膏1010用於發散來自積體電路晶粒114的熱能。在一些實施例中，不將熱膏1010連接至積體電路晶粒114中的散熱路徑，而在一些實施例中，將熱膏1010連接至積體電路晶粒114（參照例如圖14）中的散熱路徑。使用熱膏1010將積體電路晶粒114熱連接至背側重佈線結構中的金屬化圖案1005，接著將金屬化圖案1005熱連接至連接件316（參照例如圖35）。因此，在下文中可將金屬化圖案1005稱作熱圖案1005。
圖32說明對圖31所示結構的進一步製程。所述兩個圖之間的製程相似於以上參照圖3至圖6所說明及所闡述的製程，圖6是與圖32相似的製程階段，本文中不再贅述圖32。在圖32中，移除載體基底100及離型層102並將其放置於膠帶190上。在移除離型層102之後，背側重佈線結構的背側介電層1001被暴露出。
在圖33中，在介電層1001中形成一組開口1012以暴露出金屬化圖案1004的多個部分及熱圖案1005的多個部分。開口1012可藉由雷射鑽孔製程（laser drill process）、蝕刻製程等或其組合來形成。開口1012暴露出與通孔112耦合的金屬化圖案1004及與熱膏1010耦合的熱圖案1005。
在圖34中，在開口1012中的暴露出的金屬化圖案1004及熱圖案1005中的每一者上形成含焊料的層1014，含焊料的層1014可為焊料層（有時稱為前體焊料層（pre-solder layer））、焊料膏等。在一些實施例中，含焊料的層1014可完全填充或過度填充（overfill）開口1012，而在其他實施例中，含焊料的層1014則可僅局部地填充開口1012。在沈積含焊料的層1014之後，可在將導電連接件314及316接合至含焊料的層1014及封裝結構1050（參照例如圖35）之前執行回焊製程。在一些實施例中，可省略含焊料的層1014。
圖35說明對圖34所示結構的進一步製程。所述兩個圖之間的製程相似於以上參照圖9至圖12所說明及所闡述的製程，圖12是與圖35相似的製程階段，本文中不再贅述圖35。
在將導電連接件314及316接合至含焊料的層1014及封裝結構1050的回焊製程之後，含焊料的層1014與連接件314及316可相互混合且不再如圖35中所示的單獨結構那樣明顯可見。
導電連接件314用於將封裝結構1050電性連接至封裝結構300。與熱膏1010相似，導電連接件316不是用於電性連接積體電路晶粒114或封裝結構中的裝置或金屬化圖案，而是用於發散來自積體電路晶粒114及/或封裝結構的熱能。因此，可將導電連接件316稱作熱連接件316。相較於不包括熱膏及熱連接件的封裝結構，使用熱膏1010、熱圖案1005、及熱連接件316使得所述封裝結構的熱阻（℃/瓦）可提高達約8%。
本發明的其他所揭露實施例的封裝體中可包括此實施例的層1010及金屬化圖案1004。
藉由在半導體晶粒的背側上形成熱元件，封裝結構的熱效能可提高。熱元件用於發散來自封裝結構的熱能。在一些實施例中，熱元件不連接至散熱路徑，而在其他實施例中，熱元件連接至半導體晶粒（參照例如圖14）中的散熱路徑。舉例而言，熱元件可連接至與半導體晶粒中的一個或多個電晶體熱耦合/熱連接的通孔，以發散由所述電晶體產生的熱能。相較於不在半導體晶粒的背側上形成熱元件的封裝結構，本發明的實施例使得所述封裝結構的熱阻（℃/瓦）可提高達約8%。
在實施例中，一種封裝體包括第一封裝結構，所述第一封裝結構包括：第一積體電路晶粒，具有主動側及背側，所述主動側包括晶粒連接件；第一通孔，相鄰第一積體電路晶粒；包封體，在側向上包封第一積體電路晶粒及第一通孔；第一重佈線結構，位於第一積體電路晶粒的晶粒連接件及第一通孔上且電性連接至所述第一積體電路晶粒的晶粒連接件及所述第一通孔；以及熱元件，位於第一積體電路晶粒的背側上。所述封裝體更包括第二封裝結構，所述第二封裝結構藉由第一組導電連接件接合至第一通孔及熱元件。在實施例中，熱元件與第一積體電路晶粒內的積體電路電性隔離。在實施例中，第一積體電路晶粒的背側自包封體的表面凹陷，熱元件位於所述凹陷內。在實施例中，熱元件具有與第一積體電路晶粒的背側垂直的側壁。在實施例中，熱元件具有自所述熱元件的頂表面至所述熱元件的底表面漸縮的側壁。在實施例中，熱元件具有自所述熱元件的頂表面至所述熱元件的底表面加寬的側壁。在實施例中，熱元件包括導電膏及金屬化圖案。在實施例中，所述封裝體更包括：底部填充劑，環繞第一組導電連接件，所述底部填充劑位於第一封裝結構與第二封裝結構之間。在實施例中，底部填充劑接觸熱元件。在實施例中，第一封裝結構與第二封裝結構之間的中心部分不具有導電連接件。在實施例中，所述封裝體更包括：通孔，位於第一積體電路晶粒的背側內，熱元件熱連接至所述通孔。在實施例中，第一封裝結構更包括：第二重佈線結構，位於所述第一通孔上且電性連接至第一通孔，所述第二重佈線結構位於第一積體電路晶粒與第二封裝結構之間。在實施例中，所述封裝體更包括：虛擬晶粒，位於第一積體電路晶粒的背側上，熱元件位於所述虛擬晶粒上。
在實施例中，一種方法包括形成第一封裝體，所述形成第一封裝體包括：在載體基底之上形成電性連接件；使用黏合劑層將第一晶粒貼合至載體基底，電性連接件自第一晶粒的背側延伸至所述第一晶粒的主動側，所述主動側與所述背側相對，所述電性連接件相鄰所述第一晶粒；使用模塑化合物包封第一晶粒及電性連接件；形成第一重佈線結構，所述第一重佈線結構上覆於第一晶粒的主動側、模塑化合物、及電性連接件上；移除載體基底，以暴露出電性連接件的第一端及黏合劑層；移除黏合劑層，以暴露出第一晶粒的背側；以及在第一晶粒的暴露出的背側上形成熱元件。所述方法更包括：在熱元件及電性連接件的第一端之上形成第一組導電連接件；以及使用第一組導電連接件將第二封裝體接合至第一封裝體，所述第二封裝體緊鄰第一晶粒的背側。在實施例中，所述方法更包括：在第一晶粒的背側上的熱元件之上以及在電性連接件的第一端之上形成第二重佈線結構，所述第二重佈線結構電性連接至所述電性連接件，第二封裝體接合至所述第二重佈線結構。在實施例中，熱元件熱連接至第二重佈線結構。在實施例中，所述方法更包括：將模塑化合物及第一晶粒的背側平坦化至具有水平表面，熱元件位於所述第一晶粒的背側的平坦化表面及所述模塑化合物的平坦化表面上。在實施例中，在第一晶粒的暴露出的背側上形成熱元件包括：在所述第一晶粒的暴露出的所述背側上形成晶種層；在晶種層上形成介電層；藉由圖案化形成穿過介電層的孔，以暴露出晶種層的多個部分；以及在孔中形成導電材料，所述導電材料形成熱元件。
在實施例中，一種方法包括形成第一封裝體，所述形成第一封裝體包括：在載體基底之上形成電性連接件；使用黏合劑層將第一晶粒貼合至載體基底，所述第一晶粒包括在所述第一晶粒的背側上位於所述黏合劑層內的導電接墊，電性連接件自所述第一晶粒的背側延伸至所述第一晶粒的主動側，所述主動側與所述背側相對，所述電性連接件相鄰所述第一晶粒；使用模塑化合物包封第一晶粒及電性連接件；形成重佈線結構，所述重佈線結構上覆於第一晶粒的主動側、模塑化合物、及電性連接件上；移除載體基底，以暴露出電性連接件的第一端及黏合劑層；移除黏合劑層，以暴露出導電接墊及第一晶粒的背側。所述方法更包括：在導電接墊及電性連接件的第一端上形成第一組導電連接件；以及使用第一組導電連接件將第二封裝體接合至第一封裝體，所述第二封裝體緊鄰第一晶粒的背側。在實施例中，所述方法更包括：在第一晶粒的背側上的導電接墊之上以及在電性連接件的第一端之上形成第二重佈線結構，所述第二重佈線結構電性連接至所述電性連接件，第二封裝體接合至所述第二重佈線結構。
在實施例中，所述方法包括形成第一封裝體，所述形成第一封裝體包括：在載體基底之上形成第一金屬化圖案及第二金屬化圖案；在第一金屬化圖案及第二金屬化圖案的第一表面之上形成介電層並將所述介電層圖案化，所述圖案化介電層暴露出第一金屬化圖案及第二金屬化圖案二者的第一表面的多個部分；在介電層之上形成電性連接件並將所述電性連接件電性連接至第一金屬化圖案；使用第一黏合劑層將第一晶粒貼合至介電層，所述第一黏合劑層接觸第二金屬化圖案的暴露出的第一表面；使用模塑化合物包封第一晶粒及電性連接件；形成上覆於第一晶粒的主動層、模塑化合物以及電性連接件上的第一重佈線結構；移除載體基底，其中在所述移除之後，第一金屬化圖案及第二金屬化圖案的第二表面被暴露出；在第一金屬化圖案及第二金屬化圖案的第二表面之上形成第一組導電連接件，所述第一組導電連接件中的至少一個導電連接件電性耦合至所述電性連接件；以及使用第一組導電連接件將第二封裝體接合至第一封裝體，所述第二封裝體緊鄰第一晶粒的背側，所述背側與主動側相對。在實施例中，第一黏合劑層為導電膏。在實施例中，所述方法更包括：在第一重佈線結構上形成第二組導電連接件；以及使用第二組導電連接件將第一封裝體接合至基底。在實施例中，所述方法更包括在第一晶粒的背側中形成通孔，所述通孔接觸第一黏合劑層。
在實施例中，一種封裝體包括第一封裝結構，所述第一封裝結構包括：虛擬晶粒，具有前側及背側；第一積體電路晶粒，具有前側及背側，所述前側包括晶粒連接件；第一貼合層，位於第一積體電路晶粒的背側與虛擬晶粒的前側之間且接觸所述第一積體電路晶粒的背側及所述虛擬晶粒的前側；第一電性連接件，相鄰第一積體電路晶粒、第一貼合層以及虛擬晶粒；包封體，在側向上包封第一積體電路晶粒、虛擬晶粒、第一貼合層以及第一電性連接件；第一重佈線結構，位於第一積體電路晶粒的晶粒連接件及第一電性連接件上且電性連接至所述第一積體電路晶粒的晶粒連接件及所述第一電性連接件；以及熱元件，位於虛擬晶粒的背側上。所述封裝體更包括第二封裝結構，所述第二封裝結構藉由第一組導電連接件接合至第一電性連接件及熱元件。在實施例中，第一貼合層為包括金屬的導電層。在實施例中，其中虛擬晶粒是由金屬製成。在實施例中，虛擬晶粒的背側相對於包封體的表面凹陷，所述熱元件位於凹陷內。
在實施例中，一種結構包括第一封裝結構，所述第一封裝結構包括：第一重佈線結構，包括金屬化圖案及介電層；第一晶粒，位於第一重佈線結構之上且電性連接至所述第一重佈線結構，所述第一晶粒的主動側包括面對所述第一重佈線結構的晶粒連接件；第一通孔，相鄰第一晶粒，所述第一通孔電性連接至第一重佈線結構；包封體，在側向上包封第一晶粒及通孔；貼合層，位於第一晶粒的背側之上，所述第一晶粒的背側與主動側相對，所述貼合層接觸包封體；以及第二重佈線結構，位於貼合層及第一通孔之上，所述第二重佈線結構包括金屬化圖案及介電層，所述第二重佈線結構電性連接至第一通孔。所述結構更包括第二封裝結構，所述第二封裝結構藉由第一組導電連接件接合至第二重佈線結構的金屬化圖案。在實施例中，貼合層為導電膏。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。
100‧‧‧載體基底
102‧‧‧離型層
112‧‧‧電性連接件
114‧‧‧積體電路晶粒
116、804‧‧‧黏合劑
118‧‧‧基底
120‧‧‧內連結構
122‧‧‧接墊
124‧‧‧保護膜
126‧‧‧晶粒連接件
128‧‧‧介電材料
130‧‧‧包封體
132、140、148、156、904、908、912、1001、1002‧‧‧介電層
138、146、154、1004、1005‧‧‧金屬化圖案
160‧‧‧重佈線結構
162‧‧‧接墊
166‧‧‧導電連接件
180、714‧‧‧凹陷
182‧‧‧接墊
182A‧‧‧側壁
190‧‧‧膠帶
200‧‧‧封裝體
300‧‧‧封裝體
302‧‧‧基底
303、304‧‧‧接合墊
305、712‧‧‧熱接墊
306‧‧‧通孔
308‧‧‧堆疊晶粒
308A、308B‧‧‧晶粒
310‧‧‧導線接合件
312‧‧‧模塑材料
314‧‧‧導電連接件
316‧‧‧導電連接件
320‧‧‧底部填充劑
330‧‧‧區域
400‧‧‧基底
402‧‧‧接合墊
500‧‧‧半導體封裝體
600‧‧‧第一封裝區
602‧‧‧第二封裝區
702‧‧‧通孔
802‧‧‧虛擬晶粒
806‧‧‧黏合劑
808‧‧‧熱接墊
900‧‧‧封裝體
902‧‧‧晶種層
906、910、914‧‧‧金屬化圖案
920、930‧‧‧背側重佈線結構
1006、1012‧‧‧開口
1010‧‧‧層
1014‧‧‧含焊料的層
1050‧‧‧封裝結構
D1、D2、D3‧‧‧深度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖12說明根據一些實施例的在形成封裝結構的製程期間的各中間步驟的剖視圖。
圖13A及圖13B說明根據一些實施例的另一封裝結構的剖視圖及平面圖。
圖14說明根據一些實施例的另一封裝結構的剖視圖。
圖15至圖18說明根據一些實施例的另一封裝結構的製程期間的各中間步驟的剖視圖。
圖19至圖21說明根據一些實施例的另一封裝結構的製程期間的各中間步驟的剖視圖。
圖22至圖25說明根據一些實施例的另一封裝結構的製程期間的各中間步驟的剖視圖。
圖26至圖29說明根據一些實施例的另一封裝結構的製程期間的各中間步驟的剖視圖。
圖30至圖35說明根據一些實施例的另一封裝結構的製程期間的各中間步驟的剖視圖。

Claims (20)

  1. 一種封裝體，包括： 第一封裝結構，包括： 第一積體電路晶粒，具有主動側及背側，所述主動側包括晶粒連接件； 第一通孔，相鄰所述第一積體電路晶粒； 包封體，在側向上包封所述第一積體電路晶粒及所述第一通孔； 第一重佈線結構，位於所述第一積體電路晶粒的所述晶粒連接件及所述第一通孔上，且電性連接至所述第一積體電路晶粒的所述晶粒連接件及所述第一通孔；以及 熱元件，位於所述第一積體電路晶粒的所述背側上；以及 第二封裝結構，藉由第一組導電連接件接合至所述第一通孔及所述熱元件。
  2. 如申請專利範圍第1項所述的封裝體，其中所述熱元件與所述第一積體電路晶粒內的積體電路電性隔離。
  3. 如申請專利範圍第1項所述的封裝體，其中所述第一積體電路晶粒的所述背側自所述包封體的表面凹陷，所述熱元件位於所述凹陷內。
  4. 如申請專利範圍第1項所述的封裝體，其中所述熱元件具有側壁，其與所述第一積體電路晶粒的所述背側垂直。
  5. 如申請專利範圍第1項所述的封裝體，其中所述熱元件具有側壁，其自所述熱元件的頂表面至所述熱元件的底表面漸縮。
  6. 如申請專利範圍第1項所述的封裝體，其中所述熱元件具有側壁，其自所述熱元件的頂表面至所述熱元件的底表面加寬。
  7. 如申請專利範圍第1項所述的封裝體，其中所述熱元件包括導電膏及金屬化圖案。
  8. 如申請專利範圍第1項所述的封裝體，更包括： 底部填充劑，環繞所述第一組導電連接件，所述底部填充劑位於所述第一封裝結構與所述第二封裝結構之間。
  9. 如申請專利範圍第8項所述的封裝體，其中所述底部填充劑接觸所述熱元件。
  10. 如申請專利範圍第1項所述的封裝體，其中所述第一封裝結構與所述第二封裝結構之間的中心部分不具有導電連接件。
  11. 如申請專利範圍第1項所述的封裝體，更包括： 通孔，位於所述第一積體電路晶粒的所述背側內，所述熱元件熱連接至所述通孔。
  12. 如申請專利範圍第1項所述的封裝體，其中所述第一封裝結構更包括： 第二重佈線結構，位於所述第一通孔上，且電性連接至所述第一通孔，所述第二重佈線結構位於所述第一積體電路晶粒與所述第二封裝結構之間。
  13. 如申請專利範圍第1項所述的封裝體，更包括： 虛擬晶粒，位於所述第一積體電路晶粒的所述背側上，所述熱元件位於所述虛擬晶粒上。
  14. 一種方法，包括： 形成第一封裝體，包括： 在載體基底之上形成電性連接件； 使用黏合劑層將第一晶粒貼合至所述載體基底，所述電性連接件自所述第一晶粒的背側延伸至所述第一晶粒的主動側，所述主動側與所述背側相對，所述電性連接件相鄰所述第一晶粒； 以模塑化合物包封所述第一晶粒及所述電性連接件； 形成第一重佈線結構，所述第一重佈線結構上覆於所述第一晶粒的所述主動側、所述模塑化合物以及所述電性連接件上； 移除所述載體基底，以暴露出所述電性連接件的第一端及所述黏合劑層； 移除所述黏合劑層，以暴露出所述第一晶粒的所述背側；以及 在所述第一晶粒的暴露出的所述背側上形成熱元件； 在所述熱元件及所述電性連接件的所述第一端之上形成第一組導電連接件；以及 使用所述第一組導電連接件將第二封裝體接合至所述第一封裝體，所述第二封裝體緊鄰所述第一晶粒的所述背側。
  15. 如申請專利範圍第14項所述的方法，更包括： 在所述第一晶粒的所述背側上的所述熱元件之上以及在所述電性連接件的所述第一端之上形成第二重佈線結構，所述第二重佈線結構電性連接至所述電性連接件，所述第二封裝體接合至所述第二重佈線結構。
  16. 如申請專利範圍第15項所述的方法，其中所述熱元件熱連接至所述第二重佈線結構。
  17. 如申請專利範圍第14項所述的方法，更包括： 將所述模塑化合物及所述第一晶粒的所述背側平坦化至具有水平表面，所述熱元件位於所述第一晶粒的所述背側的平坦化表面及所述模塑化合物的平坦化表面上。
  18. 如申請專利範圍第14項所述的方法，其中在所述第一晶粒的暴露出的所述背側上形成熱元件包括： 在所述第一晶粒的暴露出的所述背側上形成晶種層； 在所述晶種層上形成介電層； 藉由圖案化以形成穿過所述介電層的孔，以暴露出所述晶種層的多個部分；以及 在所述孔中形成導電材料，所述導電材料形成所述熱元件。
  19. 一種方法，包括： 形成第一封裝體，包括： 在載體基底之上形成電性連接件； 使用黏合劑層將第一晶粒貼合至所述載體基底，所述第一晶粒包括在所述第一晶粒的背側上的所述黏合劑層內的導電接墊，所述電性連接件自所述第一晶粒的所述背側延伸至所述第一晶粒的主動側，所述主動側與所述背側相對，所述電性連接件相鄰所述第一晶粒； 以模塑化合物包封所述第一晶粒及所述電性連接件； 形成重佈線結構，所述重佈線結構上覆於所述第一晶粒的所述主動側、所述模塑化合物以及所述電性連接件上； 移除所述載體基底，以暴露出所述電性連接件的第一端及所述黏合劑層； 移除所述黏合劑層，以暴露出所述導電接墊及所述第一晶粒的所述背側；以及 在所述導電接墊及所述電性連接件的所述第一端上形成第一組導電連接件；以及 使用所述第一組導電連接件將第二封裝體接合至所述第一封裝體，所述第二封裝體緊鄰所述第一晶粒的所述背側。
  20. 如申請專利範圍第19項所述的方法，更包括： 在所述第一晶粒的所述背側上的所述導電接墊之上以及在所述電性連接件的所述第一端之上形成第二重佈線結構，所述第二重佈線結構電性連接至所述電性連接件，所述第二封裝體接合至所述第二重佈線結構。
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