TWI689998B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TWI689998B
TWI689998B TW107119359A TW107119359A TWI689998B TW I689998 B TWI689998 B TW I689998B TW 107119359 A TW107119359 A TW 107119359A TW 107119359 A TW107119359 A TW 107119359A TW I689998 B TWI689998 B TW I689998B
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Taiwan
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dielectric layer
conductive
bump
metal
under
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TW107119359A
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TW201923914A (zh
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陳威宇
蘇安治
葉德強
黃立賢
葉名世
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台灣積體電路製造股份有限公司
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Abstract

在一個實施例中，半導體封裝包括：積體電路晶粒；在體積電路晶粒上的第一介電層；延伸穿過第一介電層而電連接積體電路晶粒的第一金屬化圖案；在第一金屬化圖案上的第二介電層；延伸穿過第二介電層的凸塊下金屬；在第二介電層上和凸塊下金屬的部分上的第三介電層；密封第三介電層與凸塊下金屬的界面的導電環；以及延伸穿過導電環的中心的導電連接件，導電連接件電連接到凸塊下金屬。

Description

半導體封裝及其製造方法
本發明實施例是有關於一種半導體封裝及其製造方法。
由於各種電子元件(如電晶體、二極體、電阻器、電容器等)積集度的不斷提高，半導體產業經歷了快速發展。主要來說，積集度的改進是由最小特徵尺寸的迭代縮減導致的，這允許更多的元件被整合到給定的區域中。隨著對電子元件進行微縮的需求不斷增長，對半導體晶粒的更小且更具創造性的封裝技術的需求也出現了。這種封裝系統的一個實例是層疊封裝(package-on-package，POP)技術。在疊層封裝元件中，頂部半導體封裝堆疊在底部半導體封裝頂部上，以提供高水平的積集度和元件密度。層疊封裝技術通常可以在印刷電路板(PCB)上製造高效能且小面積的半導體元件。
在一個實施例中，半導體封裝包括：積體電路晶粒；所述 積體電路晶粒上的第一介電層；穿過所述第一介電層而延伸以電連接到所述積體電路晶粒的第一金屬化圖案；所述第一金屬化圖案上的第二介電層；延伸穿過所述第二介電層的凸塊下金屬；在所述第二介電層上和所述凸塊下金屬的部分上的第三介電層；密封所述第三介電層和所述凸塊下金屬的界面的導電環；以及延伸穿過所述導電環的中心的導電連接件，所述導電連接件電連接到所述凸塊下金屬。
在一些實施例中，半導體封裝包括：積體電路晶粒；鄰近於所述積體電路晶粒的穿孔；所述穿孔和所述積體電路晶粒周圍的包封體；以及重佈線結構，包括：所述第一介電層上的第一金屬化圖案，所述第一介電層設置於所述包封體上，所述第一金屬化圖案延伸穿過所述第一介電層以電連接到所述穿孔；所述第二介電層上的凸塊下金屬，所述第二介電層設置於所述第一介電層上，所述凸塊下金屬延伸穿過所述第二介電層以電連接到所述第一金屬化圖案；以及在第三介電層上的導電環，所述第三介電層設置於所述第二介電層上，所述導電環密封所述第三介電層和所述凸塊下金屬的界面。
在一些實施例中，一種半導體封裝的製造方法包括：在積體電路晶粒上沉積設置第一介電層；形成沿著所述第一介電層延伸的第一金屬化圖案；在所述第一金屬化圖案和所述第一介電層上沉積第二介電層；形成沿所述第二介電層延伸的凸塊下金屬；在所述凸塊下金屬和所述第二介電層上沉積第三介電層；在所述第 三介電層中形成暴露出所述凸塊下金屬的開口；在所述第三介電層和所述凸塊下金屬的界面分配導電膏；以及固化所述導電膏以形成密封所述第三介電層和所述凸塊下金屬的所述界面的導電環。
100:承載基底
102:離型層
104、108、134、140、146、152、158:介電層
106:金屬化圖案
110:背側重佈線結構
112、306:穿孔
114:積體電路晶粒
116:黏著劑
118:半導體基底
120:內連線結構
122:接墊
124:保護膜
126:晶粒連接件
128:介電材料
130:包封體
132:前側重佈線結構
136、142、148、154、160、178:開口
138、144、150:金屬化圖案
156:凸塊下金屬
162:導電膏
164:導電環
166:助焊劑
168:導電連接件
170、172:金屬間化合物
174:界面
176:膠帶
200、302:第一封裝
202:基底
300:第二封裝
303、304、402:接合接墊
308:堆疊晶粒
308A、308B:晶粒
310:打線
312:模製材料
314:導電連接件
318:焊料抗蝕劑
400:封裝基底
500:封裝結構
600:第一封裝區
602:第二封裝區
650:區
R1、R2、R5:半徑
R3:外徑
R4:內徑
W1:寬度
接合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖19示出了根據一些實施例的在用於形成元件封裝的製程期間的中間步驟的剖視圖。
圖20至圖21示出了根據一些實施例的在用於形成封裝結構的製程期間的中間步驟的剖視圖。
以下揭露內容提供用於實作所提供主題的不同特徵的諸多不同的實施例或實例。以下闡述組件、值、操作、材料、排列等的具體實例以簡化本發明。當然，該些僅為實例且不旨在進行限制。預期存在其他組件、值、操作、材料、排列等。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使 得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於...之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向)且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
根據一些實施例，在重佈線結構的凸塊下金屬(under bump metallurgy，UBM)上形成介電層。在介電層中形成開口，且開口暴露出UBM。在介電層和UBM的界面形成導電膏，然後將導電膏固化。在UBM上形成助焊劑，在助焊劑上形成導電連接件(例如焊料)。在導電連接件的回流(reflow)期間，導電膏防止助焊劑進入介電層和UBM的界面。因此介電層和UBM之間的黏合力可以得到改善，從而提高了重佈線結構的機械可靠度。
圖1至圖19示出了根據一些實施例的在用於形成第一封裝200的製程期間的中間步驟的剖視圖。圖1至圖19示出了第一封裝區600和第二封裝區602，第一封裝200形成在每個封裝區中。第一封裝200也可以稱為積體扇出(InFO)封裝。
在圖1中，提供承載基底100，並且在承載基底100上形成離型層102。承載基底100可以是玻璃承載基底、陶瓷承載基底等。承載基底100可以是晶圓，以使得承載基底100上可以同時形成多個封裝。離型層102可以由聚合物系材料形成，該聚合物系材料可與承載基底100一起自隨後步驟中形成的上覆結構移除。在一些實施例中，離型層102是一種環氧樹脂系的熱離型材料，其在加熱時失去黏著性。熱離型材料例如是光熱轉化(LTHC)離型塗層。在其他實施例中，離型層102可以是紫外光(UV)膠，當暴露於UV光線時失去黏著性。離型層102可為液體而被分配並固化，可以是層壓到承載基底100上的層壓膜，或者可為類似者。離型層102的頂面可以被平整化，並且可以具有高度的共面性(coplanarity)。
在圖2中，形成介電層104、金屬化圖案106(有時稱為重佈線層或重分佈線)和介電層108。介電層104形成在離型層102上。介電層104的底面可以與離型層102的頂面接觸。在一些實施例中，介電層104由聚苯並噁唑(PBO)、聚乙醯胺、苯並環丁烯(BCB)等聚合物形成。在其他實施例中，介電層104由：諸如氮化矽的氮化物；諸如氧化矽、磷矽酸玻璃(PSG)，硼矽玻璃(BSG)、硼摻雜磷矽酸玻璃(BPSG)等氧化物；或類似者而形成。介電層104可以由任何可接受的沉積製程形成。上述的沉積製程例如是旋轉塗佈、化學氣相沉積(CVD)、層壓等，或其組合。
在介電層104上形成金屬化圖案106。作為形成金屬化圖 案106的例子，在介電層104上形成晶種層(未示出)。在一些實施例中，晶種層是金屬層，其可以是單層或由不同材料形成的多個子層組成的複合層。在一些實施例中，晶種層包含鈦層和在鈦層上的銅層。晶種層可以使用例如物理氣相沉積(physical vapor deposition，PVD)法等形成。然後在晶種層上形成光阻並將其圖案化。光阻可以通過旋轉塗佈等方法形成，並且可以暴露於光線以進行圖案化。光阻圖案對應於金屬化圖案106。經圖案化而形成的開口穿過光阻且曝露出晶種層。在光阻的開口處和晶種層的暴露部分上形成導體材料。導電材料可以通過例如是電鍍或無電鍍等鍍覆製程形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁等。然後，去除光阻以及上方未形成導電材料的部分的晶種層。光阻可以通過可接受的灰化或剝離製程來去除，例如使用氧電漿等。一旦去除光阻，例如通過使用可接受的蝕刻製程(諸如通過濕法或乾式蝕刻)去除晶種層的暴露部分。晶種層的剩餘部分和導電材料構成金屬化圖案106。
在金屬化圖案106和介電層104上形成介電層108。在一些實施例中，介電層108由聚合物形成，該聚合物可為諸如PBO、聚乙醯胺、BCB等的光敏材料，且可藉由使用微影罩幕而圖案化此光敏材料。在其他實施例中，介電層108由：諸如氮化矽的氮化物；如氧化矽、PSG、BSG、BPSG的氧化物；或類似者形成。介電層108可以通過旋轉塗佈、疊層、CVD等或其組合的方法來形成介電層108。隨後，圖案化介電層108以形成開口，以暴露部分 金屬化圖案106。圖案化可以通過可接受的製程來實施，例如當介電層108是光敏材料時通過將介電層108暴露於光線，或通過使用例如非等向性蝕刻的蝕刻製程來對介電層108進行圖案化。
介電層104、介電層108以及金屬化圖案106可以被稱為背側重佈線結構110。在所示實施例中，背側重佈線結構110包括兩層介電層(介電層104和介電層108)以及一層金屬化圖案106。在其他實施例中，背側重佈線結構110可以包括任何數量的介電層、金屬化圖案和導通孔。通過重複進行形成金屬化圖案106和介電層108的製程，可以在背側重佈線結構110中形成一個或多個額外的金屬化圖案和介電層。導通孔(未示出)可通過在形成金屬化圖案的期間在下伏的介電層的開口中形成金屬化圖案的晶種層和導電材料而形成。導通孔可因此可以與各種金屬化圖案內連並電耦接。
在圖3中，形成穿孔112。作為形成穿孔112的例子，在背側重佈線結構110上形成晶種層，例如在如圖所示的介電層108和金屬化圖案106的暴露部分上形成晶種層。在一些實施例中，晶種層是金屬層，其可以是單層或由不同材料形成的多個子層組成的複合層。在一些實施例中，晶種層包含鈦層和在鈦層上的銅層。晶種層可以使用例如PVD等方法形成。在晶種層上形成光阻，並圖案化光阻。光阻可以通過旋轉塗佈等方法形成，並且可以使光阻暴露於光線而進行圖案化。光阻圖案對應於穿孔(through vias)。經圖案化而形成的開口穿過光阻，以暴露出晶種層。在光阻的開口 處和晶種層的暴露部分上形成導體材料。導電材料可以通過如電鍍或無電鍍等鍍覆製程形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁等。去除光阻以及上方未形成導電材料的部分的晶種層。光阻可以通過可接受的灰化或剝離製程(例如使用氧電漿等)來去除。一旦去除光阻，例如通過使用可接受的蝕刻製程(諸如通過濕法或乾式蝕刻)去除晶種層的暴露部分。晶種層的剩餘部分和導電材料形成穿孔112。
在圖4中，通過黏著劑116而將積體電路晶粒114黏附到介電層108上。儘管在第一封裝區600和第二封裝區602中的每一者示出了兩個積體電路晶粒114，但應該理解的是，可以在每個封裝區中附著更多或更少的積體電路晶粒114。例如，每個區域僅黏附有一個積體電路晶粒114。積體電路晶粒114可以是邏輯晶粒(例如中央處理單元與微控制器等)、記憶體晶粒(例如動態隨機存取記憶體(DRAM)晶粒以及靜態隨機存取記憶體(SRAM)晶粒等)、功率管理晶粒(例如電源管理積體電路(PMIC)晶粒)、射頻(射頻)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、訊號處理晶粒(例如數位訊號處理(DSP)晶粒)、前端晶粒(例如類比前端(AFE)晶粒)等或其組合。另外，在一些實施例中，多個積體電路晶粒114可以是不同的尺寸(例如，不同的高度及/或表面積)，並且在其他實施例中，多個積體電路晶粒114可以是相同的尺寸(例如，相同的高度及/或表面積)。
在貼附於介電層108之前，可依照適用的製造製程進行 處理，以在積體電路晶粒114中形成積體電路。例如，積體電路晶粒114各自包括半導體基底118，例如是經摻雜或未經摻雜的矽或絕緣體上覆半導體(SOI)基底的主動層。半導體基底可以包括其他半導體材料，例如：鍺；包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦的化合物半導體；包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP的合金半導體；或其組合。在一些實施例中，也可使用如多層基底或梯度基底的其他基底。在半導體基底118中及/或半導體基底118上可以形成元件(例如電晶體、二極體、電容器、電阻器等)。並且可以通過例如在半導體基底118上的一個或多個介電層中藉由金屬化圖案所形成的內連線結構120而對元件進行互連，從而形成積體電路。
積體電路晶粒114還包括接墊122，例如鋁接墊。可在接墊122上形成外部連接。接墊122位於可被稱為積體電路晶粒114的相應主動側的區域上。保護膜124位於積體電路晶粒114上並且位於部分的接墊122上。開口穿過保護膜124到接墊122。晶粒連接件126，諸如導電支柱(例如包括銅之類的金屬)位於穿過保護膜124的開口中，並且機械和電性地耦接到相應的接墊122。晶粒連接件126可以通過例如電鍍等方法形成。晶粒連接件126電耦接於積體電路晶粒114的相應積體電路。
介電材料128位於積體電路晶粒114的主動側上，如位於保護膜124和晶粒連接件126上。介電材料128側向地包封晶粒連接件126，且介電材料128側向地與相應的積體電路晶粒114 相接。介電材料128可以是如PBO、聚乙醯胺、BCB等的聚合物；諸如氮化矽等的氮化物；如氧化矽、PSG、BSG、BPSG等的氧化物；類似者或其組合。介電材料128可以通過例如是旋轉塗佈、疊層、CVD等方法形成。
黏著劑116位於積體電路晶粒114的背面，並將積體電路晶粒114黏附至背側重佈線結構110(例如是介電層108)。黏著劑116可以是任何適合的黏著劑、環氧樹脂、晶粒貼合膜(die attach film，DAF)等。黏著劑116可以施加到積體電路晶粒114的背面，例如施加到相應的半導體晶圓的背面，或者可以施加在承載基底100的表面上。積體電路晶粒114可以例如通過鋸切或切割進行單體化，並且通過使用例如拾放工具將積體電路晶粒114藉由黏著劑116黏附到介電層108上。
在圖5中，將包封體130形成在各種部件上。包封體130可以是模製化合物、環氧樹脂等，且可以通過壓縮成型(compression molding)、轉注成型(transfer molding)等來施加。包封體130可以形成在承載基底100上，使得積體電路晶粒114的穿孔112及/或晶粒連接件126埋入於或覆蓋於包封體130中。隨後，固化包封體130。
在圖6中，在包封體130上執行平坦化製程，以暴露出穿孔112和晶粒連接件126。平坦化製程也可研磨介電材料128。在平坦化製程之後，穿孔112、晶粒連接件126、介電材料128和包封體130的頂面共面。平坦化製程可以是例如化學機械研磨 (CMP)、研磨(grinding)製程等。在一些實施例中，例如，如果穿孔112和晶粒連接件126已經暴露出來，則可以省略平坦化製程。
在圖7至15中，形成前側重佈線結構132。如下所述，前側重佈線結構132包括介電層134、介電層140、介電層146、介電層152和介電層158，並且還包括金屬化圖案138、金屬化圖案144和金屬化圖案150。金屬化圖案也可稱為重佈線層或重分佈線，且包括導通孔和導線(未單獨標註)。
在圖7中，在包封體130、穿孔112和晶粒連接件126上沉積介電層134。在一些實施例中，介電層134由聚合物形成，該聚合物可以是諸如PBO、聚乙醯胺、BCB等的光敏材料，且此光敏材料可藉由使用微影罩幕而圖案化。在其他實施例中，介電層134由：諸如氮化矽的氮化物；如氧化矽、PSG、BSG、BPSG的氧化物；或類似者形成。介電層134可以通過旋轉塗佈、疊層、CVD等或其組合來形成。
隨後，圖案化介電層134。圖案化介電層134所形成的開口136暴露出穿孔112和部分的晶粒連接件126。圖案化可以通過可接受的製程來實施，例如當介電層134是光敏材料時，通過將介電層134暴露於光線，或通過使用例如非等向性蝕刻的蝕刻製程來對介電層108進行圖案化。如果介電層134是光敏材料，則介電層134可以在曝光之後被顯影。
在圖8中，在介電層134上形成具有通孔的金屬化圖案 138。作為形成金屬化圖案138的示例，在介電層134上方和穿過介電層134的開口136中形成晶種層(未示出)。在一些實施例中，晶種層是金屬層，其可以是單層或由不同材料形成的多個子層組成的複合層。在一些實施例中，晶種層包含鈦層和在鈦層上的銅層。晶種層可以使用例如PVD等方法形成。隨後，在晶種層上形成光阻並將其圖案化。光阻可以通過旋轉塗佈等方法形成，並且可以暴露於光線以進行圖案化。光阻圖案對應於金屬化圖案138。圖案化光阻所形成的開口穿過光阻，以曝露出晶種層。在光阻的開口處和晶種層的暴露部分上形成導體材料。導電材料可以通過例如是電鍍或無電鍍等鍍覆製程來形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁等。接著，去除光阻以及上方未形成導電材料的部分的晶種層。光阻可以通過可接受的灰化或剝離製程來去除，例如使用氧電漿等。一旦去除光阻，例如通過使用可接受的蝕刻製程(諸如通過濕法或乾式蝕刻)去除晶種層的暴露部分。晶種層的剩餘部分和導電材料構成金屬化圖案138和通孔。通孔形成在開口136中，穿過介電層134而到達例如是穿孔112及/或晶粒連接件126。
在圖9中，在金屬化圖案138和介電層134上沉積介電層140。在一些實施例中，介電層140由聚合物形成，該聚合物可以是諸如PBO、聚乙醯胺、BCB等的光敏材料，且此光敏材料可藉由使用微影罩幕而圖案化。在其他實施例中，介電層140由：諸如氮化矽的氮化物；如氧化矽、PSG、BSG、BPSG的氧化物；或 類似者形成。介電層140可以通過旋轉塗佈、疊層、CVD等或其組合的方法來形成。
之後，圖案化介電層140。圖案化介電層140所形成的開口142暴露出部分金屬化圖案138。圖案化可以通過可接受的製程來實施，例如當介電層140是光敏材料時通過將介電層140暴露於光線，或通過使用例如非等向性蝕刻的蝕刻製程來對介電層140進行圖案化。如果介電層140是光敏材料，則介電層140可以在曝光之後被顯影。
在圖10中，在介電層140上形成具有通孔的金屬化圖案144。作為形成金屬化圖案144的示例，在介電層140上和穿過介電層140的開口142中形成晶種層(未示出)。在一些實施例中，晶種層是金屬層，其可以是單層或由不同材料形成的多個子層組成的複合層。在一些實施例中，晶種層包含鈦層和在鈦層上的銅層。晶種層可以使用例如PVD等方法形成。然後在晶種層上形成光阻並將其圖案化。光阻可以通過旋轉塗佈等方法形成，並且可以暴露於光線以進行圖案化。光阻圖案對應於金屬化圖案144。經圖案化而形成的開口穿過光阻且曝露出晶種層。在光阻的開口處和晶種層的暴露部分上形成導體材料。導電材料可以通過如電鍍或無電鍍等鍍覆製程形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁等。然後，去除光阻以及上方未形成導電材料的部分的晶種層。光阻可以通過可接受的灰化或剝離製程來去除，例如使用氧電漿等。一旦去除光阻，例如通過使用可接受的蝕刻製程(諸如通過濕 法或乾式蝕刻)去除晶種層的暴露部分。晶種層的剩餘部分和導電材料構成金屬化圖案144和通孔。通孔形成在開口142中，穿過介電層140而到達例如是部分的金屬化圖案138。
在圖11中，在金屬化圖案144和介電層140上沉積介電層146。在一些實施例中，介電層146由聚合物形成，該聚合物可以是諸如PBO、聚乙醯胺、BCB等的光敏材料，且此光敏材料可藉由使用微影罩幕而圖案化。在其他實施例中，介電層146由：諸如氮化矽的氮化物；如氧化矽、PSG、BSG、BPSG的氧化物；或類似者形成。介電層146可以通過旋轉塗佈、疊層、CVD等或其組合的方法來形成。
隨後，圖案化介電層146。圖案化介電層146所形成的開口148暴露出部分金屬化圖案144。圖案化可以通過可接受的製程來實施，例如當介電層146是光敏材料時通過將介電層146暴露於光線，或通過使用例如非等向性蝕刻的蝕刻製程來對介電層108進行圖案化。如果介電層146是光敏材料，則介電層146可以在曝光之後被顯影。
在圖12中，在介電層146上形成具有通孔的金屬化圖案150。作為形成金屬化圖案150的例子，在介電層146上和穿過介電層146的開口148中形成晶種層(未示出)。在一些實施例中，晶種層是金屬層，其可以是單層或由不同材料形成的多個子層組成的複合層。在一些實施例中，晶種層包含鈦層和在鈦層上的銅層。晶種層可以使用例如PVD等方法形成。之後，在晶種層上形 成光阻並將其圖案化。光阻可以通過旋轉塗佈等方法形成，並且可以暴露於光線以進行圖案化。光阻圖案對應於金屬化圖案150。圖案化光阻所形成的開口穿過光阻，以曝露出晶種層。在光阻的開口處和晶種層的暴露部分上形成導體材料。導電材料可以通過如電鍍或無電鍍等鍍覆製程來形成。導電材料可以包括金屬，如銅、鈦、鎢、鋁等。然後，去除光阻以及未形成導電材料於其上的晶種層的部分。光阻可以通過可接受的灰化或剝離製程來去除，例如使用氧電漿等。一旦去除光阻，例如通過使用可接受的蝕刻製程(諸如通過濕法或乾式蝕刻)去除晶種層的暴露部分。晶種層的剩餘部分和導電材料構成金屬化圖案150和通孔。通孔形成在開口中，穿過介電層146而到達例如部分的金屬化圖案144。
在圖13中，在金屬化圖案150和介電層146上沉積介電層152。在一些實施例中，介電層152由聚合物形成，該聚合物可以是諸如PBO、聚乙醯胺、BCB等的光敏材料，且此光敏材料可藉由使用微影罩幕而圖案化。在其他實施例中，介電層152由：諸如氮化矽的氮化物；如氧化矽、PSG、BSG、BPSG的氧化物；或類似者形成。介電層152可以通過旋轉塗佈、疊層、CVD等或其組合的方法來形成。
之後，圖案化介電層152。圖案化介電層152所形成的開口154暴露出部分金屬化圖案150。圖案化可以通過可接受的製程來實施，例如當介電層152是光敏材料時通過將介電層152暴露於光線，或通過使用例如非等向性蝕刻的蝕刻製程來對介電層152 進行圖案化。如果介電層152是光敏材料，則介電層152可以在曝光之後被顯影。開口154可以比開口136、開口142、開口148更寬。
在圖14中，在介電層152上形成UBM 156。在所示的實施例中，所形成的UBM 156穿過開口154且接觸於金屬化圖案150，其中開口154穿過介電層152。作為形成UBM156的例子，在介電層152上形成晶種層(未示出)。在一些實施例中，晶種層是金屬層，其可以是單層或由不同材料形成的多個子層組成的複合層。在一些實施例中，晶種層在包含鈦層和鈦層上的銅層。晶種層可以使用例如PVD等方法形成。然後在晶種層上形成光阻並將其圖案化。光阻可以通過旋轉塗佈等方法形成，並且可以暴露於光線以進行圖案化。光阻的圖案對應於UBM 156。經圖案化的光阻所形成的開口穿過光阻且曝露出晶種層。在光阻的開口處和晶種層的暴露部分上形成導體材料。導電材料可以通過如電鍍或無電鍍等鍍覆製程形成。導電材料可以包括金屬，例如銀、金、鋁、鈀、鎳、鎳合金、鎢合金、鉻、鉻合金等或其組合，並且可以是多層的導電特徵。在一個實施例中，UBM 156包括鎳層、金層和鈀層，並且通過化鎳鈀浸金(electroless nickel-electroless palladium-immersion gold，ENEPIG)製程來形成。一旦形成導電材料，去除光阻和其上未形成導電材料的晶種層的部分。光阻可以通過可接受的灰化或剝離製程來去除，例如使用氧電漿等。一旦去除光阻，例如通過使用可接受的蝕刻製程(諸如通過濕法或乾式蝕刻)去除 晶種層的暴露部分。晶種層的剩餘部分和導電材料形成UBM 156。在以不同方式形成UBM 156的實施例中，可以使用更多的光阻和圖案化步驟來形成UBM 156。
在圖15中，在UBM 156和介電層146上沉積介電層158。在一些實施例中，介電層158由聚合物形成，該聚合物可以是諸如PBO、聚乙醯胺、BCB等的光敏材料，且可藉由使用微影罩幕而圖案化此光敏材料。在其他實施例中，介電層158由：諸如氮化矽的氮化物；如氧化矽、PSG、BSG、BPSG的氧化物；或類似者形成。可以通過旋轉塗佈、疊層、CVD等或其組合的方法形成介電層158。
之後，圖案化介電層158。圖案化介電層158所形成的開口160暴露出部分UBM 156。圖案化可以通過可接受的製程來實施，例如當介電層158是光敏材料時通過將介電層158暴露於光線，或通過使用例如非等向性蝕刻的蝕刻製程來對介電層158進行圖案化。如果介電層158是光敏材料，則介電層158可以在曝光之後被顯影。
前側重佈線結構132係作為一示例。在前側重佈線結構132中可以形成更多或更少的介電層和金屬化圖案。如果形成更少的介電層和金屬化圖案，則可以省略上述的一些步驟和製程。如果形成更多的介電層和金屬化圖案，可以重複進行如上所述的步驟和製程。所屬領域中具有通常知識者將容易地理解哪個步驟和製程將被省略或重複。
在圖16中，在UBM 156上形成導電環164，導電環164圍繞開口160的周邊。此外，在UBM 156上以及開口160中形成導電連接件168。圖17A至圖17C示出在形成導電環164和導電連接件168的製程期間的區650的放大剖視圖。圖18示出形成導電環164之後的區650的放大俯視圖。以下接合圖16、17A、17B、17C和18而進行描述。
在圖17A中在UBM 156上，形成導電膏162。導電膏162可以例如是銅膏、焊膏、銀膏等，並且可以通過例如印刷製程等方法來分配(dispense)。在使用印刷製程的實施例中，使用模板(stencil)在UBM 156上印刷具有期望圖案的導電膏162的影像。導電膏162形成為圍繞開口160的周邊的環(annulus/ring)，且密封UBM 156和介電層158之間的界面。導電膏162沿著介電層158的頂面、界定開口160的介電層158的側面以及部分的UBM 156延伸。
在形成之後，導電膏162被固化以使其硬化，從而形成導電環164。導電環164可以通過在大約100℃至大約200℃的溫度(例如大約150℃)下且持續約30分鐘至約2小時的時間的退火製程來固化。
所形成的UBM 156的半徑R1約100μm至約250μm。所形成的開口160的半徑R2約70μm至約220μm。UBMS156的半徑R1大於開口160的半徑R2。導電環164具有環形的外形，此環形外形的外徑(outer radius)R3為約100μm至約250μm， 且此環形外形的內徑(inner radius)R4為約50μm至約200μm。不同的半徑之間的關係式為：R1>R3>R2>R4。
所形成的導電環164具有寬度W1。寬度W1是導電環164的外徑R3和內徑R4之間的差值。在導電環164是通過印刷形成的銅膏的實施例中，寬度W1為約30μm至約50μm。銅膏的印刷技術可能有至30微米的不準確性。如此，無論印刷錯誤或偏移，至少30μm的寬度W1可確保介電層158和UBM 156的界面完全被導電環164密封。此外，增加UBM 156的暴露出的表面積允許導電連接件168的材料在回流期間更容易擴散。如此，至50μm的寬度W1可確保UBM 156具有足夠的被暴露出的表面積。
在圖17B中，在UBM 156上塗覆助焊劑166。助焊劑166可以是例如免清洗助焊劑。助焊劑166可以通過例如噴射製程(jetting process)而施加到UBM 156的表面，並且所形成的助焊劑166可以具有約25μm至約50μm的厚度。導電環164充當阻障物，防止助焊劑166在UBM 156和介電層158之間的界面處發生反應。助焊劑166形成在導電環164的內徑的邊界內。
在圖17C中，在開口160中和UBM 156上(例如在助焊劑166上)形成導電連接件168。每個導電連接件168完全延伸穿過導電環164的中間部分。導電連接件168可以是球柵陣列(ball grid array，BGA)連接件、焊球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、ENEPIG形成的凸塊等。導電連接件168可以包括諸如焊料、銅、鋁、金、 鎳、銀、鈀、錫等等的導電材料或其組合。在一些實施例中，導電連接件168的形成方法包括先藉由如蒸鍍、電鍍、印刷、焊料轉移、植球等常用方法形成焊料層。一旦在結構上形成了一層焊料，就可以進行回流以便將材料成形為所需的凸塊形狀。在另一個實施例中，導電連接件168是通過濺射、印刷、電鍍、化學鍍、CVD等方法形成的金屬柱(例如銅柱)。金屬柱可以不含焊料，並具有實質上垂直側壁。在一些實施例中，在金屬柱的頂部上形成金屬頂蓋層(未示出)。金屬頂蓋層可以包括鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金等或其組合，並且可以通過鍍覆製程形成。在形成之後，導電連接件168具有半徑R5。在一個實施例中，導電連接件168的半徑R5大於導電環164的內徑R4。
在回流期間，助焊劑166可能被消耗，並且導電連接件168潤擴散至導電環164和UBM 156。此外，導電環164和UBM 156的材料在回流期間形成金屬間化合物(inermetalliz compound，IMC)170。IMC 170可以共形於下伏的UBM 156的形狀。在回流期間，導電連接件168和導電環164的材料也形成IMC 172。IMC 172可以共形於下伏的導電環164的形狀。由於UBM 156和導電環164是不同的材料，所以IMC 170和IMC 172是不同的化合物。此外，雖然導電連接件168和IMC 170和IMC 172被示出為具有可區分的界面，但應了解各種導電材料在回流期間可能混合。如此一來，在導電連接件168和IMC 170以及IMC 172的界面174處可形成IMC(未示出)，其包括來自導電連接件168、導電環164 與UBM 156的導電材料。
而且在導電連接件168的回流期間，導電環164具有阻障作用，可以防止助焊劑166在UBM 156和介電層158之間流動。在UBM 156和介電層158的界面處可以形成氧化物(例如氧化銅)，以充當黏著層。助焊劑166可沖走黏著層，且防止助焊劑166流入界面可提高UBM 156與介電層158之間的黏附性。如此一來，可降低界面分層的可能性。UBM 156和介電層158的分層可能導致可回流材料(reflowable material)進入界面，這可能導致介電層破裂(crack)。通過減小界面處的分層，可以改善前側重佈線結構132的機械可靠度。
圖18是示出形成導電環164之後且形成導電連接件168之前的區650的放大俯視圖。換句話說，圖18是圖17B所示的中間步驟的俯視圖。
在圖19中，執行承載基底分離，以將承載基底100從背側重佈線結構110(例如背側重佈線結構110的介電層104)分離(去接合)。藉此在第一封裝區600和第二封裝區602中的每一者中形成第一封裝200。根據一些實施例，去接合包括在離型層102上投射光線(諸如雷射光線或UV光線)，使得離型層102在光線的熱量下分解並且使得承載基底100可以被移除。隨後，將結構翻轉並放置在膠帶176上。此外，形成穿過介電層104的開口178，以暴露出部分金屬化圖案106。開口178可以例如使用雷射鑽孔、蝕刻等方法來形成。
圖20至圖21示出了根據一些實施例的在用於形成封裝結構500的製程期間的中間步驟的剖視圖。封裝結構500可以被稱為疊層封裝(packge-on-package，PoP)結構。
在圖20中，第二封裝300附接到第一封裝200。第二封裝300包括基底302和耦接到基底302的一個或多個堆疊晶粒308(包括晶粒308A和晶粒308B)。儘管示出了堆疊晶粒308(包括晶粒308A和晶粒308B)的單一堆疊，但在其他實施例中，多個堆疊晶粒308(各自具有一個或多個堆疊晶粒)可以並排地(side by side)耦接到基底302的同一表面。基底302可以由諸如矽、鍺、金剛石等半導體材料製成。在一些實施例中，也可以使用諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化物、磷化砷鎵、磷化銦鎵、其組合等化合物材料。另外，基底302可以是絕緣體上覆矽(SOI)基底。一般而言，SOI基底包括半導體材料層，諸如磊晶矽、鍺、矽鍺、SOI、絕緣體上覆矽鍺(silicon germanium-on-insulator，SGOI)或其組合。在一個替代實施例中，基底302是基於諸如玻璃纖維增強樹脂芯的絕緣芯。芯材料的一個實例是玻璃纖維樹脂，例如FR4。芯材料的替代品包括雙馬來醯亞胺-三嗪(bismaleimide-triazine，BT)樹脂，或者其他印刷電路板(PCB)材料或膜。基底302可以使用味之素增層膜(Ajinomoto build-up film，ABF)或其他層壓材料。
基底302可以包括主動元件和被動元件(未示出)。如所屬領域中具有通常知識者所認知，可以使用諸如電晶體、電容器、 電阻器、其組合等的各種元件來產生對於第二封裝300的結構上與功能上的要求。上述元件可以使用任何合適的方法形成。
基底302還可以包括金屬化層(未示出)和穿孔306。金屬化層可以形成在主動元件和被動元件上，並且被設計成連接各種元件以形成功能電路。金屬化層可以由交替堆疊的介電質(例如低介電材料)和導電材料(例如銅)形成，其中通孔互連導電材料層。金屬化層可以通過任何合適的製程(例如沉積、鑲嵌、雙鑲嵌等)形成。在一些實施例中，基底302是實質上不具有主動元件和被動元件的。
基底302可在基底302的第一側上具有接合接墊303以耦接至堆疊晶粒308，並且在基底302的第二側上具有接合接墊304以耦接至導電連接件314。基底302的第二側與第一側相對。在一些實施例中，通過在基底302的第一側和第二側上的介電層(未示出)中形成凹槽(未示出)而形成接合接墊303和接合接墊304。凹槽可以形成為可允許接合接墊303和接合接墊304被嵌入到介電層中。在其他實施例中，由於可以在介電層上形成接合接墊303和304，故可省去形成凹槽。在一些實施例中，接合接墊303和接合接墊304包括由銅、鈦、鎳、金、鈀等或其組合製成的薄晶種層(未示出)。接合接墊303和接合接墊304的導電材料可以沉積在薄晶種層上。導電材料可以通過電化學鍍覆製程、無電鍍製程、CVD、原子層沉積(atomic layer deposition，ALD)、PVD等或其組合的方法來形成。在一個實施例中，接合接墊303和接合 接墊304的導電材料是銅、鎢、鋁、銀、金等或其組合。
在一個實施例中，接合接墊303和接合接墊304是包括三層導電材料(例如鈦層、銅層和鎳層)的UBM。然而，所屬領域中具有通常知識者將會認識到材料和層具有許多合適的配置。舉例而言，適用於形成接合接墊303和接合接墊304的排列包括鉻/鉻銅合金/銅/金的排列、鈦/鈦鎢/銅的排列或銅/鎳/金的排列。可以用於接合接墊303和接合接墊304的任何合適的材料或材料層皆屬於在本申請的範疇。在一些實施例中，穿孔306延伸穿過基底302並且將至少一個接合接墊303耦接到至少一個接合接墊304。
在所示實施例中，堆疊晶粒308通過打線310與基底302耦接，但也可以使用其他連接，例如導電凸塊，以使堆疊晶粒308與基底302耦接。在一個實施例中，堆疊晶粒308是堆疊記憶體晶粒。舉例而言，堆疊晶粒308可以是低功率(low-power，LP)雙倍資料速率(double data rate，DDR)記憶體模組的記憶體晶粒，低功率雙倍資料速率記憶體模組例如是LPDDR1、LPDDR2、LPDDR3、LPDDR4或其類似的記憶體模組。
堆疊晶粒308和打線310可以藉由模製材料312包封。模製材料312可以例如使用壓縮模製而模製於堆疊晶粒308和打線310上。在一些實施例中，模製材料312是模製化合物、聚合物、環氧樹脂、氧化矽填充材料等、或其組合。可以執行固化製程以固化模製材料312。固化製程可以是熱固化、UV固化等、或其 組合。
在一些實施例中，堆疊晶粒308和打線310被埋入於模製材料312中。並且在模製材料312固化之後，執行平坦化步驟(例如研磨)，以移除模製材料312的多餘部分並且為第二封裝300提供實質上平整的表面。
在形成第二封裝300之後，通過導電連接件314、接合接墊304和金屬化圖案106將第二封裝300機械地和電性地接合到第一封裝200。在一些實施例中，堆疊晶粒308可通過打線接合310、接合接墊303和接合接墊304、穿孔306、導電連接件314和穿孔112將耦接到積體電路晶粒114。
儘管導電連接件314和導電連接件168不需要是相同的，但是導電連接件314可以類似於上述的導電連接件168，並且此處不再重複描述。導電連接件314可以設置在基底302的與堆疊晶粒308相對的一側上，且位於開口178中。在一些實施例中，也可以在基底302的與堆疊晶粒308相對的一側上形成焊料抗蝕劑。導電連接件314可以設置在焊料抗蝕劑的開口中，以與基底302中的導電特徵(例如，接合接墊304)電性耦接和機械耦接。焊料抗蝕劑可用於保護基底302的區域，免受外部損傷。
在一些實施例中，在將導電連接件314進行接合之前，於導電連接件314上塗覆助焊劑(未示出)，助焊劑例如是免清洗助焊劑。導電連接件314可以浸於助焊劑中，或可以將助焊劑噴到導電連接件314上。在另一個實施例中，助焊劑可以施加於金 屬化圖案106的表面。
在一些實施例中，導電連接件314可以選擇性地具有形成在其上方的環氧助焊劑(未示出)，此環氧助焊劑可以在回流前形成。在第二封裝300附接到第一封裝200之後，導電連接件314回流，而環氧助焊劑的至少一些環氧部分殘留下來。
於第一封裝200與第二封裝300之間可形成底部填充件(未示出)，且底部填充件圍繞導電連接件314。底部填充件可以減小應力並保護由導電連接件314的回流導致的接面(joint)。底部填充件可以在第一封裝200附接之後通過毛細管流動製程形成，或者可以在第一封裝200附接之前通過合適的沉積方法形成。在形成環氧助焊劑的實施例中，環氧助焊劑可以充當底部填充件。
第二封裝300和第一封裝200之間的接合可以是焊料接合。在一個實施例中，第二封裝300通過回流製程與第一封裝200接合。在回流製程期間，導電連接件314與接合接墊304和金屬化圖案106接觸，以將第二封裝300物理性地和電性地與第一封裝200耦接。在接合製程之後，金屬化圖案106與導電連接件314的界面處可形成金屬間化合物(IMC，未示出)。並且IMC也可以形成在導電連接件314和接合接墊304之間的界面處(未示出)。
通過沿切割道區(例如在第一封裝區600和第二封裝區602之間)鋸切以執行單體化製程。上述鋸切使第一封裝區600自第二封裝區602分離。所產生的單體化的第一封裝200和第二封裝300來自第一封裝區域600或第二封裝區域602中的一者。在 一些實施例中，在將第二封裝300附接到第一封裝200之後執行單體化製程。在其他實施例中(未示出)，在第二封裝300附接到第一封裝200之前執行單體化製程，例如在承載基底100被解除接合且形成開口178之後。
在圖21中，使用導電連接件168將第一封裝200安裝到封裝基底400。封裝基底400可以由諸如矽、鍺、金剛石等半導體材料製成。或者，也可以使用諸如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、矽鍺碳化合物、磷化砷鎵、磷化銦鎵及其組合等化合物材料。另外，封裝基底400可以是SOI基底。一般而言，SOI基底包括諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其組合的半導體材料的層。在一個替代實施例中，封裝基底400是基於諸如玻璃纖維增強樹脂芯的絕緣芯。芯材料的一個例子是玻璃纖維樹脂，例如FR4。芯材料的替代品包括雙馬來酰亞胺三嗪BT樹脂，或者其他PCB材料或膜。封裝基底400可以使用積層膜，如ABF或其他層壓板。
封裝基底400可能包括主動元件和被動元件(未示出)。如所屬領域中具有通常知識者所認知，可以使用諸如電晶體、電容器、電阻器、其組合等的各種元件來產生對於封裝結構500的設計的結構和功能要求。上述元件可以使用任何合適的方法形成。
封裝基底400還可以包括金屬化層和通孔(未示出)，且包括金屬化層和通孔上的接合接墊402。金屬化層可以形成在主動元件和被動元件上，並且被設計成連接各種元件以形成功能電路。金屬化層可以由交替堆疊的介電質(例如低介電材料)和導電材料 (例如銅)形成，其中通孔互連導電材料層。金屬化層可以通過任何合適的製程(如沉積、鑲嵌、雙鑲嵌等)形成。在一些實施例中，封裝基底400實質上不含主動元件和被動元件。
在一些實施例中，導電連接件168經回流以將第一封裝200附接到接合接墊402。導電連接件168將封裝基底400電性地及/或物理性地耦接第一封裝200，包括將封裝基底400的金屬化層電性地及/或物理性地耦接至第一封裝200。在一些實施例中，在安裝到封裝基底400上之前，可以將被動元件(例如，表面安裝元件(SMD)，未示出)附接至第一封裝200(例如，接合到接合接墊402)。在此實施例中，被動元件可以與導電連接件168接合到第一封裝200的同一表面。
在導電連接件168回流之前，可在導電連接件168上形成環氧樹脂助焊劑。在第一封裝200被附接至封裝基底400之後，環氧樹脂助焊劑的至少一些環氧樹脂部分殘留下來。剩餘的環氧樹脂部分可作為底部填充件，以降低應力並保護由導電連接件168回流產生的接點(joint)。在一些實施例中，在第一封裝200與封裝基底400之間並圍繞導電連接件168可形成底部填充件(未示出)。底部填充件可以在第一封裝200附接之後通過毛細管流動製程形成，或者可以在第一封裝200附接之前通過合適的沉積方法形成。
實施例可以實現以下優點。用導電環164密封UBM 156和介電層158的界面可有助於防止界面分層，增加前側重佈線結 構132的機械可靠度。將導電環164形成為約30μm至約50μm的寬度W1可允許UBM156與導電連接件168之間的足夠接觸面積，同時允許使用印刷形成製程。
在一個實施例中，半導體封裝包括：積體電路晶粒；所述積體電路晶粒上的第一介電層；穿過所述第一介電層而延伸以電連接到所述積體電路晶粒的第一金屬化圖案；所述第一金屬化圖案上的第二介電層；延伸穿過所述第二介電層的凸塊下金屬；在所述第二介電層上和所述凸塊下金屬的部分上的第三介電層；密封所述第三介電層和所述凸塊下金屬的界面的導電環；以及延伸穿過所述導電環的中心的導電連接件，所述導電連接件電連接到所述凸塊下金屬。
在一個實施例中，所述半導體封裝更包括：在所述凸塊下金屬上的助焊劑，所述助焊劑鄰接所述導電環的內側壁，所述導電連接件位於所述助焊劑上。在所述半導體封裝的一個實施例中，所述導電環自所述第一介電層分離所述導電連接件。在所述半導體封裝的一個實施例中，所述凸塊下金屬延伸穿過所述第二介電層中的開口，所述凸塊下金屬具有第一半徑，所述開口具有小於第一半徑的第二半徑。在所述半導體封裝的一個實施例中，所述導電環在所述開口的周圍，所述導電環具有環形，所述環形具有外徑和內徑，所述外徑與所述內徑之間的差值為30μm到50μm。在所述半導體封裝的一個實施例中，所述凸塊下金屬的所述第一半徑大於所述導電環的所述外徑。在所述半導體封裝的一個實施例中， 所述開口的所述第二半徑大於所述導電環的所述內徑且小於所述導電環的所述外徑。在所述半導體封裝的一個實施例中，所述凸塊下金屬的所述第一半徑大於所述開口的所述第二半徑。在所述半導體封裝的一個實施例中，所述導電環沿著所述第三介電層的頂面和所述凸塊下金屬延伸。在所述半導體封裝的一個實施例中，所述導電環和所述凸塊下金屬包括不同的導電材料。
在一個實施例中，半導體封裝包括：積體電路晶粒；鄰近於所述積體電路晶粒的穿孔；所述穿孔和所述積體電路晶粒周圍的包封體；以及重佈線結構，包括：所述第一介電層上的第一金屬化圖案，所述第一介電層設置於所述包封體上，所述第一金屬化圖案延伸穿過所述第一介電層以電連接到所述穿孔；所述第二介電層上的凸塊下金屬，所述第二介電層設置於所述第一介電層上，所述凸塊下金屬延伸穿過所述第二介電層以電連接到所述第一金屬化圖案；以及在第三介電層上的導電環，所述第三介電層設置於所述第二介電層上，所述導電環密封所述第三介電層和所述凸塊下金屬的界面。
在一個實施例中，所述半導體封裝更包括：在所述凸塊下金屬和所述導電環上的導電連接件，所述導電環自所述第三介電層分離所述導電連接件。在一個實施例中，所述半導體封裝更包括：通過所述導電連接件而與所述重佈線結構電連接及物理連接的基底。在所述半導體封裝的一個實施例中，所述導電環從所述導電環延伸穿過所述第三介電層，從所述第三介電層的頂面延伸到 所述凸塊下金屬的頂面。
在一個實施例中，一種半導體封裝的製造方法包括：在積體電路晶粒上沉積設置第一介電層；形成沿著所述第一介電層延伸的第一金屬化圖案；在所述第一金屬化圖案和所述第一介電層上沉積第二介電層；形成沿所述第二介電層延伸的凸塊下金屬；在所述凸塊下金屬和所述第二介電層上沉積第三介電層；在所述第三介電層中形成暴露出所述凸塊下金屬的開口；在所述第三介電層和所述凸塊下金屬的界面分配導電膏；以及固化所述導電膏以形成密封所述第三介電層和所述凸塊下金屬的所述界面的導電環。
在所述半導體封裝的製造方法的一個實施例中，所述導電膏是焊膏。在所述方法的一個實施例中，所述固化所述導電膏包括：在約100℃至約200℃的溫度下對所述的所述焊膏進行退火，所述退火的時間為30分鐘至2小時。在一個實施例中，所述半導體封裝的製造方法更包括：在所述凸塊下金屬的暴露部分塗覆助焊劑，所述導電環自定義所述開口的所述第三介電層的側面分離所述助焊劑；在所述助焊劑和所述導電環上放置導電連接件。在一個實施例中，所述半導體封裝的製造方法更包括：回流所述導電連接件以形成第一金屬間化合物(IMC)和第二IMC，所述第一IMC形成在所述導電連接件與所述凸塊下金屬的界面，所述第二IMC形成於所述導電環與所述凸塊下金屬的界面。在所述方法的一個實施例中，所述分配所述導電膏包括：在所述凸塊下金屬上印刷所述導電膏，所述導電膏在定義所述開口的所述第三介電層的側面 上，且所述導電膏在所述第三介電層的接近所述側面的頂部部分上。
以上概述了若干實施例的特徵，以便本領域技術人員可以更好地理解本公開的各方面。本領域技術人員應該理解，他們可以容易地使用本公開作為設計或修改其他製程和結構的基礎，以實現與本文介紹的實施例相同的目的及/或實現相同的優點。本領域技術人員還應該認識到，這樣的等同構造不脫離本公開的精神和範圍，並且可以在不脫離本公開的精神和範圍的情況下進行各種改變，替換和變更。
100‧‧‧承載基底
102‧‧‧離型層
104、108、134、140、146、152、158‧‧‧介電層
106‧‧‧金屬化圖案
110‧‧‧背側重佈線結構
112‧‧‧穿孔
114‧‧‧積體電路晶粒
116‧‧‧黏著劑
130‧‧‧包封體
132‧‧‧前側重佈線結構
138、144、150‧‧‧金屬化圖案
156‧‧‧凸塊下金屬
164‧‧‧導電環
168‧‧‧導電連接件
600‧‧‧第一封裝區
602:第二封裝區
650:區

Claims (14)

  1. 一種半導體封裝，包括：積體電路晶粒；第一介電層，位於所述積體電路晶粒上；第一金屬化圖案，延伸穿過所述第一介電層而電連接於所述積體電路晶粒；第二介電層，在所述第一金屬化圖案上；凸塊下金屬，延伸穿過所述第二介電層；第三介電層，在所述第二介電層上和部分的所述凸塊下金屬上；導電環，密封所述第三介電層和所述凸塊下金屬的界面；以及導電連接件，延伸穿過所述導電環的中心，所述導電連接件電連接到所述凸塊下金屬。
  2. 如申請專利範圍第1項所述的半導體封裝，更包括：助焊劑，在所述凸塊下金屬上，所述助焊劑鄰接所述導電環的內側壁，所述導電連接件位於所述助焊劑上。
  3. 如申請專利範圍第1項所述的半導體封裝，其中：所述導電環分離所述第三介電層與所述導電連接件；或所述凸塊下金屬延伸穿過所述第二介電層中的開口，所述凸塊下金屬具有第一半徑，所述開口具有小於所述第一半徑的第二半徑；或 所述導電環沿著所述第三介電層和所述凸塊下金屬的頂面延伸；或所述導電環和所述凸塊下金屬包括不同的導電材料。
  4. 如申請專利範圍第3項所述的半導體封裝，其中所述導電環在所述開口周圍，所述導電環具有環形，所述環形具有外徑和內徑，所述外徑與所述內徑的差值為30μm至50μm。
  5. 如申請專利範圍第4項所述的半導體封裝，其中：所述凸塊下金屬的所述第一半徑大於所述導電環的所述外徑；或所述開口的所述第二半徑大於所述導電環的所述內徑且小於所述導電環的所述外徑；或所述凸塊下金屬的所述第一半徑大於所述開口的所述第二半徑。
  6. 一種半導體封裝，包括：積體電路晶粒；穿孔，鄰近於所述積體電路晶粒；包封體，位於所述穿孔和所述積體電路晶粒周圍；以及重佈線結構，包括：第一金屬化圖案，位於所述第一介電層上，所述第一介電層設置於所述包封體上，所述第一金屬化圖案延伸穿過所述第一介電層以與所述穿孔電連接；凸塊下金屬，位於所述第二介電層上，所述第二介電層 設置於所述第一介電層上，所述凸塊下金屬延伸穿過所述第二介電層以與所述第一金屬化圖案電連接；以及導電環，位於第三介電層上，所述第三介電層設置於所述第二介電層上，所述導電環密封所述第三介電層和所述凸塊下金屬的界面。
  7. 如申請專利範圍第6項所述的半導體封裝，更包括：導電連接件，位於所述凸塊下金屬和所述導電環上，所述導電環分離所述第三介電層以及所述導電連接件。
  8. 如申請專利範圍第7項所述的半導體封裝，更包括：基底，通過所述導電連接件而與所述重佈線結構電連接和物理連接。
  9. 如申請專利範圍第6項所述的半導體封裝，其中所述導電環延伸穿過所述第三介電層，從所述第三介電層的頂面延伸至所述凸塊下金屬的頂面。
  10. 一種半導體封裝的製造方法，包括：在積體電路晶粒上沉積設置第一介電層；形成沿著所述第一介電層延伸的第一金屬化圖案；在所述第一金屬化圖案和所述第一介電層上沉積第二介電層；形成沿所述第二介電層延伸的凸塊下金屬；在所述凸塊下金屬和所述第二介電層上沉積第三介電層；在所述第三介電層中形成暴露出所述凸塊下金屬的開口；在所述第三介電層和所述凸塊下金屬的界面分配導電膏；以 及固化所述導電膏以形成密封所述第三介電層和所述凸塊下金屬的所述界面的導電環。
  11. 如申請專利範圍第10項所述的半導體封裝的製造方法，其中：所述導電膏為焊膏；或所述分配所述導電膏包括：在所述凸塊下金屬上印刷所述導電膏，所述導電膏在定義所述開口的所述第三介電層的側面上，且所述導電膏在所述第三介電層的接近所述側面的頂部部分上。
  12. 如申請專利範圍第11項所述的半導體封裝的製造方法，其中所述固化所述導電膏包括：在約100℃至約200℃的溫度下對所述的所述焊膏進行退火，所述退火的時間為30分鐘到2小時。
  13. 如申請專利範圍第10項所述的半導體封裝的製造方法，更包括：在所述凸塊下金屬的暴露部分塗覆助焊劑，所述導電環分離所述助焊劑與定義所述開口的所述第三介電層的側面；在所述助焊劑和所述導電環上放置導電連接件。
  14. 如申請專利範圍第13項所述的半導體封裝的製造方法，更包括：回流所述導電連接件以形成第一金屬間化合物和第二金屬間化合物，所述第一金屬間化合物形成於所述導電連接件和所述凸 塊下金屬的界面，所述第二金屬間化合物形成在所述導電環和所述凸塊下金屬的界面。
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