TWI567900B - 半導體裝置及封裝組件 - Google Patents

半導體裝置及封裝組件 Download PDF

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Publication number
TWI567900B
TWI567900B TW101147091A TW101147091A TWI567900B TW I567900 B TWI567900 B TW I567900B TW 101147091 A TW101147091 A TW 101147091A TW 101147091 A TW101147091 A TW 101147091A TW I567900 B TWI567900 B TW I567900B
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Taiwan
Prior art keywords
layer
bump
metal layer
crack
underlying metal
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TW101147091A
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TW201332073A (zh
Inventor
陳玉芬
林俊宏
普翰屏
董志航
吳凱強
何明哲
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台灣積體電路製造股份有限公司
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Description

半導體裝置及封裝組件
本發明係有關於半導體封裝結構，且特別是有關於一種半導體裝置及封裝組件。
一般而言，半導體晶粒可使用例如球柵陣列(ball grid array)或覆晶接合技術(controlled collapse chip connection，C4)之焊料凸塊(solder bump)等技術接合至其它基板，例如一有機印刷電路板。在上述製程中，焊料凸塊可使用例如電鍍、焊料漏印(paste screening)、或球架(ball mount)等方法形成於此半導體晶粒、基板、或兩者上，隨後再將焊料回流(reflow)為所需的凸塊形狀。形成焊料凸塊後，半導體晶粒上的接觸點(contact)與其對應之基板上的接觸點對準，焊料凸塊位於二接觸點之間。對準後，再度回流並液化此焊料凸塊，其中液化之焊料流經並潤濕接觸墊(contact pads)，提供半導體晶粒及基板之間的電性及實體連接。
然而，半導體晶粒可能具有與基板差異極大的熱膨脹係數。此時，當半導體晶粒接合至基板並共同經過一熱機循環(thermo-mechanical cycling)，模擬系統電力開關循環以達到JEDEC可靠度測試需求後，半導體晶粒及基板可能在加熱循環時延展，且在冷卻循環期間收縮而成為不同長度。這種延展會於連接半導體晶粒及基板的焊料接合點(solder joint)形成應力，此問題特別常見於半導體晶粒及基 板之間的連接，特別是因半導體晶粒及基板間的熱膨脹係數不匹配所造成的強應力，其可在連接半導體晶粒及基板的焊料接合點產生裂縫(crack)，這些裂縫隨後可能擴散至整個接合點，劣化或破壞半導體晶粒及基板之間的電性導通及/或實體連接。這樣的破壞可能使此部份失效並需要重新製作。
本發明一實施例提供一種半導體裝置，包括：一凸塊底層金屬層，設置於一半導體基板上；以及一止裂物，設置於凸塊底層金屬層上，止裂物沿凸塊底層金屬層之外緣區域設置，其中，止裂物為一空心圓柱體，其包括由至少二開口所分隔之至少二區段，且至少二開口之一第一總面積(A)及至少二區段之一第二總面積(B)，其符合下列公式：0.7*B>A>0.03*B。
本發明另一實施例提供一種封裝組件，包括：一半導體晶粒；一基板；以及一焊料連接結構；其中，半導體晶粒透過焊料連接結構電性及實體耦接至基板；其中，半導體晶粒包括一半導體基板，一凸塊底層金屬層設置於半導體基板下方，以及一止裂物設置於凸塊底層金屬層下方，並沿凸塊底層金屬層之外緣設置；其中，止裂物為一空心圓柱體，具有由至少二開口分隔之至少二區段；以及其中，至少二開口之一第一總面積(A)及至少二區段之一第二總面積(B)符合下列公式：0.7*B>A>0.03*B。
為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
這些實施例為特定背景之實施例，亦即晶圓級晶片封裝、覆晶接合技術、或堆疊式封裝(package-on-package，PoP)內連接結構中，用於半導體晶粒及基板間焊料接合點的止裂物之實施例。然而，這些實施例亦可應用於其它接合製程。
參照第1圖，顯示了具有一半導體基底基板102、一接觸墊104、一鈍化保護層(passivation layer)106、一第一保護層(protective layer)108、一後鈍化保護內連線(post-passivation interconnect layer，PPI)層110、一第二保護層112、一凸塊底層金屬層114、一止裂物116、及一凸塊118之半導體晶粒100。
半導體基底基板102可包括摻雜或未摻雜之矽塊材、或一絕緣層上矽晶(silicon on inculator，SOI)基板之主動層。一般而言，絕緣層上矽晶基板包括一半導體材料層，例如矽、鍺、矽化鍺、絕緣層上矽晶、絕緣層上矽鍺(silicon germanium on insulator，SGOI)、或前述之組合。可使用其它基板，包括多層基板、漸變基板(gradient substrate)、或 混合晶向基板(hybrid orientation substrate)。可於半導體基底基板102之中或之上形成不同主動裝置及/或被動裝置，可於半導體基底基板102上形成一內連接結構以連接不同主動裝置及/或被動裝置而形成功能性電路，內連接結構可包括金屬化層、及金屬層間介電層(IMD layer)。
接觸墊104形成於最上層的介電層上並連接至內連接結構最上層的金屬化層，接觸墊104可包括鋁，亦可使用其它材料，例如銅。鈍化保護層106形成於內連接結構上方的半導體基底基板102上，隨後被圖案化形成一開口以露出部份接觸墊104。鈍化保護層106可使用一種或多種適當介電材料製作，例如氧化矽、氮化矽、低介電常數介電質(例如，摻碳氧化物)、極低介電常數介電質(例如，多孔摻碳二氧化矽)、前述之組合等等。
第一保護層108形成於鈍化保護層106上，且被圖案化形成另一開口以露出部份接觸墊104。此穿透第一保護層108之開口可電性連接接觸墊104及後鈍化保護內連線層110。第一保護層108可使用一種或多種適當高分子材料製作，例如環氧樹脂、聚亞醯胺、苯並環丁烯(benzocyclobutene，BCB)、聚苯並噁唑(polybenzoxazole，PBO)等等，亦可使用其它相對柔軟、通常為有機的介電材料。另外，第一保護層108可使用與鈍化保護層106相似的材料形成，例如氧化矽、氮化矽、低介電常數介電質(例如，摻碳氧化物)、極低介電常數介電質(例如，多孔摻碳二氧化矽)、或前述之組合等等。
後鈍化保護內連線層110為設置於第一保護層108上 之一圖案化金屬化層，其透過第一保護層108電性連接至接觸墊104。在一些實施例中，後鈍化保護內連線層110可包括銅、鋁、銅合金、鎳、金、其它導電材料其中至少任一者。在一些實施例中，後鈍化保護內連線層110可包括位於上述金屬化層上之一介電層，例如一氮化矽層、一氧化物層等等。在一些實施例中，此後鈍化保護內連線層110可用以作為電源線、重佈線(redistribution line，RDL)、電感、電容、或任何被動元件。在一實施例中，後鈍化保護內連線層110包括一內連線區域110A及一接合墊區域(landing pad)110B，一凸塊特徵在後續製程中形成於接合墊區域110B上並電性連接至接合墊區域110B。在一實施例中，接合墊區域110B可如第1圖所示，不直接設置於接觸墊104上。在另一實施例中，接合墊區域110B可直接設置於接觸墊104上。
第二保護層112形成於後鈍化保護內連線層110上且露出第一保護層108之表面。可圖案化第二保護層112以形成一開口以露出一部份後鈍化保護內連線層110之接合墊區域110B。第二保護層112可使用一種或多種適當高分子材料製作，例如環氧樹脂、聚亞醯胺、苯並環丁烯、聚苯並噁唑等等，亦可使用其它相對柔軟、通常為有機的介電材料。在一些實施例中，第二保護層112使用與第一保護層108相似或相同的材料形成。
凸塊底層金屬層114可形成於接合墊區域110B的露出部份上。在一實施例中，凸塊底層金屬層114可沿第二保護層112之開口的底部及側壁形成，並延伸於第二保護層 112的表面上至一預定距離。在一實施例中，凸塊底層金屬層114可包括由鈦、銅鈦合金、鎳、或前述之合金構成之導電材料其中至少一者。使用其它適當導電材料或不同材料層之組合作為凸塊底層金屬層114亦屬本發明之範疇。凸塊底層金屬層114可藉由形成位於第二保護層112及其開口上的各層膜層來製作，可使用一鍍膜製程形成凸塊底層金屬層114，例如電鍍，但亦可視所需材料而使用其他形成方法，例如濺鍍、蒸鍍、或物理氣相沈積製程。形成所需膜層之後，隨後可藉由一適當微影罩幕及蝕刻步驟移除不需要的材料而移除一部分的凸塊底層金屬層114，使凸塊底層金屬層114具有所需的外形，例如圓形、八角形、正方形、長方形，但其他適當形狀亦可。
止裂物116可形成於凸塊底層金屬層114上並與其實體接觸。在一些實施例中，可使用一罩幕及鍍膜製程形成止裂物116，如第1~3圖所繪示。止裂物116可由一導電材料形成，例如銅，但其他導電材料例如鎳、金、合金、或前述之組合亦可。
可以由凸塊底層金屬層114延伸至凸塊118內的方式放置並形成止裂物116，亦可以截斷並阻止任何由凸塊底層金屬層114及/或後鈍化保護內連線層110邊緣發生之裂痕的方式放置及形成止裂物116，防止裂痕進一步散佈至凸塊底層金屬層114及/或後鈍化保護內連線層110內部。
第2圖為一止裂物116及凸塊底層金屬層114的平面示意圖，其繪示了止裂物116的設置方式及外形。在此實施例中，止裂物116可設置於接近凸塊底層金屬層114外 緣114p處並可成形為一空心圓柱體，例如一環形，其外緣116e接近凸塊底層金屬層114的外緣114p。在一實施例中，凸塊底層金屬層114的直徑(D)，且止裂物116外緣與凸塊底層金屬層114外緣之間的距離(d)符合此公式：1/3*D>d>3微米。例如，D=240微米則80微米>d>3微米。止裂物116的厚度為W，高度為H。在至少一實施例中，其高度對厚度的比例(H/W)如下：H/W大於或等於1、或H/W大於或等於2。在一些實施例中，厚度W小於約20微米，例如為約15微米。在一些實施例中，高度H可大於約15微米，或可大於約20微米，例如為約30微米。此外，止裂物116可具有至少二開口117a及117b，以分隔止裂物116為二區段116a及116b。在一實施例中，開口117a及117b共同具有一俯角觀察之總開口面積A(即，由基板102厚度的方向觀察)，且區段116a及116b共同具有一俯角觀察之總止裂物區域B。區域A及B符合此公式：0.7*B>A>0.03*B。
第3圖為根據本發明另一實施例所繪示之止裂物116及凸塊底層金屬層114的平面示意圖。在此實施例中，止裂物116可設置於接近凸塊底層金屬層114外緣114p處且可成形為環形，例如一空心圓柱體，其外緣116e接近凸塊底層金屬層114外緣114p並與其之間具有一距離d。在一實施例中，直徑D及距離d符合此公式：1/3*D>d>3微米。在此實施例中，止裂物116具有四個開口117’a、117’b、117’c、及117’d，使止裂物116分隔為四個區段116’a、116’b、116’c、及116’d。在一實施例中，開口117’a、117’b、 117’c、及117’d具有俯角觀察之總開口面積A，且區段116’a、116’b、116’c、及116’d具有俯角觀察之總止裂物面積B。區域A及B符合此公式：0.7*B>A>0.03*B。
藉由將止裂物116成形為具有開口117的空心圓柱體並環繞於凸塊底層金屬層114外緣114p，沿凸塊底層金屬層114及/或後鈍化保護內連線層110之外緣發生並向內部擴散的裂痕，會垂直地遇上止裂物116。此垂直的交互作用有助於防止裂痕進一步擴散進入凸塊底層金屬層114及/或後鈍化保護內連線層110，止裂物116可藉此防止裂痕劣化半導體晶粒100的效能。空心圓柱體中的開口117可作為應力緩和之用，例如在熱循環時，當空心圓柱體的材料膨脹，開口117可使此空心圓柱體在不會擠壓到空心圓柱體其他部份的條件下膨脹，故可降低在熱循環時因熱膨脹係數不匹配所引起的應力造成損傷。
然而，本技術領域具有通常知識者應知上述環形及/或空心圓柱體係為用以說明之實施例，其形狀並不限於此，其它可保有空心圓柱體狀但非完全呈圓形之形狀亦屬本發明之範疇。例如，止裂物116之外緣116e可成形為八角形、五角形、六角形等等，但大體保有環形之形狀。在一些實施例中，止裂物116之內緣可具有與止裂物116之外緣不同形狀。
參照第1圖，在形成止裂物116之後，於凸塊底層金屬層114上形成凸塊118以覆蓋止裂物116。在一實施例中，凸塊118為一焊料凸塊，其可藉由於凸塊底層金屬層114上附著一焊料球，隨後再熱回流此焊料而形成。在一 些實施例中，此焊料凸塊可包括一無鉛預焊層(lead-free pre-solder layer)、銀錫合金、包括錫、鉛、銀、銅、鎳、鉍之合金的一焊料、或前述之組合。在一些實施例中，此焊料可藉由電鍍一焊料層配合微影技術，隨後再進行一回流步驟而形成。在一些實施例中，焊料118的直徑為約200微米至約300微米。在其他實施例中，焊料118的直徑為約100微米至約200微米。在又一實施例中，焊料118的直徑小於約100微米。藉由於凸塊底層金屬層114上設置止裂物116，可防止可能形成於焊料118內部的裂痕擴散。止裂物116可提供更佳的焊料接合潤濕性，防止孔洞形成於焊料接合結構內部。
第4~9圖為根據第1圖之實施例所繪示之於半導體晶粒上形成止裂物之中間步驟。
參照第4圖，半導體基板102包括一基板10、一電路12、一內層介電(ILD)層14、一金屬層間介電(IMD)層16及相關金屬化層。
根據本發明一實施例，基板10的一部份具有電路形成於其上。基板10可包括摻雜或未摻雜之矽塊材、或一絕緣層上半導體基板之主動層。基板10可為晶圓級尺寸或晶片級尺寸，亦可使用其他基板，例如多層基板、或漸變基板。
形成於基板10上的電路12可為具有特定用途之任何類型的電路。在一實施例中，電路12可包括形成於基板10上的電子裝置，且具有一層或多層介電層設置於此電子裝置上方。可於介電層之間形成金屬層以傳遞電子裝置間的電子信號。電子裝置亦可形成於一層或多層介電層之 中，例如，電路12可包括不同n型金氧半導體(NMOS)及/或p型金氧半導體(PMOS)裝置，例如電晶體、電容、電阻、二極體、光電二極體、熔絲等等，彼此內連接以提供一種或多種功能，這些功能可包括記憶體結構、處理結構、感測器、放大器、配電(power distribution)電路、輸入/輸出電路等等。本技術領域具有通常知識者應知上述實施例僅進一步說明本發明一些實施例之應用，其並非用以限定本發明，亦可使用其他具有特定用途之電路。
內層介電層14可由例如一低介電常數介電材料所構成，例如摻磷矽玻璃(PSG)、摻硼磷矽玻璃(BPSG)、摻氟矽玻璃(FSG)、SiOxCy、旋塗式玻璃(Spin-On-Glass)、旋塗高分子層(Spin-On-Polymers)、碳化矽材料、或前述之組合。內層介電層14可藉由任何適當方法形成，例如旋塗、化學氣相沈積、及/或物理氣相沈積。在一些實施例中，內層介電層14可包括複數介電層。可形成穿透內層介電層14的接觸點(未顯示於圖中)，以提供一電性接觸至電路12。
一層或多層金屬層間介電(IMD)層16及相關金屬化層形成於內層介電層14上。通常此一層或多層金屬層間介電層16及相關金屬化層(例如金屬導線18及介層連接窗19)可用於將電路12相互內連接，以提供一外部電性連接。金屬層間介電層16可使用一低介電常數介電材料(例如，以電漿輔助化學氣相沈積法或高密度電漿化學氣相沈積法等方法形成之摻氟矽玻璃)，且其可包括居中的蝕刻停止層。在一些實施例中，可設置一層或多層蝕刻停止層(未顯示於圖中)於相鄰介電層之間，例如內層介電層14及金屬層間 介電層16之間。通常此蝕刻停止層可在形成介層連接窗及/或接觸點時用以停止蝕刻程序。此蝕刻停止層可使用與鄰接層具有不同蝕刻選擇比的介電材料形成，例如與下方之半導體基板10、上方之內層介電層14、及上方之金屬層間介電層16具有不同蝕刻選擇比的介電材料。在一實施例中，蝕刻停止層可使用氮化矽、氮化碳矽、氧化碳矽、氮化碳、或前述之組合等等形成，且可使用化學氣相沈積法或電漿輔助化學氣相沈積法沈積。
在一些實施例中，上述金屬化層，包括金屬導線18及介層連接窗19，可使用銅或銅合金、或其他材料形成。此外，上述金屬化層可包括一頂部金屬層20，其形成並被圖案化於金屬層間介電層16之上或之中，以提供外部電性連接並保護下方膜層免於各種環境污染物。在一些實施例中，此最上層之金屬層間介電層可使用一介電材料形成，例如氮化矽、氧化矽、未摻雜之矽玻璃等等。在後續圖式中，並未繪示半導體基板10、電路12、內層介電層14、金屬化層，例如金屬導線18及介層連接窗19。在一些實施例中，頂部金屬層20可為最上層之金屬層間介電層上的部份頂部金屬化層。
隨後，形成並圖案化接觸墊104以接觸頂部金屬層20或藉由一介層連接窗電性連接頂部金屬層20。在一些實施例中，此接觸墊104可使用鋁、鋁銅合金、鋁合金、銅、銅合金等等形成。一層或多層鈍化保護層(例如一鈍化保護層106)可由一介電材料所形成，例如未摻雜之矽玻璃(un-doped silicate glass，USG)、氮化矽、氧化矽、氮氧化 矽、或無孔洞材料，且可使用如化學氣相沈積法、物理氣相沈積法等方法形成。可形成鈍化保護層106以覆蓋接觸墊104邊緣部份，且透過鈍化保護層106中的開口露出接觸墊104中央部份。鈍化保護層106可為單層或多層，在第4圖中所顯示之單層接觸墊及鈍化保護層僅作為說明之用，其他實施例可包括任何層數的導電層及/或鈍化保護層。
隨後，可於鈍化保護層106上形成並圖案化第一保護層108。在一些實施例中，第一保護層108可為一高分子層，其被圖案化形成一開口109以露出接觸墊104。在一些實施例中，此高分子層可由一高分子材料所形成，例如環氧樹脂、聚亞醯胺、苯並環丁烯、聚苯並噁唑等等，亦可使用其它相對柔軟、通常為有機之介電材料。其形成方法可包括旋塗或其他方法。第一保護層108的厚度可介於約1微米至約10微米之間，例如其厚度可介於約5微米至約8微米之間。
參照第5圖，可於第一保護層108上形成至少一金屬化層110並填充開口109，隨後此金屬化層可被圖案化為一內連線層110，其可電性連接至接觸墊104並可露出位於其下方之第一保護層108的一部份。在至少一實施例中，內連線層110為一後鈍化保護內連線層110，其亦可作為電源線、重佈線(redistribution lines，RDL)、電感、電容、或任何被動元件。後鈍化保護內連線層110可包括一內連線區域110A及一接合墊區域110B，在一些實施例中，內連線區域110A及接合墊區域110B可同時形成且可 使用相同導電材料形成。可於後續步驟中形成一凸塊特徵於接合墊區域110B上並使其電性連接至接合墊區域110B。在一些實施例中，後鈍化保護內連線層110可包括銅、鋁、銅合金、或其他導電材料，且可使用鍍膜、電鍍、濺鍍、化學氣相沈積法等方法形成。在一實施例中，後鈍化保護內連線層110可包括銅或銅合金。在第5圖之實施例中，接合墊區域110B並非直接接觸於接觸墊104上。在其他實施例中，藉由此接合墊區域110B的佈線(routing)，接合墊區域110B可直接接觸於接觸墊104上。
參見第5圖，隨後於基板10上形成一第二保護層112以覆蓋後鈍化保護內連線層110。藉由使用微影及/或蝕刻步驟，可進一步圖案化第二保護層112以形成一開口113，露出後鈍化保護內連線層110之接合墊區域110B的至少一部份。開口113的形成方法可包括微影、濕蝕刻或乾蝕刻、雷射鑽孔(laser drill)等方法。在一些實施例中，第二保護層112可由一高分子層所形成，例如環氧樹脂、聚亞醯胺、苯並環丁烯、聚苯並噁唑等等形成，亦可使用其它相對柔軟、通常為有機之介電材料。在一些實施例中，第二保護層112可使用選自未摻雜之矽玻璃、氮化矽、氮氧化矽、氧化矽、前述之組合之無機材料。
如第6圖所示，於整體表面上形成第一凸塊底層金屬層114a以覆蓋第二保護層112，以及接合墊區域110B露出部份，使其電性連接至後鈍化保護內連線層110。隨後於凸塊底層金屬層114a上形成一圖案化第二凸塊底層金屬層114b，於接合墊區域110B上(即止裂物116所形成之 處)形成一圖案化凸塊底層金屬層114b。隨後於凸塊底層金屬層114a及114b上形成並圖案化光阻層115，使其具有一開口115a以露出第二凸塊底層金屬層114b的一部分，開口115a的形狀、尺寸、及位置分別與止裂物116對應。凸塊底層金屬層114a及114b可由金屬沈積法所形成。在一些實施例中，凸塊底層金屬層114a及114b可包括至少一金屬化層，包括鈦、鉭、氮化鈦、氮化鉭、銅、銅合金、鎳、錫、金、或前述之組合。在一實施例中，凸塊底層金屬層114a可包括至少一含鈦層，凸塊底層金屬層114b可包括至少一含銅層。
如第7圖所示，形成導電材料以填充光阻層115之開口115a並電性連接至第一凸塊底層金屬層114a及第二凸塊底層金屬層114b。在移除光阻層115之後，留在凸塊底層金屬層114b上的導電材料層用以形成止裂物116，如第8圖所繪示。在至少一實施例中，止裂物116包括一銅金屬層。此銅金屬層可包括純元素銅、包含不可避免雜質之銅、及/或包含微量元素例如鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁、鋯之銅合金。止裂物116可使用濺鍍、印刷、電鍍、無電鍍、電化學沈積(electrochemical deposition，ECD)、分子束磊晶(molecular beam epitaxy，MBE)、原子層沈積(atomic layer deposition，ALD)、及/或常用化學氣相沈積法形成。在一實施例中，此銅層可使用電化學鍍膜(electro-chemical plating，ECP)形成。
隨後，如第9圖所示，可蝕刻第一凸塊底層金屬層114a露出的表面，留下止裂物116於第一凸塊底層金屬層114a 及第二凸塊底層金屬層114b上。在一些實施例中，凸塊底層金屬層的蝕刻步驟可使用一濕蝕刻或乾蝕刻步驟。可在此凸塊底層金屬層蝕刻步驟蝕刻第二凸塊底層金屬層114b，使第二凸塊底層金屬層114b的邊緣可實質上與止裂物116外緣對準。
隨後，於凸塊底層金屬層114上形成凸塊118以覆蓋止裂物116，如第1圖所示。凸塊118可為焊料凸塊、銅凸塊、或包括鎳或金之金屬凸塊。在一實施例中，凸塊118為一焊料凸塊，其可藉由附著焊料球於凸塊底層金屬層114上後熱回流此焊料球而形成。在一些實施例中，此焊料凸塊可包括無鉛預焊層、錫化銀、或包括錫、鉛、銀、銅、鎳、鉍之焊料、或前述之組合。在一些實施例中，此焊料凸塊可使用電鍍一焊料層配合光學微影技術，隨後實施一回流製程而形成。
在形成焊料之後，可例如形成一封膠材料、實施一單粒化(singulation)製程以單粒化個別晶粒100、實施晶圓等級或晶粒等級堆疊等等。然而需注意的是，這些實施例可應用於多種不同情況，例如上述實施例可用於晶粒對晶粒接合(die-to-die bonding)結構、晶粒對晶圓接合(die-to-wafer bonding)結構、晶圓對晶圓接合(wafer-to-wafer bonding)結構、晶粒級封裝、晶圓級封裝等等。
第10圖為一剖面圖，用以說明覆晶封裝組件的一實施例。將第1圖所繪示之半導體晶粒100翻轉為頂面朝下並貼附至另一基板200之底部，如第10圖所繪示。在一些實施例中，基板200可為封裝基板、電路板(例如印刷電路板， PCB)、晶圓、晶粒、轉接基板(interposer substrate)、或其它適當基板。上述凸塊結構可經由不同導電連接點電性連接至基板200，例如形成並圖案化導電區域202於基板200上。導電區域202為接觸墊或導電走線(conductive trace)的一部分，其可由罩幕層204所定義。在一實施例中，罩幕層204為一防焊層，其形成並圖案化於基板200上以露出導電區域202。罩幕層204具有一罩幕開口，其提供一開口以形成焊料接合點。舉例而言，焊料層可包括錫、鉛、銀、銅、鎳、鉍、前述之合金、或前述之組合，並可形成於導電區域202上。在一些實施例中，半導體晶粒100可連接至基板200以在接合墊區域110B及導電區域202之間形成接合點結構206。在一實施例中，接合點結構206為一焊料接合點特徵。藉由於凸塊118中形成止裂物116，止裂物116在封裝步驟之後可鑲嵌於焊料接合點結構206中，以提供更佳的接合方式及無孔洞的接合點結構，使封裝組件達到良好的焊料接合點品質及提昇熱疲勞壽命。舉例而言，可使用一耦接步驟形成一焊料接合點結構，其包括塗上助焊劑(flux application)、放置晶片、回焊(reflowing of melting solder joints)、及/或清潔。半導體晶粒100、接合點結構206、及基板200可視為一封裝結構300，在本實施例中則可視為一覆晶封裝結構。
在另一實施例中，半導體晶粒100可使用如第11圖所示之非阻焊層(non-solder mask)技術翻轉為頂面朝下並貼附至另一基板400。導電區域202為一接觸墊或一導電走線的一部分，其並非由罩幕層204所定義而成。
根據本發明一實施例，提供一種半導體裝置，包括：一凸塊底層金屬層，設置於一半導體基板上；以及一止裂物，設置於凸塊底層金屬層上，止裂物沿凸塊底層金屬層之外緣區域設置，其中，止裂物為一空心圓柱體，其包括由至少二開口所分隔之至少二區段，且至少二開口之一第一總面積(A)及至少二區段之一第二總面積(B)，其符合下列公式：0.7*B>A>0.03*B。
根據本發明另一實施例，提供一種封裝組件，包括：一半導體晶粒；一基板；以及一焊料連接結構；其中，半導體晶粒透過焊料連接結構電性及實體耦接至基板；其中，半導體晶粒包括一半導體基板，一凸塊底層金屬層設置於半導體基板下方，以及一止裂物設置於凸塊底層金屬層下方，並沿凸塊底層金屬層之外緣設置；其中，止裂物為一空心圓柱體，具有由至少二開口分隔之至少二區段；以及其中，至少二開口之一第一總面積(A)及至少二區段之一第二總面積(B)符合下列公式：0.7*B>A>0.03*B。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，可在不脫離本發明之精神和範圍內改變形成止裂物的材料及方法。此外，為了有助於防止或減少裂痕的延伸可改變止裂物的實質外形。
再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明 揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧基板
12‧‧‧電路
14‧‧‧內層介電層
16‧‧‧金屬層間介電層
18‧‧‧金屬導線
19‧‧‧介層連接窗
20‧‧‧頂部金屬層
100‧‧‧半導體晶粒
102‧‧‧基底基板
104‧‧‧接觸墊
106‧‧‧鈍化保護層
108‧‧‧第一保護層
109‧‧‧開口
110‧‧‧金屬化層
110A‧‧‧內連線區域
110B‧‧‧接合墊區域
112‧‧‧第二保護層
113‧‧‧開口
114‧‧‧凸塊底層金屬層
114a‧‧‧第一凸塊底層金屬層
114b‧‧‧第二凸塊底層金屬層
114p‧‧‧凸塊底層金屬層114之外緣
115‧‧‧光阻層
115a‧‧‧開口
116‧‧‧止裂物
116a、116b、116’a、116’b、116’c、116’d‧‧‧止裂物之區段
116e‧‧‧止裂物之外緣
117a、117b、117’a、117’b、117’c、117’d‧‧‧止裂物之開口
118‧‧‧凸塊
200‧‧‧基板
202‧‧‧導電區域
204‧‧‧罩幕層
206‧‧‧接合點結構
300‧‧‧封裝結構
D‧‧‧凸塊底層金屬層的直徑
d‧‧‧止裂物外緣與凸塊底層金屬層外緣之間的距離
H‧‧‧止裂物的高度
W‧‧‧止裂物的厚度
第1圖係繪示出根據本發明一實施例之剖面示意圖，用以說明設置於半導體晶粒上之一止裂物。
第2圖係繪示出根據本發明一實施例之平面示意圖，用以說明具有開口之止裂物。
第3圖係繪示出根據本發明另一實施例之平面示意圖，用以說明具有開口之止裂物。
第4~9圖係繪示出根據本發明一實施例之於半導體基板上形成止裂物之方法剖面示意圖。
第10圖係繪示出根據本發明一實施例之剖面示意圖，用以說明具有連接至一基板的止裂物焊料之半導體晶粒。
第11圖係繪示出根據本發明一實施例之剖面示意圖，用以說明具有連接至另一基板的止裂物焊料之半導體晶粒。
102‧‧‧基底基板
104‧‧‧接觸墊
106‧‧‧鈍化保護層
108‧‧‧第一保護層
110A‧‧‧內連線區域
110B‧‧‧接合墊區域
112‧‧‧第二保護層
114a‧‧‧第一凸塊底層金屬層
114b‧‧‧第二凸塊底層金屬層
116‧‧‧止裂物

Claims (8)

  1. 一種半導體裝置，包括：一凸塊底層金屬層，設置於一半導體基板上；以及一止裂物，設置於該凸塊底層金屬層上，該止裂物沿該凸塊底層金屬層之外緣區域設置；其中，該止裂物為一空心圓柱體，其包括由至少二開口所分隔之至少二區段，且該至少二開口之一第一總面積(A)及該至少二區段之一第二總面積(B)，其符合下列公式：0.7*B>A>0.03*B，其中該止裂物外緣及該凸塊底層金屬層外緣之間的距離(d)大於3微米，該凸塊底層金屬層的直徑(D)及該距離(d)符合下列公式：1/3*D>d>3微米。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該止裂物的厚度為W，高度為H，其比例H/W大於或等於1。
  3. 如申請專利範圍第1項所述之半導體裝置，更包括一焊料凸塊，設置於該凸塊底層金屬層上並覆蓋該止裂物。
  4. 如申請專利範圍第1項所述之半導體裝置，更包括：一內連接層，設置於該凸塊底層金屬層下方；一鈍化保護層，設置於該內連接層下方；以及一高分子層，設置於該內連接層及該凸塊底層金屬層之間。
  5. 一種封裝組件，包括：一半導體晶粒；一基板；以及一焊料連接結構； 其中，該半導體晶粒透過該焊料連接結構電性及實體耦接至該基板；其中，該半導體晶粒包括一半導體基板，一凸塊底層金屬層設置於該半導體基板下方，以及一止裂物設置於該凸塊底層金屬層下方，並沿該凸塊底層金屬層之外緣設置；其中，該止裂物為一空心圓柱體，具有由至少二開口分隔之至少二區段；以及其中，該至少二開口之一第一總面積(A)及該至少二區段之一第二總面積(B)符合下列公式：0.7*B>A>0.03*B，其中該止裂物的外緣及該凸塊底層金屬層外緣之間的距離(d)大於3微米，該凸塊底層金屬層的直徑(D)及該距離(d)符合下列公式：1/3*D>d>3微米。
  6. 如申請專利範圍第5項所述之封裝組件，其中該止裂物的厚度為W，高度為H，其比例H/W大於或等於1。
  7. 如申請專利範圍第5項所述之封裝組件，其中該止裂物形成於該焊料連接結構中。
  8. 如申請專利範圍第5項所述之封裝組件，其中該半導體晶粒更包括：一內連接層，設置於該凸塊底層金屬層下方；一鈍化保護層，設置於該內連接層下方；以及一高分子層，設置於該內連接層及該凸塊底層金屬層之間。
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