CN108630676B - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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CN108630676B
CN108630676B CN201711290793.5A CN201711290793A CN108630676B CN 108630676 B CN108630676 B CN 108630676B CN 201711290793 A CN201711290793 A CN 201711290793A CN 108630676 B CN108630676 B CN 108630676B
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die
package
integrated circuit
layer
thermal element
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CN108630676A (zh
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余振华
叶德强
普翰屏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

实施例是封装件，包括第一封装结构。第一封装结构包括：具有有源侧和背侧的第一集成电路管芯，有源侧包括管芯连接件，邻近第一集成电路管芯的第一通孔，横向密封第一集成电路管芯和第一通孔的密封剂，位于第一集成电路管芯的管芯连接件和第一通孔上并且电连接至第一集成电路管芯的管芯连接件和第一通孔的第一再分布结构，和位于第一集成电路管芯的背侧上的热元件。该封装件还包括：通过第一组导电连接件接合至第一通孔和热元件的第二封装结构。本发明的实施例还涉及半导体封装件及其形成方法。

Description

半导体封装件及其形成方法
技术领域
本发明的实施例涉及半导体封装件及其形成方法。
背景技术
由于各个电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的持续改进，半导体工业经历了快速增长。对于大部分而言，集成密度的改进来自于最小部件尺寸的迭代减小，从而允许将更多组件集成到给定的区域。随着对缩小电子器件的需求的增长，对半导体管芯的更小、更具创意的封装技术的需求已经出现。这种封装系统的实例是堆叠式封装(PoP)技术。在PoP器件中，顶部半导体封装件堆叠在底部半导体封装件的顶部上以提供高水平的集成和组件密度。PoP技术通常能够在印刷电路板(PCB)上产生具有增强的功能和小的覆盖区的半导体器件。
发明内容
本发明的实施例提供了一种封装件，包括：第一封装结构，包括：第一集成电路管芯，具有有源侧和背侧，所述有源侧包括管芯连接件；第一通孔，邻近所述第一集成电路管芯；密封剂，横向密封所述第一集成电路管芯和所述第一通孔；第一再分布结构，位于所述第一集成电路管芯的所述管芯连接件和所述第一通孔上并且电连接至所述第一集成电路管芯的所述管芯连接件和所述第一通孔；和热元件，位于所述第一集成电路管芯的背侧上；以及第二封装结构，通过第一组导电连接件接合至所述第一通孔和所述热元件。
本发明的另一实施例提供了一种形成封装件的方法，包括：形成第一封装件，包括：在载体衬底上方形成电连接件；使用粘合层将第一管芯附接至所述载体衬底，所述电连接件从所述第一管芯的背侧延伸至所述第一管芯的有源侧，所述有源侧与所述背侧相对，所述电连接件邻近所述第一管芯；用模塑料密封所述第一管芯和所述电连接件；在所述第一管芯的有源侧、所述模塑料和所述电连接件上面形成第一再分布结构；去除所述载体衬底以暴露所述电连接件的第一端和所述粘合层；去除所述粘合层以暴露所述第一管芯的背侧；和在所述第一管芯的暴露的背侧上形成热元件；在所述热元件和所述电连接件的第一端上方形成第一组导电连接件；以及使用所述第一组导电连接件将第二封装件接合至所述第一封装件，所述第二封装件接近所述第一管芯的背侧。
本发明的又一实施例提供了一种形成封装件的方法，包括：形成第一封装件，包括：在载体衬底上方形成电连接件；使用粘合层将第一管芯附接至所述载体衬底，所述第一管芯包括位于所述第一管芯的背侧上的所述粘合层内的导电焊盘，所述电连接件从所述第一管芯的背侧延伸至所述第一管芯的有源侧，所述有源侧与所述背侧相对，所述电连接件邻近所述第一管芯；用模塑料密封所述第一管芯和所述电连接件；在所述第一管芯的有源侧、所述模塑料和所述电连接件上面形成再分布结构；去除所述载体衬底以暴露所述电连接件的第一端和所述粘合层；去除所述粘合层以暴露所述导电焊盘和所述第一管芯的背侧；和在所述导电焊盘和所述电连接件的第一端上形成第一组导电连接件；以及使用所述第一组导电连接件将第二封装件接合至所述第一封装件，所述第二封装件邻近所述第一管芯的背侧。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图12示出了根据一些实施例的在用于形成封装结构的工艺期间的中间步骤的截面图。
图13A和图13B示出了根据一些实施例的另一封装结构的截面图和平面图。
图14示出了根据一些实施例的另一封装结构的截面图。
图15至图18示出了根据一些实施例的在用于另一封装结构的工艺期间的中间步骤的截面图。
图19至图21示出了根据一些实施例的在用于另一封装结构的工艺期间的中间步骤的截面图。
图22至图25示出了根据一些实施例的在用于另一封装结构的工艺期间的中间步骤的截面图。
图26至图29示出了根据一些实施例的在用于另一封装结构的工艺期间的中间步骤的截面图。
图30至图35示出了根据一些实施例的在用于另一封装结构的工艺期间的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
此处讨论的实施例可以在特定上下文中讨论，即，包括位于半导体管芯的背侧上的热元件的封装结构。公开的实施例中的热元件不是用于电连接封装结构中的器件或金属化图案，而是用于消散来自封装结构的热量。在一些实施例中，热元件没有连接至散热路径，而在一些实施例中，热元件连接至半导体管芯中的散热路径。例如，热元件可以连接至通孔(热耦合/连接至半导体管芯中的一个或多个晶体管)以消散由晶体管产生的热量。与不包括位于半导体管芯的背侧上的热元件的封装结构相比，本发明的实施例可以改进封装结构的热阻(℃/瓦)高达约8％。
此外，本公开的教导适用于包括一个或多个半导体管芯的任何封装结构。其他实施例考虑其他应用，诸如不同的封装类型或不同的配置对于基于阅读本发明的本领域中普通技术人员是显而易见的。应该注意，此处讨论的实施例可能不必要示出可能存在于结构中的每个组件或部件。例如，可以从图中省略多个组件，诸如当讨论一个组可能足以传达实施例的方面时。此外，此处讨论的方法实施例可以讨论为以特定顺序实施；然而，其他方法实施例可以以任何逻辑顺序实施。
图1至图12示出了根据一些实施例的在用于形成第一封装结构的工艺期间的中间步骤的截面图。图1示出了载体衬底100和形成在载体衬底100上的释放层102。示出了分别用于形成第一封装件和第二封装件的第一封装区域600和第二封装区域602。
载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以是晶圆，从而使得可以在载体衬底100上同时形成多个封装件。释放层102可以由聚合物基材料形成，其可以与将载体衬底100一起从将在随后的步骤中形成的上面的结构去除。在一些实施例中，释放层102是环氧基热释放材料(诸如光热转换(LTHC)释放涂层)，当加热时，失去其粘合性。在其他实施例中，释放层102可以是紫外(UV)胶，当暴露于UV光时，失去其粘合性。释放层102可以以液体分配并且固化，可以是层压至载体衬底100上的层压膜等。释放层102的顶表面可以被水平化并且可以具有高度的共面性。
此外，在图1中，形成电连接件112。例如，为了形成电连接件112，在释放层102上方形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如物理汽相沉积(PVD)等形成晶种层。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于通孔。该图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中并且在晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成电连接件112。
在图2中，集成电路管芯114通过粘合剂116粘合至释放层102。如图2示出的，在第一封装区域600和第二封装区域602的每个中粘合一个集成电路管芯114，并且在其他实施例中，可在每个区域中粘合多个集成电路管芯114。例如，在实施例中，可以在每个区域中粘合两个集成电路管芯114或四个集成电路管芯114。集成电路管芯114可以是逻辑管芯(例如，中央处理单元、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如，电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微电子机械系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯)、前端管芯(例如，模拟前端(AFE)管芯)等或它们的组合。同样，在每个区域中具有多个管芯的实施例中，集成电路管芯114可以是不同的尺寸(例如，不同的高度和/或表面积)，并且在其他实施例中，集成电路114可以是相同的尺寸(例如，相同的高度和/或表面积)。
在被粘合至释放层102之前，可以根据适用的制造工艺处理集成电路管芯114以在集成电路管芯114中形成集成电路。例如，集成电路管芯114的每个均包括半导体衬底118，诸如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括其他半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。可以使用诸如多层或梯度衬底的其他衬底。可以在半导体衬底118中和/或上形成诸如晶体管、二极管、电容器、电阻器等的器件并且通过例如在半导体衬底118上的一个或多个介电层中的金属化图案形成的互连结构120互连该器件以形成集成电路。
集成电路管芯114还包括诸如铝焊盘的焊盘122以制成外部连接。焊盘122位于可以称为集成电路管芯114的相应的有源侧上。钝化膜124位于集成电路管芯114上并且位于焊盘122的部分上。开口穿过钝化膜124至焊盘122。诸如导电柱(例如，包括诸如铜的金属)的管芯连接件126位于穿过钝化膜124的开口中并且机械和电连接至相应的焊盘122。可以通过例如镀等形成管芯连接件126。管芯连接件126电连接集成电路管芯114的相应的集成电路。
介电材料128位于集成电路管芯114的有源侧上，诸如位于钝化膜124和管芯连接件126上。介电材料128横向密封管芯连接件126，并且介电材料128与相应的集成电路管芯114横向相连。介电材料128可以是聚合物，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等。在其他实施例中，介电材料128由氮化物，诸如氮化硅；氧化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等；等或它们的组合形成，并且可以例如通过旋涂、层压、化学汽相沉积(CVD)等形成。
粘合剂116位于集成电路管芯114的背侧上并且将集成电路管芯114粘合至释放层102。粘合剂116可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。在一些实施例中，粘合剂具有在从约5μm至约30μm的范围内的厚度，其中，该厚度在垂直于相应的集成电路管芯114的背侧的方向上测量。可以将粘合剂116施加至集成电路管芯114的背侧，诸如施加至相应的半导体晶圆的背侧，或者可以施加在载体衬底100的表面上方。可以切割(例如，通过锯切或分割)集成电路管芯114并且使用例如拾取放置工具通过粘合剂116粘合至释放层102。
在图3中，在各个组件上形成密封剂130。密封剂130可以是模塑料、环氧树脂等，并且可以通过压缩模塑、转移模塑等施加。在固化之后，密封机130可以经受研磨工艺以暴露电连接件112和管芯连接件126。在研磨工艺之后，电连接件112、管芯连接件126和密封剂130的顶面齐平。在一些实施例中，例如，如果已经暴露电连接件112和管芯连接件126，则可以省略研磨。电连接件112在下文中可以称为通孔112。
在图4中，形成前侧再分布结构160。前侧再分布结构160包括介电层132、140、148和156以及金属化图案138、146和154。
可以通过在密封剂130、通孔112和管芯连接件126上沉积介电层132开始前侧再分布结构160的形成。在一些实施例中，介电层132由聚合物形成，该聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其他实施例中，介电层132由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG等或它们的组合形成。
下一步，之后，图案化介电层132。图案化形成开口，开口暴露通孔112和管芯连接件126的部分。可以通过可接受的工艺图案化，可接受的工艺诸如当介电层132是感光材料时，将介电层132暴露于光或者通过使用例如各向异性蚀刻的蚀刻。如果介电层132是感光材料，则在曝光之后，可以显影介电层132。
下一步，在介电层132上形成具有通孔的金属化图案138。作为形成金属化图案138的实例，在介电层132上方和穿过介电层132的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案138。该图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中并且在晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案138和通孔。在开口中形成穿过介电层132至例如通孔112和/或管芯互连件126的通孔。
可以对介电层140和148以及金属化图案和通孔146和154重复该工艺以继续再分布结构160的形成。用于形成再分布结构160的这些层的材料和工艺与介电层132以及金属化图案和通孔138类似并且此处不再重复描述。
在金属化图案和通孔154的形成之后，在金属化图案154和介电层148上沉积介电层156。在一些实施例中，介电层156由聚合物形成，该聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其他实施例中，介电层156由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层156。
下一步，之后，图案化介电层156。该图案化形成开口，开口暴露金属化图案154的部分。可以通过可接受的工艺图案化，可接受的工艺诸如当介电层156是感光材料时，将介电层156暴露于光或者通过使用例如各向异性蚀刻的蚀刻。如果介电层156是感光材料，则在曝光之后，可以显影介电层156。
前侧再分布结构160示出为实例。可以在前侧再分布结构160中形成更多或更少的介电层和金属化图案。如果形成更少的介电层和金属化图案，则可以省略上述步骤和工艺。如果形成更多的介电层和金属化图案，则可以重复上述步骤和工艺。本领域普通技术人员将容易理解哪些步骤和工艺将被省略或重复。
下一步，在前侧再分布结构160的外侧上形成焊盘162。焊盘162用于连接至导电连接件166(见图5)并且可以称为凸块下金属(UBM)162。在示出的实施例中，通过穿过介电层156至金属化图案154的开口来形成焊盘162。作为形成焊盘162的实例，在介电层156上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于焊盘162。该图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中并且在晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成焊盘162。在实施例中，在不同地形成焊盘162的情况下，可以使用更多的光刻胶和图案化步骤。
在图5中，在UBM 162上形成导电连接件166。导电连接件166可以是球栅阵列(BGA)连接件、焊料球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件166可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或他们的组合。在一些实施例中，通过诸如蒸发、电镀、印刷、焊料转移、球放置等通用的方法初始形成焊料层来形成导电连接件166。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接件166是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(例如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱连接件166的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金等或它们的组合，并且可以通过镀工艺形成。
在图6中，实施载体衬底分离以使载体衬底100与集成电路管芯114、通孔112和密封剂130分开(分离)。根据一些实施例，分离包括将诸如激光或UV光的光投射到释放层102上，使得释放层102在光的热量下分解，并且可以去除载体衬底100。之后，翻转结构并且将该结构放置在胶带190上。
进一步如图6示出的，暴露通孔112的端部。在一些实施例中，可以实施蚀刻或清洗以从通孔112的端部去除残留物。
在图7中，去除粘合剂116以暴露集成电路管芯114的背侧，例如，集成电路管芯114的衬底118的背侧。可以通过任何合适的工艺去除粘合剂116，诸如剥落粘合剂116，对粘合剂层116投射诸如激光或UV光的光，使得粘合剂层116在光的热量下分解，蚀刻粘合剂116等。
粘合剂116的去除在集成电路管芯114的背侧上方形成凹槽180。凹槽180具有从密封剂130的顶面至相应的集成电路管芯114的衬底118的暴露表面测量的深度D1。在一些实施例中，凹槽180的深度D1在从约5μm至约30μm的范围内。
在图8中，在集成电路管芯114的衬底118的暴露表面上形成焊盘182。焊盘182不是用于电连接集成电路管芯114或封装结构中的器件或金属化图案，而是用于消散来自集成电路管芯114和/或封装结构的热量。在一些实施例中，焊盘182可以称为热焊盘182，该热焊盘182用于消散来自集成电路管芯114的热量。在一些实施例中，热焊盘182没有连接至集成电路管芯114中的散热路径，而在一些实施例中，热焊盘182连接至集成电路管芯114中的散热路径(例如，见图12)。
热焊盘182也用于热连接至连接件316(见图9)并且可以称为凸块下金属(UBM)182。在示出的实施例中，在集成电路管芯114的衬底118的背侧上形成热焊盘182。作为形成热焊盘182的实例，在衬底118的背侧上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于热焊盘182。该图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中并且在晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成热焊盘182。在实施例中，在不同地形成热焊盘182的情况下，可以使用更多的光刻胶和图案化步骤。
例如，在另一实施例中，在衬底118的背侧上方形成晶种层并且在晶种层上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。在形成导电材料之后，可以在导电材料上方形成并且图案化对应于热焊盘182的位置的掩模。在一些实施例中，光刻胶或硬掩模用作掩模。在图案化掩模之后，诸如通过可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除导电材料和晶种层的暴露部分(例如，导电材料和晶种层没有位于掩模下方的部分)。晶种层和导电材料的剩余部分形成热焊盘182。在该实施例中，热焊盘182从焊盘的顶面至焊盘的底面可以具有倾斜的侧壁182A(例如，变宽的侧壁)。如图8示出的，热焊盘182的倾斜的侧壁182A意味着在那个实施例中，热焊盘182具有比顶面更大的底面。虽然仅在图8的热焊盘182的一个上示出了倾斜的侧壁182A，但是在该实施例中，所有热焊盘182都将具有倾斜的侧壁182A。
在先前的实施例中，在光刻胶的开口内形成导电材料的情况下，热焊盘182的侧壁可以基本垂直于基板118的背侧。
在一些实施例中，可以在通孔112的暴露的端部上形成UBM或焊盘(未示出)。该UBM或焊盘可以与上述的热焊盘182和/或焊盘162类似地形成，并且此处不再重描述。
在图9中，导电连接件314和316分别形成在通孔112和热焊盘182上方并且分别连接至通孔112和热焊盘182。导电连接件314用于将图9的封装结构电连接至其他封装结构(例如，图10中的封装结构300)。与热焊盘182类似，导电连接件316不是用于电连接集成电路管芯114或封装结构中的器件或金属化图案，而是用于消散来自集成电路管芯114和/或封装结构的热量。因此，导电连接件316在下文中可以称为热连接件316。通过利用热焊盘182和热连接件316，与不包括热焊盘和热连接件的封装结构相比，该封装结构的热阻(℃/瓦)可以改进高达约8％。
导电连接件314和热连接件316可以是BGA连接件、焊料球、金属柱、C4凸块、微凸块、ENEPIG形成的凸块等。导电连接件314和热连接件316可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，通过诸如蒸发、电镀、印刷、焊料转移、球放置等通用的方法初始形成焊料层来形成导电连接件314和热连接件316。一旦已经在结构上形成焊料层，则可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接件314和热连接件316是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(例如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱连接件314和316的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金等或它们的组合，并且可以通过镀工艺形成。
在图10中，封装结构300接合至图9的具有导电连接件314和热连接件316的封装结构。封装结构300包括衬底302和连接至衬底302的一个或多个堆叠管芯308(308A和308B)。衬底302可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，衬底302可以是绝缘体上硅(SOI)衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合的半导体材料层。在一个可选实施例中，衬底302基于诸如玻璃纤维增强树脂芯的绝缘芯。核心材料的一个实例是诸如FR4的玻璃纤维树脂。核心材料的替代物包括双马来酰亚胺-三嗪(BT)树脂或者其他印刷电路板(PCB)材料或薄膜。诸如味之素积聚膜(ABF)或其他层压材料的积聚膜可以用于衬底302。
衬底302可以包括有源和无源器件(未在图10中示出)。本领域中普通技术人员将意识到，可以使用诸如晶体管、电容器、电阻器、这些的组合等的多种器件来产生用于半导体封装件300的结构和功能需求的设计。可以使用任何合适的方法形成器件。
衬底302也可以包括金属化层(未示出)和通孔306。金属化层可以形成在有源和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，其中，通孔互连导电材料层，并且金属化层可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，衬底302基本无有源和无源器件。
衬底302可以具有位于衬底302的第一侧的接合焊盘303以连接至堆叠管芯308以及位于衬底302的第二侧上的接合焊盘304和热焊盘305，第二侧与衬底302的第一侧相对，以连接至连接件314和316。在一些实施例中，省略热焊盘305。在一些实施例中，通过在衬底302的第一和第二侧上的介电层(未示出)内形成凹槽来形成接合焊盘303和304以及热焊盘305。该凹槽可以形成为允许接合焊盘303和304以及热焊盘305嵌入至介电层内。在其他实施例中，由于接合焊盘303和304以及热焊盘305可以形成在介电层上，因此可以省略凹槽。在一些实施例中，接合焊盘303和304以及热焊盘305包括由铜、钛、镍、金、钯等或它们的组合制成的薄晶种层(未示出)。可以在薄晶种层上方沉积接合焊盘303和304以及热焊盘305的导电材料。可以通过电化学电镀工艺、无电电镀工艺、CVD、ALD、PVD等或它们的组合来形成导电材料。在实施例中，接合焊盘303和304以及热焊盘305的导电材料是铜、钨、铝、银、金等或他们的组合。
在一些实施例中，接合焊盘303和304以及热焊盘305是包括导电材料的三层的UBM，该三层诸如钛层、铜层和镍层。然而，本领域中普通技术人员将意识到，存在适合于形成UBM 303、304和305的许多合适的材料和层的布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或者铜/镍/金的布置。可以用于UBM 303、304和305的任何合适的材料或材料层完全旨在被包括在本申请的范围内。在一些实施例中，通孔306穿过衬底302延伸并且将至少一个接合焊盘303连接至至少一个接合焊盘304。
在示出的实施例中，堆叠管芯308通过接合线310连接至衬底302，但是可以使用其他连接，诸如导电凸块。在实施例中，堆叠管芯308是堆叠的存储器管芯。例如，堆叠的存储器管芯308可以包括低功耗(LP)双倍数据速率(DDR)存储器模块，诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等存储器模块。
在一些实施例中，堆叠管芯308和接合线310可以由模塑材料312密封。例如，可以使用压缩模塑将模塑材料312模塑在堆叠管芯308和接合线310上。在一些实施例中，模塑材料312是模塑料、聚合物、环氧树脂、氧化硅填充材料等或他们的组合。可以实施固化步骤以固化模塑材料312，其中，该固化可以是热固化、UV固化等或它们的组合。
在一些实施例中，堆叠管芯308和接合线310掩埋在模塑材料312中，并且在模塑材料312的固化之后，实施诸如研磨的平坦化步骤以去除模塑材料312的过量部分并且为第二封装件300提供基本平坦的表面。
在形成第二封装件300之后，通过导电连接件314、接合焊盘304和通孔112将封装件300接合至第一封装件200。在一些实施例中，可以通过接合线310、接合焊盘303和304、通孔306、导电连接件314、通孔112和再分布结构160将堆叠的存储器管芯308连接至集成电路管芯114。
在一些实施例中，在接合导电连接件314和热连接件316之前，导电连接件314和热连接件316涂覆有助焊剂(未示出)，诸如免洗助焊剂。导电连接件314和热连接件316可以浸入助焊剂中，或可以将助焊剂喷射到导电连接件314和热连接件316上。在另一实施例中，可以将助焊剂施加至通孔112的暴露表面。
在一些实施例中，导电连接件314和热连接件316在它们回流之前可以具有在其上形成的环氧助焊剂(未示出)，在上部封装件300附接至下部封装件之后，剩余环氧助焊剂的至少一些环氧部分。该剩余的环氧部分可以用作底部填充物以减小应力并且保护由回流导电连接件314和热连接件316产生的接头。在一些实施例中，可以在上部封装件300和下部封装件之间形成围绕导电连接件314和热连接件316的底部填充物(未在图10中示出并且见图11中的底部填充物320)。底部填充物320可以是任何可接受的材料，诸如聚合物、环氧树脂、模塑底部填充物等。底部填充物320可以在上部封装件300附接之后通过毛细管流动工艺形成，或者可以在上部封装件300附接之前通过合适的沉积方法形成。
上部封装件300和下部封装件之间的接合可以是焊料接合或直接金属至金属(诸如铜至铜或锡至锡)接合。在实施例中，上部封装件300通过回流工艺接合至下部封装件。在该回流工艺期间，导电连接件314与接合焊盘304和通孔112接触以将上部封装件300物理和电连接至下部封装件。此外，在回流工艺期间，热连接件316与热焊盘305(如果存在)和热焊盘182接触以将集成电路管芯114和热焊盘182、热连接件316和热焊盘305物理和热连接。在接合工艺之后，可以在通孔112和导电连接件314以及热焊盘182和热连接件316之间的界面处形成金属间化合物(IMC)(未示出)。此外，也可以在导电连接件314和接合焊盘304以及热连接件316和热焊盘305之间的界面处形成IMC(未示出)。
在图11中，将下部封装件切割成多个下部封装件200。可以通过沿着例如邻近的区域600和602之间的划线区域锯切来实施切割工艺。在一些实施例中，切割工艺包括锯切、激光切割、蚀刻等。切割工艺将第一封装区域600与第二封装区域602分隔开。图11示出了产生的分割封装件200，该封装件200可以由第一封装区域600或第二封装区域602的一个形成。封装件200页可以称为集成扇出(InFO)封装件200。
图12示出了包括封装件200(可以称为第一封装件200)、封装件300(可以称为第二封装件300)和衬底400的半导体封装件500。
半导体封装件500包括被安装至衬底400的封装件200和300。衬底400可以称为封装衬底400。封装件200使用导电连接件166安装至封装衬底400。
封装衬底400可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中，也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷砷化镓、磷化镓铟、这些的组合等的化合物材料。此外，封装衬底400可以是SOI衬底。通常，SOI衬底包括诸如外延硅、锗、硅锗、SOI、SGOI或它们的组合的半导体材料层。在一个可选实施例中，封装衬底400基于诸如玻璃纤维增强树脂芯的绝缘芯。核心材料的一个实例是诸如FR4的玻璃纤维树脂。核心材料的替代物包括双马来酰亚胺-三嗪(BT)树脂或者其他PCB材料或薄膜。诸如ABF或其他层压材料的积聚膜可以用于封装衬底400。
封装衬底400可以包括有源和无源器件(未在图12中示出)。本领域中普通技术人员将意识到，可以使用诸如晶体管、电容器、电阻器、这些的组合等的多种器件来产生用于半导体封装件500的结构和功能需求的设计。可以使用任何合适的方法形成器件。
封装衬底400也可以包括金属化层和通孔(未示出)以及位于金属化层和通孔上方的接合焊盘402。金属化层可以形成在有源和无源器件上方并且设计为连接各个器件以形成功能电路。金属化层可以由电介质(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，其中，通孔互连导电材料层，并且金属化层可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在一些实施例中，封装衬底400基本无有源和无源器件。
在一些实施例中，可以回流导电连接件166以将封装件200附接至接合焊盘402。导电连接件166将衬底400(包括衬底400中的金属化层)电连接和/或物理连接至第一封装件200。
在一些实施例中，导电连接件166在它们回流之前可以具有在其上形成的环氧助焊剂(未示出)，在封装件200附接至衬底400之后，剩余环氧助焊剂的至少一些环氧部分。该剩余的环氧部分可以用作底部填充物以减小应力并且保护由回流导电连接件166产生的接头。在一些实施例中，可以在第一封装件200和衬底之间形成围绕导电连接件166的底部填充物(未示出)。底部填充物可以在封装件200附接之后通过毛细管流动工艺形成，或者可以在封装件200附接之前通过合适的沉积方法形成。
图13A和图13B示出了根据一些实施例的另一封装结构的截面图和平面图。图13A和图13B中的实施例与图1至图12中示出的实施例类似，除了该实施例包括位于封装件200和300之间的无导电连接件314的区330之外。此处不再重复关于该实施例与先前描述的实施例类似的那些的细节。
在该实施例中，位于封装件200和300之间的区330是无导电连接件314的。如图13B的平面图示出的，区330位于封装件300的一个或多个管芯308的覆盖区308内。这有助于在操作期间减小管芯308的温度，因为它们没有接收许多从封装件200的管芯114消散的热量。在平面图中，该区330可以位于封装件的中心区域中。在一些实施例中，在平面图中，区330位于封装件的外围区域，并且在一些实施例中，该区330位于中心区域和外围区域。通过去除一个或多个管芯308的覆盖区308内的一些导电连接件314，可以在操作期间减小管芯308的温度。
该实施例的无导电连接件314的区330可以包括在本发明的其他公开的实施例的封装件内。
图14示出了根据一些实施例的封装结构的截面图。图14中的实施例与图1至图12中示出的实施例类似，除了该实施例包括位于集成电路管芯114的衬底118中的通孔702之外。此处不再重复关于该实施例与先前描述的实施例类似的那些的细节。
在该实施例中，集成电路管芯114可以具有形成在衬底118中的一个或多个通孔702以帮助消散来自集成电路管芯内的器件的热量。例如，通孔702可以热连接至集成电路管芯114中的晶体管以允许更容易地从集成电路管芯114去除由晶体管产生的热量。通孔702可以进一步改进本发明的其他实施例的散热。热焊盘182可以物理连接至通孔702以帮助消散来自集成电路管芯114内的器件的热量。在一些实施例中，通孔702可以形成为部分地穿过集成电路管芯114的衬底118，并且在一些实施例中，通孔702形成为基本穿过集成电路管芯114的衬底118。
可以在集成电路管芯114附接至载体(例如，见图2)之前，在集成电路管芯114中形成通孔702。可以通过在集成电路管芯114的衬底118中形成开口并且用导电材料填充开口来形成通孔702。可以通过可接受的光刻和蚀刻技术形成开口。在形成开口之后，在开口中形成诸如扩散阻挡层、粘合层等的衬垫和导电材料。该衬垫可以包括钛、氮化钛、钽、氮化钽等。导电材料可以是铜、铜合金、银、金、钨、铝、镍、钴等。可以实施诸如化学机械抛光工艺(CMP)的平坦化工艺以从衬底118的表面去除过量的材料。剩余的衬垫和导电材料形成开口中的通孔702。
之后，热焊盘182形成在集成电路管芯114的衬底118的背侧上并且物理接触通孔702。热焊盘182可以如以上在先前实施例中所描述的那样形成，并且此处不再重复描述。
该实施例的通孔702可以包括在本发明的其他公开的实施例的管芯和伪管芯内。
图15至图18示出了根据一些实施例的用于第三封装结构的工艺期间的中间步骤的截面图。图15至图18中的实施例与图1至图12中示出的实施例类似，除了在该实施例中，在集成电路管芯114附接至载体衬底100之前，在集成电路管芯114的衬底118的背侧上形成热焊盘712之外。此处不再重复关于该实施例与先前描述的实施例类似的那些的细节。
图15示出了如上述图2的工艺的等效中间阶段，并且此处不再重复描述。在图15中，热焊盘712形成为集成电路管芯114的形成工艺的一部分。例如，在集成电路管芯114的衬底118的背侧上方形成粘合剂116之前，可以形成与集成电路管芯114的背侧再分布结构类似的热焊盘712。
在集成电路管芯114的衬底118的背侧表面上形成热焊盘712。热焊盘712不是用于电连接集成电路管芯114或封装结构的器件或金属化图案，而是用于消散来自集成电路管芯和/或封装结构的热量。在一些实施例中，热焊盘712没有连接至集成电路管芯114中的散热路径，而在一些实施例中，热焊盘182连接至集成电路管芯114中的散热路径(例如，见图12)。
热焊盘712也用于物理和热连接至连接件316(例如，见图18)并且可以称为UBM712。在示出的实施例中，在集成电路管芯114的衬底118的背侧上形成热焊盘712。作为形成热焊盘712的实例，在衬底118的背侧上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于热焊盘712。该图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中并且在晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成热焊盘712。在实施例中，在不同地形成热焊盘712的情况下，可以使用更多的光刻胶和图案化步骤。
图16示出了对图15的结构的进一步处理。这两个图之间的工艺与以上参照图3至图6示出和描述的类似，其中，图6是图16的等效中间阶段并且此处不再重复描述。
在图17中，去除粘合剂116以暴露热焊盘172和集成电路管芯114的背侧，例如，集成电路管芯114的衬底118的背侧。可以通过任何合适的工艺去除粘合剂116，诸如剥落粘合剂116，对粘合剂层116投射诸如激光或UV光的光，使得粘合剂层116在光的热量下分解，蚀刻粘合剂116等。
粘合剂116的去除在集成电路管芯114的背侧上方形成凹槽714。凹槽714具有从密封剂130的顶面至相应的集成电路管芯114的衬底118的暴露表面测量的深度D2。在一些实施例中，凹槽714的深度D2在从约5μm至约30μm的范围内。
图18示出了对图17的结构的进一步处理。这两个图之间的工艺与以上参照图9至图12示出和描述的工艺类似，其中，图12是图18的等效制造阶段并且此处不再重复描述。
图19至图21示出了根据一些实施例的用于另一封装结构的工艺期间的中间步骤的截面图。图19至图21中的实施例与图1至图12中示出的实施例类似，除了在该实施例中，集成电路管芯114附接至伪管芯，其中，热焊盘808形成在伪管芯的背侧上。此处不再重复关于该实施例与先前描述的实施例类似的那些的细节。
图19示出了如上述图2的工艺的等效中间阶段，并且此处不再重复描述。在图19中，伪管芯802通过粘合剂804粘合至释放层102，并且集成电路管芯114通过粘合剂806粘合至伪管芯802。在一些实施例中，伪管芯802由刚性材料形成，该刚性材料的杨氏模量等于或大于硅的杨氏模量(约165GPa至约179GPa)。因此，伪管芯802的杨氏模量等于或大于约165GPa。
在被粘合至释放层102之前，可以根据适用于伪管芯802的制造工艺处理伪管芯802。例如，可以通过准备和切割伪晶圆来形成伪管芯802。伪晶圆可以是半导体晶圆，诸如硅晶圆。在一些实施例中，伪晶圆可以是金属晶圆。例如，可以在研磨工艺中减薄伪晶圆。产生的伪晶圆的厚度足够大，使得伪晶圆可以为上面的结构提供足够的机械支撑，该上面的结构在随后的步骤中构建。
伪管芯802可以具有良好的热导率。伪管芯802的热导率可以接近于(例如，大于90％)上面的集成电路管芯114中的半导体衬底(诸如硅衬底)的热导率。例如，硅具有等于约148W/(m*K)的热导率，并且因此伪管芯802的热导率可以大于约135W/(m*K)或更高。由于伪管芯802具有高的热导率，因此可以改进产生的结构中的散热。
根据本发明的实施例，伪管芯802由金属或金属合金、半导体材料或介电材料形成。例如，根据一些实施例，当包括金属时，伪管芯802可以由铜、铝、镍等形成，并且因此是金属膜/板。当由半导体材料形成时，伪管芯802可以是切割的硅晶圆，其可以是在其上形成有源器件集成电路管芯114的相同类型的晶圆。当由介电材料形成时，伪管芯802可以由陶瓷形成。此外，伪管芯802的材料可以是均质的。例如，每个伪管芯802的整个均可以由包括相同元素的相同材料形成，并且元素的原子百分比在整个伪管芯802中可以是均匀的。根据一些示例性实施例，伪管芯802由硅形成，其中，p型或n型杂质掺杂在伪管芯802中。根据可选实施例，没有p型或n型杂质掺杂在伪管芯802中。
在图19中，集成电路管芯114通过粘合剂806接合至伪管芯802。在一些实施例中，粘合剂806是与热焊盘712以类似的方式形成的导电层(在下文中可以称为导电层806)，除了导电层806可以形成为穿过集成电路管芯114的整个背侧。
导电层806不是用于电连接集成电路管芯114或封装结构中的器件或金属化图案，而是用于消散来自集成电路管芯114和/或封装结构的热量。在一些实施例中，导电层806可以称为热层806，该热层806用于将来自集成电路管芯114的热量消散至伪管芯802。在一些实施例中，导电层806没有连接至集成电路管芯114中的散热路径，而在一些实施例中，热层806通过通孔(例如，见图14)连接至集成电路管芯114中的散热路径。
热层806也用于热连接至伪管芯802。在示出的实施例中，在集成电路管芯114的衬底118的背侧上形成热层806。作为形成热层806的实例，在衬底118的背侧上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。晶种层和导电材料形成热层806。
图20示出了对图19的结构的进一步处理。这两个图之间的工艺与以上参照图3至图8示出和描述的工艺类似，其中，图8是图20的等效中间阶段并且此处不再重复描述。
在图20中，在伪管芯802的背侧上形成热焊盘808。热焊盘808具有与用于形成如图8的热焊盘182类似的材料和方法并且此处不再重复描述。
图21示出了对图20的结构的进一步处理。这两个图之间的工艺与以上参照图8至图12示出和描述的工艺类似，其中，图12是图21的等效中间阶段并且此处不再重复描述。
该实施例的伪管芯802可以包括在本发明的其他公开的实施例的封装件内。
图22是图25示出了根据一些实施例的用于另一封装结构的工艺期间的中间步骤的截面图。图22至图25中的实施例与图1至图12示出的实施例类似，除了在该实施例中，集成电路管芯114具有背侧再分布结构。此处不再重复关于该实施例与先前描述的实施例类似的那些的细节。
图22示出了如上述图7的工艺的等效中间阶段，并且此处不再重复描述。在形成晶种层902之前，位于集成电路管芯114的衬底118的暴露表面上方的凹槽具有从密封剂130的顶面至相应的集成电路管芯114的衬底118的暴露表面测量的深度D3。在一些实施例中，凹槽的深度D3在从约5μm至约30μm的范围内。
在图22中，在图7的结构的集成电路管芯114的衬底118的暴露表面上形成晶种层902。在一些实施例中，晶种层902是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层902包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层902。
在图23和图24中，形成背侧再分布结构920。背侧再分布结构920包括介电层904、908、912和金属化图案906、910和914。
可以通过在晶种层902上沉积介电层904开始背侧再分布结构920的形成。在一些实施例中，介电层904由聚合物形成，该聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其他实施例中，介电层904由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层904。
下一步，之后，图案化介电层904。图案化形成暴露晶种层902的部分的开口。可以通过可接受的工艺图案化，可接受的工艺诸如当介电层904是感光材料时，将介电层904暴露于光或者通过使用例如各向异性蚀刻的蚀刻。如果介电层904是感光材料，则在曝光之后，可以显影介电层904。
下一步，在介电层904中形成通孔906。作为形成通孔906的实例，在介电层904的开口中并且在晶种层902的暴露部分上形成导电材料。可以通过诸如电镀、化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。晶种层的剩余部分和导电材料形成金属化图案138和通孔。在开口中形成穿过介电层132至例如通孔112和/或管芯互连件126的通孔。可以实施诸如CMP的平坦化工艺以从介电层904的表面去除过量的导电材料。剩余的导电材料形成通孔906。在CMP之后，通孔906、介电层904、密封剂130和通孔112的表面齐平。
通孔906不是用于电连接集成电路管芯114或封装结构中的器件或金属化图案，而是用于消散来自集成电路管芯114和/或封装结构的热量。在一些实施例中，通孔906可以称为热通孔906，热通孔906用于消散来自集成电路管芯114的热量。在一些实施例中，热通孔906没有连接至集成电路管芯114中的散热路径，而在一些实施例中，热通孔906连接至集成电路管芯114的散热路径(例如，见图14)。热通孔906也用于热连接至背侧再分布结构920(见图24)中的金属化图案。如图所示，热通孔具有从通孔902的顶面至通孔的底面的逐渐变窄的侧壁。
在图24中，在密封剂130、通孔112、介电层904和热通孔906上形成介电层908。在一些实施例中，介电层908由聚合物形成，该聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其他实施例中，介电层908由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG等形成。可以通过旋涂、层压、CVD等或它们的组合形成介电层908。
下一步，之后，图案化介电层908。图案化形成暴露通孔112和热通孔906的部分的开口。可以通过可接受的工艺图案化，可接受的工艺诸如当介电层908是感光材料时，将介电层908暴露于光或者通过使用例如各向异性蚀刻的蚀刻。如果介电层908是感光材料，则在曝光之后，可以显影介电层908。
下一步，在介电层908上形成具有通孔的金属化图案910。作为形成金属化图案910的实例，在介电层908上方并且在穿过介电层908的开口中形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案910。该图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中并且在晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案910和通孔。在开口中形成穿过介电层908至例如通孔112和/或热通孔906的通孔。
在金属化图案和通孔910的形成之后，在金属化图案910和介电层908上沉积介电层912。在一些实施例中，介电层912由聚合物形成，该聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其他实施例中，介电层912由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG等形成。可以通过旋涂、层压、CVD等或他们的组合形成介电层912。
下一步，之后，图案化介电层912。图案化形成暴露金属化图案910的部分的开口。可以通过可接受的工艺图案化，可接受的工艺诸如当介电层912是感光材料时，将介电层912暴露于光或者通过使用例如各向异性蚀刻的蚀刻。如果介电层912是感光材料，则在曝光之后，可以显影介电层912。
背侧再分布结构920示出为实例。可以在背侧再分布结构920中形成更多或更少的介电层和金属化图案。如果形成更少的介电层和金属化图案，则可以省略上述步骤和工艺。如果形成更多的介电层和金属化图案，则可以重复上述步骤和工艺。本领域普通技术人员将容易理解哪些步骤和工艺将被省略或重复。
下一步，在背侧再分布结构920的外侧上形成焊盘914。焊盘914用于连接至导电连接件316和314(见图25)并且可以称为凸块下金属(UBM)914。在示出的实施例中，通过穿过介电层912至金属化图案910的开口来形成焊盘914。作为形成焊盘914的实例，在介电层912上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于焊盘914。该图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中并且在晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。之后，去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成焊盘914。在实施例中，在不同地形成焊盘914的情况下，可以使用更多的光刻胶和图案化步骤。
随后，背侧再分布结构920和焊盘914通过电连接件314将通孔112和封装件900电连接至随后接合的封装件300。
图25示出了对图24的结构的进一步处理。这两个图之间的工艺与以上参照图8至图12示出和描述的工艺类似，其中，图12是图25的等效中间阶段并且此处不再重复描述。
该实施例的背侧再分布结构920和热通孔906可以包括在本发明的其他公开的实施例的封装件内。
图26至图29示出了根据一些实施例的用于另一封装结构的工艺期间的中间步骤的截面图。图26至图29中的实施例与图22至图25中的实施例类似，除了在该实施例中，在形成通孔906之前，实施平坦化工艺以去除凹槽。此处不再重复关于该实施例与先前描述的实施例类似的那些的细节。
图26示出了如图7的工艺的等效中间阶段并且此处不再重复。在该实施例中，位于集成电路管芯114的衬底118的暴露表面上方的凹槽具有从密封剂130的顶面至相应的集成电路管芯114的衬底118的暴露表面测量的深度D4。在一些实施例中，凹槽的深度D4在从约5μm至约30μm的范围内。
在图27中，可以实施诸如CMP的平坦化工艺以使集成电路管芯114的衬底118、密封剂130和通孔112的表面齐平。也就是说，平坦化工艺去除凹槽。
在图28中，在集成电路管芯114的衬底、密封剂130和通孔112的平坦化的表面上方形成晶种层902、介电层904和通孔906。在先前的实施例中描述了这些结构的材料和形成并且不再此处重复。在该实施例中，一些通孔906电连接和物理连接至通孔112以将通孔112电连接至随后接合的封装件300。但是一些通孔906用作热通孔(直接位于集成电路管芯114的衬底118上面的通孔906)。
图29示出了对图28的结构的进一步处理。这两个图之间的工艺与以上参照图23至图25示出和描述的工艺类似，其中，图25是图29的工艺的等效阶段并且此处不再重复描述。在图29中，示出了与先前实施例的背侧再分布结构920类似的背侧再分布结构930并且此处不再重复。
该实施例的背侧再分布结构930和热通孔906可以包括在本发明的其他公开的实施例的封装件内。
图30至图35示出了根据一些实施例的用于另一封装结构的工艺期间的中间阶段的截面图。图30至图35中的实施例与图1至图12中示出的实施例类似，除了在该实施例中，在集成电路管芯114附接至载体之前，在载体上方形成背侧再分布结构。此处不再重复关于该实施例与先前描述的实施例类似的那些的细节。
图30示出了如以上图1描述的载体衬底100和位于载体衬底上方的释放层102并且此处不再重复描述。在图30中，在释放层102上方进一步形成介电层1001、金属化图案1004和1005、介电层1002和通孔112。
在释放层102上形成介电层1001。介电层1001的底面可以与释放层102的顶面接触。在一些实施例中，介电层1001由聚合物形成，该聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其他实施例中，介电层1001由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG等形成。可以通过诸如旋涂、CVD、层压等或它们的组合的任何可接受的沉积工艺形成介电层1001。
在介电层1001上形成金属化图案1004和1005。作为形成金属化图案1004和1005的实例，在介电层1001上方形成晶种层(未示出)。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。之后，在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案1004和1005。该图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中并且在晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案1004和1005。
在金属化图案1004和1005以及介电层1001上形成介电层1002。在一些实施例中，介电层1002由聚合物形成，该聚合物可以是可以使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的感光材料。在其他实施例中，介电层1002由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG等形成。可以通过诸如旋涂、层压、CVD等或他们的组合形成介电层1002。
介电层1001和1002以及金属化图案1004和1005可以称为背侧再分布结构。如图所示，背侧再分布结构包括两个介电层1001和1002以及一个金属化图案1004。在其他实施例中，背侧再分布结构可以包括任何数量的介电层、金属化图案和通孔。可以通过重复用于形成金属化图案1004和介电层1002的工艺在背侧再分布结构中形成一个或多个额外的金属化图案和介电层。可以在通过在下面的介电层的开口中形成晶种层和导电材料在金属化图案的形成期间形成通孔。因此，该通孔可以互连和电连接各个金属化图案。
图案化介电层1002以形成暴露金属化图案1004和1005的部分的开口1006。可以通过可接受的工艺图案化，可接受的工艺诸如当介电层1002是感光材料时，将介电层1002暴露于光或者通过使用例如各向异性蚀刻的蚀刻。如图30示出的，图案化介电层1002以暴露一些金属化图案1004和1005，但不是全部的金属化图案1004和1005。例如，开口1006暴露将位于随后附接的集成电路管芯114之下的一些金属化图案1005，并且也将暴露其上将形成通孔112的其他金属化图案1004，而另外的金属化图案1004保持由介电层1002覆盖。
进一步在图30中，形成通孔112。作为形成通孔112的实例，在背侧再分布结构(例如，介电层1002和金属化图案1004的暴露部分)上方形成晶种层。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成并且图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶的图案对应于通孔。该图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中并且在晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。去除光刻胶和其上未形成导电材料的晶种层的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，则诸如通过使用可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成通孔112。
在图31中，通过层1010将集成电路管芯114粘合至背侧再分布结构。先前描述了集成电路管芯114并且此处不再重复描述。如图31示出的，在第一封装区域600和第二封装区域602的每个中粘合一个集成电路管芯114，并且在其他实施例中，可以在每个区域中粘合更多集成电路管芯114。例如，在实施例中，可以在每个区域中粘合两个集成电路管芯114或四个集成电路管芯114。
层1010位于集成电路管芯114的背侧上并且将集成电路管芯114粘合至背侧再分布结构。层1010可以是高k DAF、导电膏(诸如银膏)等。如图31示出的，层1010在集成电路管芯114下面的一些开口1006中向下延伸，以接触那些开口1006的暴露的金属化图案1005。可以将层1010施加至集成电路管芯114的背面，诸如施加至相应的半导体晶圆的背面，或者可以施加在载体衬底100的表面上方。集成电路管芯114可以被切割(诸如通过锯切或分割)并且使用例如拾取放置工具通过层1010粘合至背侧再分布结构。
层1010(例如，高k DAF或导电膏)不是用于电连接集成电路管芯114或封装结构中的器件或金属化图案，而是用于消散来自集成电路管芯114和/或封装结构的热量。在一些实施例中，层1010可以称为热膏1010，其用于消散来自集成电路管芯114的热量。在一些实施例中，热膏1010没有连接至集成电路管芯114中的散热路径，而在一些实施例中，热膏1010连接至集成电路管芯114中的散热路径(例如，见图14)。热膏1010用于将集成电路管芯114热连接至背侧再分布结构中的金属化图案1005，之后，该金属化图案热连接至连接件316(例如，见图35)。因此，金属化图案1005在下文中可以称为热图案1005。
图32示出了对图31的结构的进一步处理。这两个图之间的工艺与以上参照图3至图6示出和描述的工艺类似，其中，图6是与图32类似的阶段并且此处不再重复描述。在图32中，去除载体衬底100和释放层102并且将该结构放置在胶带190上。在去除释放层102之后，暴露背侧再分布结构的背侧介电层1001。
在图33中，在介电层1001中形成一组开口1012以暴露金属化图案1004和热图案1005的部分。激光钻孔工艺、蚀刻工艺等或它们的组合可以形成开口1012。开口1012暴露连接至通孔112的金属化图案1004以及连接至热膏1010的热图案1005。
在图34中，在开口1012中的暴露的金属化图案1004和热图案1005的每个上形成含焊料层1014，含焊料层1014可以是焊料层(有时称为预焊层)、焊膏等。在一些实施例中，含焊料层1014可以完全地填充或过填充开口1012，而在其他实施例中，含焊料层1014可以仅部分地填充开口1012。在沉积含焊料层1014之后，可以在将导电连接件314和316接合至含焊料层1014和封装结构1050(例如，见图35)之前，实施回流工艺。在一些实施例中，可以省略含焊料层1014。
图35示出了对图34的结构的进一步处理。这两个图之间的工艺与以上参照图9至图12示出和描述的工艺类似，其中，图12是与图35类似的工艺阶段并且此处不再重复描述。
在将导电连接件314和316接合至含焊料层1014和封装结构1050的回流工艺之后，含焊料层1014、连接件314和316可能会相互混合，而不会如图35所示的清晰可见地为单独的结构。
导电连接件314用于将封装结构1050电连接至封装结构300。与热膏1010类似，导电连接件316不是用于电连接集成电路管芯114或封装结构中的器件或金属化图案，而是用于消散来自集成电路管芯114和/或封装结构的热量。因此，导电连接件316可以称为热连接件316。通过利用热膏1010、热图案1005和热连接件316，与不包括热膏和热连接件的封装结构相比，该封装结构的热阻(℃/瓦)可以改进高达约8％。
该实施例的层1010和金属化图案1004可以包括在本发明的其他公开的实施例的封装件内。
通过包括位于半导体管芯的背侧上的热元件，可以改进封装结构的热性能。热元件用于消散来自封装结构的热量。在一些实施例中，热元件没有连接至散热路径，而在一些实施例中，热元件连接至半导体管芯中的散热路径(例如，见图14)。例如，热元件可以连接至通孔(热耦合/连接至半导体管芯中的一个或多个晶体管)以消散由晶体管产生的热量。与不包括位于半导体管芯的背侧上的热元件相比，本发明的实施例可以改进封装结构的热阻(℃/瓦)高达约8％。
在实施例中，封装件包括第一封装结构和第二封装结构，第一封装结构包括：具有有源侧和背侧的第一集成电路管芯，有源侧包括管芯连接件；邻近第一集成电路管芯的第一通孔；横向密封第一集成电路管芯和第一通孔的密封剂；位于第一集成电路管芯的管芯连接件和第一通孔上并且电连接至第一集成电路管芯的管芯连接件和第一通孔的第一再分布结构；和位于第一集成电路管芯的背侧上的热元件；以及第二封装结构通过第一组导电连接件接合至第一通孔和热元件。在实施例中，热元件与第一集成电路管芯内的集成电路电隔离。在实施例中，第一集成电路管芯的背侧从密封剂的表面凹进，热元件位于凹槽内。在实施例中，热元件具有垂直于第一集成电路管芯的背侧的侧壁。在实施例中，热元件具有从热元件的顶面至底面的逐渐变窄的侧壁。在实施例中，热元件具有从热元件的顶面至底面的变宽的侧壁。在实施例中，热元件包括导电膏和金属化图案。在实施例中，封装件还包括围绕第一组导电连接件的底部填充物，该底部填充物位于第一封装结构和第二封装结构之间。在实施例中，底部填充物接触热元件。在实施例中，第一封装结构和第二封装结构之间的中心部分无导电连接件。在实施例中，该封装件还包括第一集成电路管芯的背侧内的通孔，热元件热连接至通孔。在实施例中，第一封装结构还包括电连接至第一通孔的第二再分布结构，第二再分布结构位于第一集成电路管芯和第二封装结构之间。在实施例中，该封装件还包括位于第一集成电路管芯的背侧上的伪管芯，热元件位于伪管芯上。
在实施例中，方法包括形成第一封装件，包括在载体衬底上方形成电连接件；使用粘合层将第一管芯附接至载体衬底，电连接件从第一管芯的背侧延伸至第一管芯的有源侧，有源侧与背侧相对，电连接件邻近第一管芯；用模塑料密封第一管芯和电连接件；在第一管芯的有源侧、模塑料和电连接件上面形成第一再分布结构；去除载体衬底以暴露电连接件的第一端和粘合层；去除粘合层以暴露第一管芯的背侧；并且在第一管芯的暴露的背侧上形成热元件；在热元件和电连接件的第一端上方形成第一组导电连接件；并且使用第一组导电连接件将第二封装件接合至第一封装件，第二封装件接近第一管芯的背侧。在实施例中，该方法还包括在第一管芯的背侧上的热元件上方以及电连接件的第一端上方形成第二再分布结构，第二再分布结构电连接至电连接件，第二封装件接合至第二再分布结构。在实施例中，热元件热连接至第二再分布结构。在实施例中，该方法还包括平坦化模塑料和第一管芯的背侧以具有齐平的表面，热元件位于第一管芯的背侧和模塑料的平坦化表面上。在实施例中，在第一管芯的暴露的背侧上形成热元件包括：在第一管芯的暴露的背侧上形成晶种层；在晶种层上形成介电层；图案化穿过介电层的孔以暴露晶种层的部分；并且在孔中形成导电材料，导电材料形成热元件。
在实施例中，方法包括形成第一封装件，包括：在载体衬底上方形成电连接件；使用粘合层将第一管芯附接至载体衬底，第一管芯包括位于第一管芯的背侧上的粘合层内的导电焊盘，电连接件从第一管芯的背侧延伸至第一管芯的有源侧，有源侧与背侧相对，电连接件邻近第一管芯；用模塑料密封第一管芯和电连接件；在第一管芯的有源侧、模塑料和电连接件上面形成再分布结构；去除载体衬底以暴露电连接件的第一端和粘合层；去除粘合层以暴露导电焊盘和第一管芯的背侧；并且在导电焊盘和电连接件的第一端上形成第一组导电连接件；以及使用第一组导电连接件将第二封装件接合至第一封装件，第二封装件邻近第一管芯的背侧。在实施例中，该方法还包括在第一管芯的背侧上的导电焊盘上方和电连接件的第一端上方形成第二再分布结构，第二再分布结构电连接至电连接件，第二封装件接合至第二再分布结构。
在实施例中，该方法包括形成第一封装件，包括：在载体衬底上方形成第一金属化图案和第二金属化图案；在第一和第二金属化图案的第一表面上形成和图案化介电层，图案化的介电层暴露第一和第二金属化图案的第一表面的部分；在介电层上方形成电连接至第一金属化图案的电连接件；使用第一粘合层将第一管芯附接至介电层，第一粘合层接触第二金属化图案的暴露的第一表面；用模塑料密封第一管芯和电连接件；在第一管芯的有源侧、模塑料和电连接件上面形成第一再分布结构；去除载体衬底，其中，在去除之后，暴露第一和第二金属化图案的第二表面；在第一和第二金属化图案的第二表面上方形成第一组导电连接件，第一组导电连接件的至少一个导电连接件电连接至电连接件；以及使用第一组导电连接件将第二封装件接合至第一封装件，第二封装件接近第一管芯的背侧，背侧与有源侧相对。在实施例中，第一粘合层是导电膏。在实施例中，该方法还包括在第一再分布结构上形成第二组导电连接件；以及使用第二组导电连接件将第一封装件接合至衬底。在实施例中，该方法还包括在第一管芯的背侧中形成通孔，该通孔接触第一粘合层。
在实施例中，封装件包括第一封装结构和第二封装结构，第一封装结构包括：具有前侧和背侧的伪管芯；具有前侧和背侧的第一集成电路管芯，前侧包括管芯连接件；位于第一集成电路管芯的背侧和伪管芯的前侧之间并且接触第一集成电路管芯的背侧和伪管芯的前侧的第一附接层；邻近第一集成电路管芯、第一附接层和伪管芯的第一电连接件；横向密封第一集成电路管芯、伪管芯、第一附接层和第一电连接件的密封剂；位于第一集成电路管芯的管芯连接件和第一电连接件上并且电连接至管芯连接件和第一电连接件的第一再分布结构；和位于伪管芯的背侧上的热元件；以及第二封装结构通过第一组导电连接件接合至第一电连接件和热元件。在实施例中，第一附接层是包括金属的导电层。在实施例中，其中，伪管芯由金属制成。在实施例中，伪管芯的背侧从密封剂的表面凹进，热元件位于凹槽内。
在实施例中，结构包括第一封装结构，第一封装结构包括：包括金属化图案和介电层的第一再分布结构；位于第一再分布结构上方并且电连接至第一再分布结构的第一管芯，第一管芯的有源侧包括面向第一再分布结构的管芯连接件；邻近第一管芯的第一通孔，第一通孔电连接至第一再分布结构；横向密封第一管芯和通孔的密封剂；位于第一管芯的背侧上方的附接层，第一管芯的背侧与有源侧相对，附接层接触密封剂；和位于附接层和第一通孔上方的第二再分布结构，第二再分布结构包括金属化图案和介电层，第二再分布结构电连接至第一通孔；以及第二封装结构使用第一组导电连接件接合至第二再分布结构的金属化图案。在实施例中，附接层是导电膏。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (18)

1.一种封装件，包括：
第一封装结构，包括：
第一集成电路管芯，具有有源侧和背侧，所述有源侧包括管芯连接件；
第一通孔，邻近所述第一集成电路管芯；
密封剂，横向密封所述第一集成电路管芯和所述第一通孔；
第一再分布结构，位于所述第一集成电路管芯的所述管芯连接件和所述第一通孔上并且电连接至所述第一集成电路管芯的所述管芯连接件和所述第一通孔；和
热元件，位于所述第一集成电路管芯的背侧上，其中，所述第一集成电路管芯的背侧从所述密封剂的表面凹进，所述热元件位于凹槽内；以及
第二封装结构，通过第一组导电连接件接合至所述第一通孔和所述热元件，
其中，所述第一封装结构的所述热元件和所述第二封装结构之间的中心区域无导电连接件，而所述第一封装结构的所述热元件和所述第二封装结构之间的外围区域设置有导电连接件，所述外围区域围绕所述中心区域。
2.根据权利要求1所述的封装件，其中，所述热元件与所述第一集成电路管芯内的集成电路电隔离。
3.根据权利要求1所述的封装件，其中，所述热元件具有垂直于所述第一集成电路管芯的背侧的侧壁。
4.根据权利要求1所述的封装件，其中，所述热元件具有从所述热元件的顶面至底面的逐渐变窄的侧壁。
5.根据权利要求1所述的封装件，其中，所述热元件具有从热元件的顶面至底面的变宽的侧壁。
6.根据权利要求1所述的封装件，其中，所述热元件包括导电膏和金属化图案。
7.根据权利要求1所述的封装件，还包括：
底部填充物，围绕所述第一组导电连接件，所述底部填充物位于所述第一封装结构和所述第二封装结构之间。
8.根据权利要求7所述的封装件，其中，所述底部填充物接触所述热元件。
9.根据权利要求1所述的封装件，其中，所述热元件的顶面低于所述第一通孔的顶面。
10.根据权利要求1所述的封装件，还包括：
通孔，位于所述第一集成电路管芯的背侧内，所述热元件热连接至所述通孔。
11.根据权利要求1所述的封装件，其中，所述第一封装结构还包括：
第二再分布结构，位于所述第一通孔上方并且电连接至所述第一通孔，所述第二再分布结构位于所述第一集成电路管芯和所述第二封装结构之间。
12.根据权利要求1所述的封装件，还包括：
伪管芯，位于所述第一集成电路管芯的背侧上，所述热元件位于所述伪管芯上。
13.一种形成封装件的方法，包括：
形成第一封装件，包括：
在载体衬底上方形成电连接件；
使用粘合层将第一管芯附接至所述载体衬底，所述电连接件从所述第一管芯的背侧延伸至所述第一管芯的有源侧，所述有源侧与所述背侧相对，所述电连接件邻近所述第一管芯；
用模塑料密封所述第一管芯和所述电连接件；
在所述第一管芯的有源侧、所述模塑料和所述电连接件上面形成第一再分布结构；
去除所述载体衬底以暴露所述电连接件的第一端和所述粘合层；
去除所述粘合层以暴露所述第一管芯的背侧；和
在所述第一管芯的暴露的背侧上形成热元件，其中，所述第一管芯的背侧从所述模塑料的表面凹进，所述热元件位于凹槽内；
在所述热元件和所述电连接件的第一端上方形成第一组导电连接件；以及
使用所述第一组导电连接件将第二封装件接合至所述第一封装件，所述第二封装件接近所述第一管芯的背侧，
其中，位于所述第一管芯的中心区域的所述热元件上方无导电连接件，而位于所述第一管芯的外围区域的所述热元件上方形成有导电连接件，所述外围区域围绕所述中心区域。
14.根据权利要求13所述的方法，还包括：
在所述第一管芯的背侧上的所述热元件上方以及所述电连接件的第一端上方形成第二再分布结构，所述第二再分布结构电连接至所述电连接件，所述第二封装件接合至所述第二再分布结构。
15.根据权利要求14所述的方法，其中，所述热元件热连接至所述第二再分布结构。
16.根据权利要求13所述的方法，其中，在所述第一管芯的所述暴露的背侧上形成所述热元件包括：
在所述第一管芯的所述暴露的背侧上形成晶种层；
在所述晶种层上形成介电层；
图案化穿过所述介电层的孔以暴露所述晶种层的部分；以及
在所述孔中形成导电材料，所述导电材料形成所述热元件。
17.一种形成封装件的方法，包括：
形成第一封装件，包括：
在载体衬底上方形成电连接件；
使用粘合层将第一管芯附接至所述载体衬底，所述第一管芯包括位于所述第一管芯的背侧上的所述粘合层内的导电焊盘，所述电连接件从所述第一管芯的背侧延伸至所述第一管芯的有源侧，所述有源侧与所述背侧相对，所述电连接件邻近所述第一管芯；
用模塑料密封所述第一管芯和所述电连接件；
在所述第一管芯的有源侧、所述模塑料和所述电连接件上面形成再分布结构；
去除所述载体衬底以暴露所述电连接件的第一端和所述粘合层；
去除所述粘合层以暴露所述导电焊盘和所述第一管芯的背侧，其中，所述第一管芯的背侧从所述模塑料的表面凹进，所述导电焊盘位于凹槽内；和
在所述导电焊盘和所述电连接件的第一端上形成第一组导电连接件；以及
使用所述第一组导电连接件将第二封装件接合至所述第一封装件，所述第二封装件邻近所述第一管芯的背侧，
其中，位于所述第一管芯的中心区域的所述导电焊盘上方无导电连接件，而位于所述第一管芯的外围区域的所述导电焊盘上方形成有导电连接件，所述外围区域围绕所述中心区域。
18.根据权利要求17所述的方法，还包括：
在所述第一管芯的背侧上的所述导电焊盘上方和所述电连接件的第一端上方形成第二再分布结构，所述第二再分布结构电连接至所述电连接件，所述第二封装件接合至所述第二再分布结构。
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