CN107665887B - 封装结构及其形成方法 - Google Patents
封装结构及其形成方法 Download PDFInfo
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- CN107665887B CN107665887B CN201710631058.XA CN201710631058A CN107665887B CN 107665887 B CN107665887 B CN 107665887B CN 201710631058 A CN201710631058 A CN 201710631058A CN 107665887 B CN107665887 B CN 107665887B
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Abstract
实施例是一种结构,包括:第一管芯;模塑料,至少横向封装第一管芯;第一再分布结构,包括在所述第一管芯和所述模塑料上方延伸的金属化图案;第一导电连接件,包括耦合至所述第一再分布结构的焊球和凸块底部金属化件;以及集成无源器件,通过微凸块接合点接合至所述第一再分布结构中的第一金属化图案,所述集成无源器件邻近所述第一导电连接件。本发明还提供了一种封装结构及其形成方法。
Description
技术领域
本发明的实施例一般地涉及半导体技术领域,更具体地,涉及封装结构及其形成方法。
背景技术
半导体工业由于各种电子部件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的不断改进而经历了快速发展。在大多数情况下,由最小部件尺寸的反复减小而产生集成密度的改进,从而允许将更多的部件集成在给定区域中。随着缩小电子器件的需求不断增长,更小且更多的半导体管芯的封装技术的需要已经出现。这样封装系统的示例是堆叠封装件(POP)技术。在POP器件中,顶部半导体封装件堆叠在底部半导体封装件的顶部上以提供更高等级的集成度和部件密度。POP技术通常能够在印刷电路板(PCB)上生产具有增强的功能性和非常小的占位面积的半导体器件。
发明内容
根据本发明的一方面,提供了一种封装结构,包括:第一管芯;模塑料,至少横向封装所述第一管芯;第一再分布结构,包括在所述第一管芯和所述模塑料上方延伸的金属化图案;第一导电连接件,包括耦合至所述第一再分布结构的焊球和凸块底部金属化件;以及集成无源器件,通过微凸块接合点接合至所述第一再分布结构中的第一金属化图案,所述集成无源器件邻近所述第一导电连接件。
根据本发明的另一方面,提供了一种用于形成封装结构的方法,包括:形成所述第一封装件包括:在载体衬底上方形成电连接件;将第一管芯附接至所述载体衬底,所述电连接件从所述第一管芯的第二面延伸至所述第一管芯的第一面,所述第二面与所述第一面相对,所述电连接件邻近所述第一管芯;通过模塑料封装所述第一管芯和所述电连接件;在所述第一管芯的第一面和所述模塑料上方形成再分布结构,所述再分布结构包括金属化图案;将包括凸块底部金属化件的第一导电连接件耦合至所述第一再分布结构的第一金属化图案;以及通过接合点将集成无源器件接合至所述再分布结构的第二金属化图案。
根据本发明的又一方面,提供了一种用于形成封装结构的方法,包括:形成邻近第一管芯的第一通孔,所述第一通孔从所述第一管芯的第二面延伸至所述第一管芯的第一面,所述第二面与所述第一面相对;通过模制材料封装所述第一通孔和所述第一管芯;在所述第一管芯的第一面、所述第一通孔、以及所述模制材料上方形成第一再分布结构,所述第一再分布结构包括多个金属化图案和多个介电层;形成位于所述第一再分布结构的第一介电层上方并且穿过所述第一再分布结构的第一介电层的第一凸块底部金属化层以接触所述第一再分布结构的第一金属化图案;以及通过接合点将集成无源器件接合至所述第一再分布结构的第二金属化图案,所述接合点延伸穿过所述第一再分布结构的所述第一介电层。
附图说明
当结合附图进行阅读时,通过以下详细描述更好地理解本发明的各个方面。应该注意,根据工业中的标准实践,各种部件没有必要按比例绘制。实际上,为了讨论清楚起见,各种部件的尺寸可以任意地增加或减小。
图1至图18、图20A、图20B和图23至图26示出了根据一些实施例的在形成封装结构的工艺期间的中间步骤的截面图。
图19A至图19D示出了根据一些实施例的钝化开口的截面图。
图21A和图21B示出了根据一些实施例的集成无源器件的截面图。
图22A至图22C示出了根据一些实施例的用于集成无源器件的底部填充方案的截面图。
具体实施方式
以下公开内容提供了用于实施本发明的不同部件的实施例或实例。以下描述部件和配置的具体实例以简化本发明。当然,这些仅是实例并且不是为了进行限定。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例,并且还可以包括附件部件形成在第一部件和第二部件之间,使得第一部件和第二部件不直接接触的实施例。另外,本发明可以在各个实例中重复参考数字和/或字母。该重复是为了简单和清楚的目的,并且其本身并未指出所讨论的各个实施例和/或配置之间的关系。
此外,为了易于描述,可以使用空间相对术语(诸如“在…下方”、“之下”、“下部”、“上方”、“上部”等)以描述图中所示一个元件或部件与另一个元件或部件的关系。除图中所示的定向之外,空间相对术语还包括使用或操作中设备的不同定向。装置可以以其他方式定向(旋转90度或处于其他定向),并且本文所使用的空间相对描述符可因此进行类似的解释。
本文中所述的实施例可以在上下文的环境中进行讨论,即,包括有集成无源器件(IPD设计)封装结构增大了系统性能并且放大了工艺窗口,以改善封装结构的可靠性和产量。封装结构可以包括集成输出或集成输入封装件并且可以包括一个或多个再分布层(RDL)。IPD组件可以接合至封装结构的一个或多个RDL。IPD组件可以接合至邻近导电接合点的一个或多个RDL,该导电接合点将两个封装件/衬底耦合并接合在一起。相邻导电接合点可以包括一个或多个RDL上的凸块底部金属化件(UBM)和耦合至UBM的焊料接合点。IPD组件可以接合至没有UBM的一个或多个RDL。IPD组件可以通过包括焊料层的微凸块接合点接合并电耦合至RDL的导电层中的一个。在一些实施例中,IPD组件可以包括电容器、电阻器、电感器等或它们的组合。
在一些实施例中,IPD组件包括额外的后端制程(BEOL)金属布线,以进一步提升系统性能。然而,通过额外的金属布线,IPD的高度可能出现板级焊料接合点产量的问题。因此,通过去除IPD组件接合点区域下方的UBM,IPD组件的总高度被减小并且工艺窗口增大。
激光钻或光刻工艺可以用于在钝化或聚合物层中形成开口,以暴露将接合IPD组件的RDL的导电层。另外,完全填充、部分填充或不填充IPD组件的底部填充物可以用于防止污染并改善可靠性。
此外,本发明的技术启示可应用于包括IPD组件的任何封装件结构。在阅读本发明时,本领域技术人员将容易想到,其他实施例预期其他应用,诸如不同封装类型或不同配置。应该注意,本文中所讨论的实施例没有必要示出结构中所存在的每一个组件或部件。例如,诸如当一个组件的论述足以传达实施例的各个方面时,可以从附图中省略多个组件。此外,与以特定顺序执行的方法一样,论述本文中所讨论的方法实施例;然而,可以以任何逻辑顺序执行其他方法实施例。
图1至18、20A、20B、以及23至26示出了在根据一些实施例形成封装件结构的工艺期间的中间步骤的截面图。图1示出了载体衬底100和形成在载体衬底100上的释放层102。分别示出了用于形成第一封装件和第二封装件的第一封装区域600和第二封装区域602。
载体衬底100可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底100可以为晶圆,使得多个封装件可以同时形成在载体衬底100上。释放层102可以由聚合物基材料形成,可以从随后步骤中形成的上覆结构去除释放层以及载体衬底100。在一些实施例中,释放层100是环氧树脂基热释放材料,当加热该释放层时丢失其粘合特性,诸如光热转换(LTHC)释放涂层。在其他实施例中,释放层102可以是紫外线(UV)胶,当曝光于UV光时,该释放层会丢失其粘合特性。释放层102可以分配为液体并且被固化,可以是层压在载体衬底100的层压膜或者可以是其他类似物。释放层102的顶面可以是齐平的并且可以具有高度共面性。
在图2中,形成介电层104和金属化图案106。如图2所示,介电层104形成在释放层102。介电层104的底面可以与释放层102的顶面接触。在一些实施例中,介电层104由聚合物形成,例如,聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等。在其他实施例中,介电层104由以下材料形成,诸如氮化硅的氮化物;诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG)等的氧化物。可以通过诸如旋涂、化学汽相沉积(CVD)、层压等可接受的沉积工艺或它们的组合来形成介电层104。
金属化图案106形成在介电层104上。作为形成金属化图案106的示例,晶种层(未示出)形成在介电层104上方。在一些实施例中,晶种层为金属层,该晶种层可以是单层或者由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如可以使用PVD等形成晶种层。然后,在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成,并且将其曝光于图案化的光。光刻胶的图案对应于金属化图案106。图案化形成穿过光刻胶的开口以暴露晶种层。导电材料形成在光刻胶的开口中以及晶种层的暴露部分上。可以通过诸如电镀或非电镀等的镀来形成导电材料。导电材料可以包括诸如铜、钛、钨、铝等的金属。然后,光刻胶和其上没有形成导电材料的部分晶种层被去除。通过使用诸如氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶,就通过诸如可接受的蚀刻工艺(诸如湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案106。
在图3中,介电层108形成在金属化图案106和介电层104上。在一些实施例中,介电层108由聚合物形成,该聚合物可以是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中,介电层108由诸如氮化硅的氮化物;诸如氧化硅、PSG、BSG、BPSG等的氧化物或者它们的组合形成。然后,介电层108被图案化为形成开口以包括金属化图案106的多部分。诸如通过将介电层108暴露于光的可接受的工艺(当介电层是光敏材料时)或者通过使用诸如各向异性蚀刻的蚀刻来进行图案化。
介电层104和108以及金属化层106可以被称为背面再分布结构110。如图所示,背面再分布结构110包括两个介电层104和108以及一个金属化图案110。在其他实施例中,背面再分布结构110可以包括任何数量的介电层、金属化层和通孔。可以通过重复形成金属化图案106和介电层108的工艺在背面再分布结构110中形成一个或多个附加金属化图案和介电层。可以通过在下面的介电层的开口中形成晶种层和金属化图案的导电材料在形成金属化图案期间形成通孔。因此,通孔可以互连并且电耦合各种金属化图案。
此外,在图3中,形成通孔112。作为形成通孔112的示例,晶种层形成在背面再分布结构110上方,诸如形成在如图所示的介电层108和金属化图案106的暴露部分上方。在一些实施例中,晶种层是金属层,该晶种层可以是单层或者包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如可以使用PVD等形成晶种层。可以在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成并且可以暴露于用于图案化的光。光刻胶的图案对应于通孔。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中以及晶种层的暴露部分中形成导电材料。可以通过诸如电镀或非电镀等的镀来形成导电材料。导电材料可以包括诸如铜、钛、钨、铝等的金属。光刻胶和其上没有形成导电材料的部分晶种层被去除。可以通过诸如使用氧等离子体等的可接受的灰化或者剥离工艺去除光刻胶。一旦去除光刻胶,就可以通过使用诸如湿蚀刻或干蚀刻的可接受的蚀刻工艺去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成通孔112。
在图4中,集成电路管芯114通过粘合剂116粘合至介电层108。如图4所示,两个集成电路管芯114粘合在第一封装区域600和第二封装区域602的每个区域中,并且在其他实施例中,更多或更少的集成电路管芯114可以粘合在每个区域中。集成电路管芯114可以是逻辑管芯(例如,中央处理单元、微控制器等)、存储器管芯(例如动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如,电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如,数字信号处理(DSP)管芯)、前端管芯(模拟前端(AFE)管芯)等或它们的组合。此外,在一些实施例中,集成电路管芯114可以为不同尺寸(例如,不同高度和/或表面区域),并且在其他实施例中,集成电路管芯114可以为相同尺寸(例如,相同的高度和/或表面区域)。
在粘合至介电层108之前,根据可应用的制造工艺处理集成电路管芯114以在集成电路管芯114中形成集成电路。例如,集成电路管芯114均包括诸如掺杂或非掺杂硅的半导体衬底118或者绝缘体上半导体(SOI)衬底的有源层。半导体衬底可以包括诸如锗的其他半导体材料;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金包括体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP;或它们的组合。还可以使用诸如多层或梯度衬底的其他衬底。诸如晶体管、二极管、电容器、电阻器等的器件可以形成在半导体衬底118中和/或上,并且通过互连结构120互连这些器件以形成集成电路,其中,例如通过半导体衬底118上的一个或多个介电层中的金属化图案来形成该互连结构。
集成电路管芯114进一步包括进行外部连接的焊盘122,诸如铝焊盘。焊盘122位于可以被称为集成电路管芯114的相应的有源侧上。钝化膜124位于集成电路管芯114上以及部分焊盘122上。开口穿过钝化膜124导到达焊盘122。诸如导电柱(例如,包括诸如铜的金属)的管芯连接件126位于穿过钝化层124的开口中并且机械和电耦合至相应的焊盘122。例如通过镀等形成管芯连接件126。管芯连接件126电耦合至集成电路管芯114的相应的集成电路。
介电材料128位于集成电路管芯114的有源侧上,诸如钝化膜124以及管芯连接件126上。介电材料128横向封装管芯连接件126,并且介电材料128与相应的集成电路管芯114横向相连(coterminous)。介电材料128可以是诸如PBO、聚酰亚胺、BCB等的聚合物;诸如氮化硅等的氮化物;诸如氧化硅、PSG、BSG、BPSG的氧化物等或它们的组合,并且例如可以通过旋涂、层压、CVD等来形成该介电材料。
粘合剂116位于集成电路管芯114的背面上并且将集成电路管芯114粘合至背面再分布结构110,诸如示图中的介电层108。粘合剂116可以是任何适当的粘合剂、环氧树脂、管芯附接膜等。粘合剂116可以应用于集成电路管芯114的背面,诸如应用于对应的半导体晶圆的背面或者可以应用于载体衬底100的表面。集成电路管芯114可以通过诸如通过锯切或切割进行分割,并且通过使用例如拾取和放置工具利用粘合剂116粘合至介电层108。
在图5中,密封剂130形成在各种部件上。密封剂130可以为模制化合物、环氧树脂等,并且通过压缩模制、转移模制等施加该密封剂。在固化之后,密封剂130可以经受研磨工艺以暴露通孔112和管芯连接件126。在研磨工艺之后,通孔112、管芯连接件126和密封剂130的顶面可以共面。在一些实施例中,例如,如果已经暴露通孔112和管芯连接件126,则可以省略研磨。
在图6至图16中,形成正面再分布结构160。如图16所示,正面再分布结构160包括介电层132、140、148和156和金属化图案138、146和154。
在图6中,介电层132沉积在密封剂130、通孔112和管芯连接件126。在一些实施例中,介电层132由聚合物形成,该聚合物可以是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中,介电层132由诸如氮化硅的氮化物;诸如氧化硅、PSG、BSG、BPSG等的氧化物形成。介电层132可以通过旋涂、层压、CVD等或它们的组合形成。
在图7中,然后图案化介电层132。图案化形成开口以暴露通孔112和管芯连接件126的部分。可以通过可接受的工艺来进行图案化,诸如当介电层132是光敏材料时通过将介电层131暴露于光或者通过使用各向异性蚀刻的蚀刻。如果介电层132是光敏材料,则介电层12可以在曝光以后被显影。
在图8中,具有通孔的金属化图案138形成在介电层132上。作为形成金属化图案138的示例,晶种层(未示出)形成在介电层132上方以及穿过介电层132的开口中。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如可以使用PVD等形成晶种层。然后在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成并且可以被暴露于用于图案化的光。光刻胶的图案对应于金属化图案138。图案化形成穿过光刻胶的开口以暴露晶种层。导电材料形成在光刻胶的开口中以及晶种层的暴露部分上。通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括诸如铜、钛、钨、铝等的金属。然后,光刻胶和没有形成导电材料的部分晶种层被去除。例如,可以使用氧等离子等通过可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶,就可以通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案138和通孔。在穿过介电层132到达通孔112和/或管芯连接件126的开口中形成通孔。
在图9中,介电层140沉积在金属化图案138和介电层132上。在一些实施例中,介电层140由聚合物形成,该聚合物可以是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中,介电层140由诸如氮化硅的氮化物;诸如氧化硅、PSG、BSG、BPSG等的氧化物形成。介电层140可以通过旋涂、层压、CVD等或它们的组合形成。
在图10中,然后图案化介电层140。图案化形成开口以暴露金属化图案138的部分。可以通过任何可接受的工艺进行图案化,例如当介电层是光敏材料时将介电层140暴光于光或者例如使用各向异性蚀刻的蚀刻。如果介电层140是光敏材料,则介电层140可以在曝光之后进行显影。
在图11中,具有通孔的金属化图案146形成在介电层140上。作为形成金属化图案146的示例,晶种层(未示出)形成在介电层140上方以及穿过介电层140的开口中。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如可以使用PVD等形成晶种层。然后在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成并且可以被暴露于用于图案化的光。光刻胶的图案对应于金属化图案146。图案化形成穿过光刻胶的开口以暴露晶种层。导电材料形成在光刻胶的开口中以及晶种层的暴露部分上。通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括诸如铜、钛、钨、铝等的金属。然后,光刻胶和没有形成导电材料的部分晶种层被去除。例如,可以使用氧等离子等通过可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶,就可以通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案146和通孔。例如,在穿过介电层140到达部分金属化图案138的开口中形成通孔。
在图12中,介电层148沉积在金属化图案146和介电层140上。在一些实施例中,介电层148由聚合物形成,该聚合物可以是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中,介电层148由诸如氮化硅的氮化物;诸如氧化硅、PSG、BSG、BPSG等的氧化物形成。介电层148可以通过旋涂、层压、CVD等或它们的组合形成。
在图13中,然后图案化介电层148。图案化形成开口以暴露金属化图案146的部分。可以通过任何可接受的工艺进行图案化,例如当介电层是光敏材料时将介电层148暴光于光或者例如通过使用各向异性蚀刻的蚀刻。如果介电层148是光敏材料,则介电层148可以在曝光之后进行显影。
在图14中,具有通孔的金属化图案154形成在介电层148上。作为形成金属化图案154的示例,晶种层(未示出)形成在介电层148上方以及穿过介电层148的开口中。在一些实施例中,晶种层是金属层,其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。例如可以使用PVD等形成晶种层。然后在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成并且可以被暴露于用于图案化的光。光刻胶的图案对应于金属化图案154。图案化形成穿过光刻胶的开口以暴露晶种层。导电材料形成在光刻胶的开口中以及晶种层的暴露部分上。通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括诸如铜、钛、钨、铝等的金属。然后,光刻胶和没有形成导电材料的部分晶种层被去除。例如,可以使用氧等离子等通过可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶,就可以通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案154和通孔。例如,在穿过介电层148到达部分金属化图案146的开口中形成通孔。
在图15中,介电层156沉积在金属化图案154和介电层148上。在一些实施例中,介电层156由聚合物形成,该聚合物可以是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中,介电层156由诸如氮化硅的氮化物;诸如氧化硅、PSG、BSG、BPSG等的氧化物形成。介电层156可以通过旋涂、层压、CVD等或它们的组合形成。
在图16中,然后图案化介电层156。图案化形成开口以暴露金属化图案154的部分,以用于随后形成焊盘162。可以通过可接受的工艺进行图案化,例如当介电层是光敏材料时将介电层156暴光于光或者例如通过使用各向异性蚀刻的蚀刻。如果介电层156是光敏材料,则介电层156可以在曝光之后进行显影。
作为示例示出正面再分布结构160。更多或更少的介电层和金属化图案可以形成在正面再分布结构160中。如果要形成更少介电层和金属化图案,则可以省略以上所讨论的步骤和工艺。如果要形成更多介电层和金属化图案,则可以重复以上论述的步骤和工艺。本领域技术人员应该容易理解,可以省略或重复那些步骤或工艺。
在图17中,焊盘162形成在正面再分布结构160的外侧上。焊盘162可以用于连接至导电连接件166(参见图20A和20B)并且被称为凸块底部金属化件(UBM)162。在所示的实施例中,在穿过介电层156到达金属化图案154的开口中形成焊盘162。作为形成焊盘162的示例,晶种层(未示出)形成在介电层156上方。在一些实施例中,晶种层是金属层,其是单层或者包括由不同材料所形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和钛层上方的铜层。可以使用诸如PVD等形成晶种层。然后在晶种层上形成并图案化光刻胶。光刻胶可以通过旋涂等形成并且曝光于图案化的光。光刻胶的图案对应于焊盘162。图案化形成穿过光刻胶的开口以暴露晶种层。导电材料形成在光刻胶的开口中以及晶种层的暴露部分上。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括诸如铜、钛、钨、铝等的金属。然后,光刻胶和没有形成导电材料的部分晶种层被去除。可以通过诸如使用氧等离子等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶,就可以通过可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成焊盘162。在实施例中,在不同地形成焊盘162的情况下,可以利用更多的光刻胶和图案化步骤。
在图18中,进一步图案化介电层156。在一些实施例中,在与用于焊盘162的开口的同时形成用于IPD部件170的开口164。该图案化形成开口164以暴露用于随后接合IPD部件170的金属化图案154的部分。可以通过可接受的工艺进行图案化,诸如通过当介电层为光敏材料时将介电层156曝光于光或者通过使用诸如各向异性蚀刻的蚀刻。如果介电层156为光敏材料,则介电层156可以在曝光之后被显影。
图19A至图19D示出了根据一些实施例的开口164的截面图。图19A示出了其宽度小于金属化图案154的宽度的穿过介电层156的开口164。图19B示出了其宽度大于金属化图案154的宽度的穿过介电层156的开口164。
图19C和图19D示出了具有逐渐变细的侧壁164A的开口164。在图19C中,开口164通过光刻工艺形成并且导致逐渐变细的侧壁164A是光滑的。在图19D中,开口164通过激光钻孔工艺形成并且导致逐渐变细的侧壁164A略微粗糙。开口164的粗糙侧壁164A可以导致IPD部件170的更大粘合性和接合强度。
在图20A中,导电连接件166形成在UBM 162上并且IPD部件170通孔开口164接合至金属化图案154。IPD部件可以使用微凸块与焊料层接合至金属化图案154。在一些实施例中,在IPD部件接合并安装至再分布结构160之前,导电连接件166可以安装在焊盘162上。在一些实施例中,在将IPD部件接合并安装至再分布结构之后,将导电连接件166安装至焊盘162。
IPD部件170可以接合至正面再分布结构160的金属化图案,而没有任何UBM或焊盘。通过去除IPD部件170下方的UBM或焊盘,减小了IPD部件170的总高度H1。在一些实施例中,IPD部件170自介电层156的顶面的高度H1与结合至UBM或焊盘的IPD部件相比较,减小了20μm以上。因此,IPD部件170的背面接触衬底400的可能性降低,并且工艺窗口扩大以用于包括IPD部件170的封装结构。
在接合至再分布结构160之前,可以根据可应用的制造工艺处理IPD部件170以形成IPD部件170中的无源器件。例如,IPD部件均包括IPD部件170的主结构172中的一个或多个无源器件。主结构172可以包括衬底和/或密封剂。在包括衬底的实施例中,衬底可以是掺杂或未掺杂硅的半导体衬底或者SOI衬底的有源层。半导体衬底可以包括诸如锗的其他半导体衬底;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP;或它们的组合。还可以使用诸如多层或梯度衬底的其他衬底。无源器件可以包括电容器、电阻器、电感器等或它们的组合。无源器件可以形成在半导体衬底中/或上和/或密封剂内并且通过互连结构174进行互连以形成集成无源器件170,例如,通过主结构172上的一个或多个介电层中的金属化图案形成该互连结构。
IPD部件170进一步包括形成为互连件174上并耦合至互连件174的微凸块176,以制造至其外部连接。微凸块176具有形成在微凸块176的端部上的焊料层或凸块178,该焊料层或凸块形成介于正面再分布结构160和IPD部件170之间的焊料接合点。与诸如用于球栅阵列(BGA)连接件的传统焊球(其中,传统焊球可以具有在约150μm至约300μm的范围内的直径)(参见导电连接件166)相比较,例如,微凸块可以具有约10μm至40μm的范围内的直径。在一些实施例中,微凸块可以具有大约40μm或者更大的间距。
在一些实施例中,IPD部件170在接合工艺期间不能加压于正面再分布结构160。在这些实施例中,通过例如利用拾取和放置工具将IPD部件170放置在导电连接件166的平面处开始接合IPD部件170。接下来,拾取和放置工具将IPD部件170停止于开口164上以及正面再分布结构160的暴露的金属化图案154上。在随后的接合工艺期间,微凸块例如通过回流工艺接合至金属化图案154,作为接合工艺的结果,形成焊料接合点,从而将IPD部件170的微凸块176与封装件的金属化图案154电和机械连接。微凸块176的小尺寸允许微凸块176之间的小间距并且能够进行高密度连接。
图20B示出了再分布结构160的一部分、IPD部件170中的一个UBM162中的一个和导电连接件166中的一个的详细示图。微凸块176和焊料层178具有如自金属化图案154的表面所测量的高度H2。UBM 162具有如自金属化图案154的表面所测量的高度H3,其中高度H3大于高度H2。在一些实施例中,H2和H3之差可以大于20μm。
再次参考图20A,导电连接件166可以是BGA连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)所形成的凸块等。导电连接件166可以包括导电连接件,诸如焊锡、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中,最初通过诸如蒸发、电镀、印刷、焊料转移、球放置等的这些通用的方法形成焊料层来形成导电连接件166。一旦焊料层已经形成在结构上,就可以执行回流以将材料成型为期望的凸块形状。在另一实施例中,导电连接件166是通过溅射、印刷、电镀、化学镀、CVD等所形成的金属柱(诸如铜柱)。金属柱可以没有焊锡并且具有基本垂直的侧壁。在一些实施例中,金属覆盖层(未示出)形成在金属柱连接件166的顶部上。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金、等或它们的组合,并且可以通过镀工艺形成该金属覆盖层。
图21A和图21B示出了根据一些实施例的IPD部件170的截面图。在图21A中,IPD部件170的主结构172包括由模制材料182封装的无源器件170或者可以位于半导体衬底182中。无源器件180可以包括电容器、电阻器、电感器等或者它们的组合。模制材料182可以是模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合。在一些实施例中,衬底182可以是诸如掺杂或未掺杂的硅的半导体衬底或者SOI衬底的有源层。半导体衬底可以包括其他半导体材料,诸如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP;或者它们的组合。互连结构174包括主结构172上的一个或多个介电层中的金属化图案与耦合至互连结构174的微凸块176和焊料层178。
除了图21B中的互连结构174包括更多金属化图案和介电层之外,图21B中的IPD部件170类似于图21A中的IPD部件170。这种金属化图案和介电层的增加允许多个电源和接地网络插入IPD部件170内,以降低IPD部件170的寄生电容和/或电感,从而改善了IPD部件170的性能。IPD部件170的这些改善可以导致具有更高频率的IPD部件170部件的更稳定电压。
图22A至图22C示出了根据一些实施例的IPD部件170的底部填充方案的截面图。底部填充材料可能是环氧树脂或聚合物与填充剂或助焊剂。图22A示出了底部填充物184完全填充介于IPD部件170和正面再分布结构160之间的区域并且环绕微凸块176的完全填充底部填充方案。在IPD部件170附接之后通过毛细管流工艺形成底部填充物184或者在附接IPD部件170之前通过适当的沉积或印刷方法形成该底部填充物。
图22B示出了底部填充物184部分地填充介于介于IPD部件170和正面再分布结构160之间的区域并且部分环绕微凸块176的部分填充底部填充方案。在IPD部件170附接之后通过毛细管流工艺形成底部填充物184或者在附接IPD部件170之前通过适当的沉积或印刷方法形成该底部填充物。
图22C示出了没有底部填充物填充在IPD部件170和正面再分布结构160之间的区域的无填充的底部填充方案。
在图23中,执行载体衬底脱粘,以将载体衬底100与例如介电层104的背面再分布结构分离(脱粘)。根据一些实施例,脱粘包括将诸如激光或UV光的光投射到释放层102上,使得释放层102在光的加热下分解并且可以去除载体衬底100。然后结构被翻转并放置在胶带190上。
此外,如图23所示,开口形成为穿过介电层104以暴露金属化图案106的部分。例如,可以使用激光钻孔、蚀刻等形成开口。
在图24中,例如可以通过沿着相邻区域600和602之间的划线区域分离186来执行分离工艺。在一些实施例中,分离186包括锯切工艺、激光工艺或它们的组合。分离186将第一封装区域600与第二封装区域602分离。
图25示出了可以是第一封装区域600或第二封装区域602中的一个的生成的分离式封装件200。封装件200还可以被称为集成扇出(InFO)封装件200。在一些实施例中,在将第二封装件300接合至InFO封装件200之后执行分离工艺。
图26示出了包括封装件200(可以被称为第一封装件200)、第二封装件300和衬底400的封装结构500。第二封装件300包括衬底302和耦合至衬底的一个或多个堆叠管芯308(308A和308B)。衬底302可以由诸如硅、锗、金刚石等的半导体材料制成。在一些实施例中,还可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、它们的组合等。另外地,衬底302可以是SOI衬底。通常SOI衬底包括半导体材料层,诸如外延硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或者它们的组合。在一个可选实施例中,衬底302基于诸如玻璃纤维树脂芯的绝缘芯。芯材料的一个实例是玻璃纤维树脂,诸如FR4。可选芯材料包括双马来酰亚胺三嗪(BT)树脂,或者可选地,其他印刷电路板(PCB)材料或膜。诸如味之素累积膜(ABF,Ajinomoto build-up film)的累积膜或者其他层压件可以用于衬底302。
衬底302可以包括有源器件或无源器件(未示出)。本领域技术人员应该意识到,诸如晶体管、电容器、电阻器、它们的组合等的各种器件可以用于生成设计半导体封装件300的结构和功能必需品。可以使用任何适当的方法来形成器件。
衬底302还可以包括金属化层(未示出)和通孔306。金属化层可以形成在有源器件和无源器件上方并且被设计为连接各种器件以形成功能电路。金属化层可以由介电材料(例如,低k介电材料)和导电材料的交替层以及互连导电材料层的通孔形成,并且通过任何适当的工艺形成(诸如,沉积、镶嵌、双镶嵌等)。在一些实施例中,衬底302基本上没有有源器件和无源器件。
衬底302可以在衬底302的第一面上具有接合焊盘303以耦合至堆叠管芯308并且在衬底302的第二面上具有接合焊盘304以耦合至导电连接件314,衬底302的第二面与第一面相对。在一些实施例中,通过在衬底302的第一面和第二面上的介电层(未示出)中形成凹槽来形成接合焊盘303和304。凹槽可以形成为允许接合焊盘303和304嵌入介电层中。在其他实施例中,当接合焊盘303和304可以形成在介电层上时,省略凹槽。在一些实施例中,接合焊盘303和304包括由铜、钛、镍、金、钯等或它们的组合所制成的薄晶种层(未示出)。接合焊盘303和304的导电材料可以沉积在薄晶种层上方。可以通过电化学镀工艺、化学镀工艺、CVD、ALD、PVD等或它们的组合来形成导电材料。在实施例中,接合焊盘303和304的导电材料为铜、钨、铝、银、金等或它们的组合。
在实施例中,接合焊盘303和304为UBM,该UBM包括三个导电材料层,诸如钛层、铜层和镍层。然而,本领域技术人员将意识到,存在适用于形成UBM 303和304的多个适当的材料和层的配置,诸如铬/铬铜合金/铜/金的配置、钛/钛钨/铜的配置或者铜/镍/金的配置。可以用于UBM 303和304的任何适当的材料或者材料层完全旨在包括在本发明的范围内。在一些实施例中,通孔306延伸穿过衬底302并且将至少一个接合焊盘303耦合至至少一个接合焊盘304。
在所示的实施例中,堆叠管芯308通过接合引线310接合至衬底302,但是可以使用其他连接件,诸如导电凸块。在实施例中,堆叠管芯308是堆叠的存储器管芯。例如,堆叠的存储器管芯308可以包括低功率(LP)双数据速率(DDR)存储模块,诸如LPDDR1、LPDDR2、LPDDR3、LPDDR4等的存储模块。
在一些实施例中,可以通过模制材料312封装堆叠管芯308和接合引线310。例如,可以使用压缩模制在堆叠管芯308和接合引线310上模制模制材料312。在一些实施例中,模制材料312是模塑料、聚合物、环氧树脂、二氧化硅填充材料等或它们的组合。可以执行固化步骤以固化模制材料312,其中,固化可以是热固化、UV固化等或它们的组合。
在一些实施例中,堆叠管芯308和接合引线310埋置在模制材料312中,并且在固化模制材料312之后,执行诸如研磨的平坦化步骤以去除模制材料312的多余部分并且提供第二封装件300的基本平坦的表面。
在形成第二封装件300之后,封装件300可以通过导电连接件314、接合焊盘304、和金属化图案106接合至第一封装件200。在一些实施例中,堆叠的存储器管芯308可以通过接合引线310、接合焊盘303和304、通孔306、导电连接件314和通孔112耦合至集成电路管芯114。
导电连接件314可以类似于以上所述的导电连接件166并且该描述本文中不再重复,但是导电连接件314和166不需要是相同的。在一些实施例中,在接合至导电连接件314之前,导电连接件314涂覆有助焊剂(未示出),诸如免洗助焊剂。导电连接件314可以浸入助焊剂或者助焊剂可以喷射到导电连接件314上。在另一实施例中,助焊剂可以应用于金属化图案106的表面。
在一些实施例中,导电连接件314在回流之前,具有形成在其上的环氧树脂助焊剂(未示出),其中,在第二封装件300附接至第一封装件200之后剩余环氧树脂助焊剂的至少一些环氧树脂部分。该剩余的环氧助焊剂可以用作底部填充物以降低应力并且保护由回流导电连接件314所生成的接合点。在一些实施例中,底部填充物(未示出)可以形成在第二封装件300和第一封装件200之间并且环绕导电连接件314。可以在附接第二封装件300之后通过毛细管流工艺形成底部填充物或者在附接第二封装件300之前通过适当的沉积方法形成底部填充物。
第二封装件300和第一封装件200之间的接合可以是焊料接合或者直接金属与金属(例如,铜与铜或锡与锡)接合。在实施例中,第二封装件300通过回流工艺接合至第一封装件200。在该回流工艺期间,导电连接件314与结合焊盘304和金属化图案106接触以将第二封装件300物理地并且电耦合至第一封装件200。在接合工艺之后,IMC(未示出)可以形成在金属化图案106和导电连接件314的界面处并还形成在导电连接件314和接合焊盘304之间的界面处(未示出)。
半导体封装件500包括安装至衬底400的封装件200和300。衬底400可以被称为封装衬底400。封装件200使用导电连接件166安装至封装衬底400。通过安装至衬底400的封装件200,IPD部件(多个IPD部件)170夹置在封装件200的再分布结构160和衬底400之间。IPD部件170可以与衬底400间隔开间隙G1,可以通过本发明的改进来控制该间隙。
封装衬底400可以由半导体材料的制成,诸如硅、锗、金刚石等。可选地,还可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、它们的组合等。另外地,封装衬底400可以是SOI衬底。通常SOI衬底包括半导体材料层,诸如外延硅、锗、硅锗、SOI、SGOI、或者它们的组合。在一个可选实施例中,封装衬底400基于诸如玻璃纤维增强树脂芯的绝缘芯。芯材料的一个实例为诸如FR4的玻璃纤维树脂。可选芯材料包括双马来酰亚胺三嗪(BT)树脂,或者可选地,其他印刷电路板(PCB)材料或膜。诸如ABF的累积膜或者其他层压件可以用于封装衬底400。
封装衬底400可以包括有源器件和无源器件(图22A-22C中非示出)。本领域技术人员应该理解,诸如晶体管、电容器、电阻器、它们的组合等的各种器件可以用于生成设计半导体封装件500的结构和功能必需品。可以使用任何适当的方法来形成器件。
封装衬底400还可以包括金属化层和通孔(未示出)以及金属化层和通孔上方的接合焊盘402。金属化层可以形成在有源器件和无源器件上方并且被设计为连接功能器件以形成功能电路。金属化层可以由介电材料(低k介电材料)和导电材料(诸如铜)的交替层与互连导电材料层的通孔形成并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成该金属化层。在一些实施例中,封装衬底400基本上没有有源和无源器件。
在一些实施例在,导电连接件166可以回流以将封装件200附接至接合焊盘。导电连接件166将衬底(包括衬底400中的金属化层)400电和/或物理耦合至第一封装件200。
导电连接件166回流之前,可以具有形成在其上的环氧树脂助焊剂(未示出),其中,在封装件200附接至衬底400之后剩余环氧树脂助焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物,以降低应力并且保护由回流导电连接件166所生成的接合点。在一些实施例中,底部填充物(未示出)可以形成在第一封装件200和衬底400之间并且环绕导电连接件166和IPD部件170。在附接封装件200之后通过毛细管流工艺形成底部填充物,或者在附接封装件200之后通过适当的沉积方法形成该底部填充物。
本发明的实施例包括具有IPD设计的封装结构,该IPD设计增加系统性能并且扩大工艺窗口以改善可靠性以及封装结构的接合产量。封装结构可以包括扇出或扇入封装件并且可以包括一个或多个再分布层(RDL)。IPD部件可以接合至封装结构的一个或多个RDL。IPD部件可以接合至邻近导电接合点的一个或多个RDL,该导电接合点将两个封装件/衬底耦合并接合在一起。相邻的导电接合点可以包括一个或多个RDL上的凸块底部金属化件(UBM)以及耦合至该UBM的焊料接合点。IPD部件可以接合至一个或多个RDL而没有任何UBM。通过去除IPD部件接合区域下方的UBM,减小IPD的总高度并且扩大工艺窗口。
实施例是一种结构,该结构包括第一管芯;模塑料,至少横向封装所述第一管芯;第一再分布结构,包括在所述第一管芯和所述模塑料上方延伸的金属化图案;第一导电连接件,包括耦合至所述第一再分布结构的焊球和凸块底部金属化件;以及集成无源器件,通过微凸块接合点接合至所述第一再分布结构中的第一金属化图案,所述集成无源器件邻近所述第一导电连接件。
在实施例中,所述微凸块接合点的焊料层与所述第一再分布结构的所述第一金属化图案接触,并且,所述第一导电连接件的凸块底部金属化件与所述第一再分布结构中的第二金属化图案接触。
在实施例中,所述第一金属化图案位于与所述第二金属化图案相同的所述第一再分布结构中的平面处。
在实施例中,封装结构进一步包括:衬底使用所述第一导电连接件接合至所述第一再分布结构。
在实施例中,所述集成无源器件夹置在所述第一再分布结构和所述衬底之间。
在实施例中,封装结构进一步包括:电连接件,延伸穿过所述模塑料,所述模塑料邻近所述第一管芯;以及
封装结构,包括第二管芯,所述封装结构通过所述第二导电连接件接合至所述电连接件,所述第一管芯夹置在所述封装结构和所述衬底之间。
另一实施例为一种方法,包括:形成所述第一封装件包括:在载体衬底上方形成电连接件;将第一管芯附接至所述载体衬底,所述电连接件从所述第一管芯的第二面延伸至所述第一管芯的第一面,所述第二面与所述第一面相对,所述电连接件邻近所述第一管芯;通过模塑料封装所述第一管芯和所述电连接件;在所述第一管芯的第一面和所述模塑料下方形成再分布结构,所述再分布结构包括金属化图案;将包括凸块底部金属化件的第一导电连接件耦合至所述第一再分布结构的第一金属化图案;以及通过接合点将集成无源器件接合至所述再分布结构的第二金属化图案。
在实施例中,用于形成封装结构的方法进一步包括:使用第二组导电连接件将第一封装件耦合至所述第一封装件,所述第二封装件接近所述第一管芯的第二面。
在实施例中,所述接合点包括微凸块与焊料层,所述焊料层接触所述再分布结构的所述第二金属化图案。
在实施例中,用于形成封装结构的方法进一步包括:第一介电层图案化为形成第一开口以暴露所述第二金属化图案的第一部分,所述集成无源器件的接合点利用所述第一开口。
在实施例中,所述第一开口宽于所述第二金属化图案。
在实施例中,所述第一开口窄于所述第二金属化图案。
在实施例中,所述第一开口的侧壁从所述第一介电层的顶面朝向所述第二金属化图案逐渐变细。
在实施例中,将所述第一介电层图案化为形成第一开口包括执行激光钻工艺或者光刻以形成所述第一开口。
在实施例中,用于形成封装结构的方法进一步包括:在所述再分布结构和所述集成无源器件之间形成底部填充物,所述底部填充物环绕所述接合点。
在实施例中,用于形成封装结构的方法进一步包括:使用所述第一导电连接件将衬底接合至所述第一封装件,其中,在接合之后,所述集成无源器件夹置于所述再分布结构和所述衬底之间。
在实施例中,所述第一金属化图案位于与所述第二金属化图案相同的所述再分布结构的平面处。
另一实施例为一种方法,包括:形成邻近第一管芯的第一通孔,所述第一通孔从所述第一管芯的第二面延伸至所述第一管芯的第一面,所述第二面与所述第一面相对;通过模制材料封装所述第一通孔和所述第一管芯;在所述第一管芯的第一面、所述第一通孔、以及所述模制材料上方形成第一再分布结构,所述第一再分布结构包括多个金属化图案和多个介电层;形成位于所述第一再分布结构的第一介电层上方并且穿过所述第一再分布结构的第一介电层的第一凸块底部金属化层以接触所述第一再分布结构的第一金属化图案;以及通过接合点将集成无源器件接合至所述第一再分布结构的第二金属化图案,所述接合点延伸穿过所述第一再分布结构的所述第一介电层。
在实施例中,用于形成封装结构的方法进一步包括:使用第二导电连接件将第二封装件接合至所述第一通孔,所述第二封装件邻近所述第一管芯的第二面。
在实施例中,所述接合点包括微凸块与焊料层,所述焊料层接触所述第一再分布结构的所述第二金属化图案。
上面论述了多个实施例的特征使得本领域技术人员能够更好地理解本发明的各个方面。本领域技术人员应该理解,他们可以容易地以本公开为基础设计或修改用于执行与本文所述实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员还应该意识到,这些等效结构不背离本发明的精神和范围,并且可以在不背离本发明的精神和范围的情况下做出各种变化、替换和改变。
Claims (17)
1.一种封装结构,包括:
第一管芯;
模塑料,至少横向封装所述第一管芯;
第一再分布结构,包括在所述第一管芯和所述模塑料上方延伸的金属化图案;
第一导电连接件,包括耦合至所述第一再分布结构的焊球和凸块底部金属化件;以及
集成无源器件,通过微凸块接合点接合至所述第一再分布结构中的第一金属化图案,所述集成无源器件邻近所述第一导电连接件,其中,所述微凸块接合点包括微凸块和形成在所述微凸块上的焊料层,所述焊料层的第一面与所述第一金属化图案接触,所述焊料层的第二面与所述微凸块接触;
封装衬底,使用所述第一导电连接件接合至所述第一再分布结构,其中,所述集成无源器件在垂直方向上夹置在所述封装衬底与所述第一再分布结构之间,并且所述集成无源器件的背离所述第一管芯的表面与所述封装衬底的面向所述第一管芯的表面之间存在间隙,
其中,所述集成无源器件位于所述第一导电连接件之间,
其中,所述凸块底部金属化件与所述第一再分布结构中的第二金属化图案接触,并且具有在所述凸块底部金属化件的背离所述第一管芯的最上表面与所述凸块底部金属化件的接触所述第二金属化图案的最下表面之间测得的第一高度,
其中,所述微凸块接合点具有在所述微凸块的背离所述第一管芯的上表面和所述焊料层的第一面之间测量的第二高度,其中,所述第一高度大于所述第二高度。
2.根据权利要求1所述的封装结构,其中,所述第一金属化图案位于与所述第二金属化图案相同的所述第一再分布结构中的平面处。
3.根据权利要求1所述的封装结构,其中,所述微凸块和所述焊料层具有相同的宽度,使得所述微凸块的第一侧壁与所述焊料层的第二侧壁对齐。
4.根据权利要求1所述的封装结构,所述集成无源器件包括电容器、电阻、电感器或它们的组合。
5.根据权利要求3所述的封装结构,进一步包括:
电连接件,延伸穿过所述模塑料,所述模塑料邻近所述第一管芯;以及
封装结构,包括第二管芯,所述封装结构通过第二导电连接件接合至所述电连接件,所述第一管芯夹置在所述封装结构和所述衬底之间。
6.一种用于形成封装结构的方法,包括:
形成第一封装件包括:
在载体衬底上方形成电连接件;
将第一管芯附接至所述载体衬底,所述电连接件从所述第一管芯的第二面延伸至所述第一管芯的第一面,所述第二面与所述第一面相对,所述电连接件邻近所述第一管芯;
通过模塑料封装所述第一管芯和所述电连接件;
在所述第一管芯的第一面和所述模塑料上方形成再分布结构,所述再分布结构包括金属化图案;
将包括凸块底部金属化件的第一导电连接件耦合至所述再分布结构的第一金属化图案,其中,所述凸块底部金属化件具有在所述凸块底部金属化件的背离所述第一管芯的最上表面与所述凸块底部金属化件的接触所述第一金属化图案的最下表面之间测得的第一高度;
通过接合点将集成无源器件接合至所述再分布结构的第二金属化图案,其中,所述接合点包括微凸块和形成在所述微凸块上的焊料层,所述焊料层的第一面与所述第二金属化图案接触,所述焊料层的第二面与所述微凸块接触,所述接合点具有在所述微凸块的背离所述第一管芯的上表面和所述焊料层的第一表面之间测量的第二高度,其中,所述第一高度大于所述第二高度;以及
使用所述第一导电连接件将衬底接合至所述第一封装件,其中,在接合之后,所述集成无源器件夹置于所述再分布结构和所述衬底之间,并且所述集成无源器件的背离所述第一管芯的表面与所述衬底的面向所述第一管芯的表面之间存在间隙。
7.根据权利要求6所述的用于形成封装结构的方法,进一步包括:
使用第二组导电连接件将第二封装件耦合至所述第一封装件,所述第二封装件接近所述第一管芯的第二面。
8.根据权利要求6所述的用于形成封装结构的方法,进一步包括:
第一介电层图案化为形成第一开口以暴露所述第二金属化图案的第一部分,所述集成无源器件的接合点利用所述第一开口。
9.根据权利要求8所述的用于形成封装结构的方法,其中,所述第一开口宽于所述第二金属化图案。
10.根据权利要求8所述的用于形成封装结构的方法,其中,所述第一开口窄于所述第二金属化图案。
11.根据权利要求8所述的用于形成封装结构的方法,其中,所述第一开口的侧壁从所述第一介电层的顶面朝向所述第二金属化图案逐渐变细。
12.根据权利要求8所述的用于形成封装结构的方法,其中,将所述第一介电层图案化为形成第一开口包括执行激光钻工艺或者光刻以形成所述第一开口。
13.根据权利要求6所述的用于形成封装结构的方法,进一步包括:
在所述再分布结构和所述集成无源器件之间形成底部填充物,所述底部填充物环绕所述接合点。
14.根据权利要求6所述的用于形成封装结构的方法,其中,所述微凸块和所述焊料层具有相同的宽度,使得所述微凸块的第一侧壁与所述焊料层的第二侧壁对齐。
15.根据权利要求6所述的用于形成封装结构的方法,其中,所述第一金属化图案位于与所述第二金属化图案相同的所述再分布结构的平面处。
16.一种用于形成封装结构的方法,包括:
形成邻近第一管芯的第一通孔,所述第一通孔从所述第一管芯的第二面延伸至所述第一管芯的第一面,所述第二面与所述第一面相对;
通过模制材料封装所述第一通孔和所述第一管芯;
在所述第一管芯的第一面、所述第一通孔、以及所述模制材料上方形成第一再分布结构,所述第一再分布结构包括多个金属化图案和多个介电层;
形成位于所述第一再分布结构的第一介电层上方并且穿过所述第一再分布结构的第一介电层的第一凸块底部金属化层以接触所述第一再分布结构的第一金属化图案,其中,所述第一凸块底部金属化层具有在所述第一凸块底部金属化层的背离所述第一管芯的最上表面与所述第一凸块底部金属化层的接触所述第一金属化图案的最下表面之间测得的第一高度;以及
通过接合点将集成无源器件接合至所述第一再分布结构的第二金属化图案,所述接合点延伸穿过所述第一再分布结构的所述第一介电层,其中,所述接合点包括微凸块和形成在所述微凸块上的焊料层,所述焊料层的第一表面与所述第二金属化图案接触,所述焊料层的第二面与所述微凸块接触,所述接合点具有在所述微凸块的背离所述第一管芯的上表面和所述焊料层的第一表面之间测量的第二高度,其中,所述第一高度大于所述第二高度;
使用包括所述第一凸块底部金属化层的第一导电连接件将衬底接合至所述第一再分布结构,其中,在接合之后,所述集成无源器件夹置于所述第一再分布结构和所述衬底之间,并且所述集成无源器件的背离所述第一管芯的表面与所述衬底的面向所述第一管芯的表面之间存在间隙。
17.根据权利要求16所述的用于形成封装结构的方法,进一步包括:使用第二导电连接件将第二封装件接合至所述第一通孔,所述第二封装件邻近所述第一管芯的第二面。
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