TWI571185B - 電子封裝件及其製法 - Google Patents
電子封裝件及其製法 Download PDFInfo
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description
本發明係有關一種封裝製程,特別是關於一種能改善封裝製程良率之電子封裝件及其製法。
貫穿膠體(Through molding via,簡稱TMV)之技術,目前已廣泛運用於半導體領域,其主要技術係利用雷射燒灼方式於封裝膠體表面進行開孔製程,以增加佈線空間。例如,製作扇出型(Fan-Out,簡稱FO)封裝堆疊(Package on Package,簡稱POP)結構時,便會使用該技術。
第1A至1F圖係為習知扇出型封裝堆疊裝置之其中一電子封裝件1之製法之剖面示意圖。
如第1A圖所示,設置一如晶片之電子元件10於一第一承載件18之離形層180上,再形成一絕緣層11於該離形層180上以覆蓋該電子元件10。
如第1B圖所示,將具有銅箔190之第二承載件19設於該絕緣層11上。
如第1C圖所示,移除該第一承載件18及其離形層180,以露出該電子元件10與絕緣層11。
如第1D圖所示,以雷射方式形成複數通孔110於該
電子元件10周邊之絕緣層11上。
如第1E圖所示,電鍍銅材於該些通孔110中,以形成導電柱12,再於該絕緣層11上形成複數線路重佈層(redistribution layer,簡稱RDL)13,以令該線路重佈層13電性連接該導電柱12與電子元件10。
如第1F圖所示,移除該第二承載件19,再利用該銅箔190進行圖案化線路製程,以形成線路結構15,之後再進行切單製程。
隨著該電子元件10之體積朝輕薄短小及功能性增強之趨勢設計,故需藉由增加該絕緣層11之厚度以提升該電子封裝件1之可靠度。
惟,前述習知導電柱12之製法中,使用雷射鑽孔方式形成該通孔110,目前雷射鑽孔製程與電鍍製程技術所能相互配合之深寬比係小於1.25,故增加該絕緣層11之厚度對於該通孔110的深寬比製作影響極大。例如,當該絕緣層11之厚度變厚(即該通孔110之深度H增加)時,若雷射鑽孔製程需將該通孔110之深寬比控制在小於1.25之範圍內,則該通孔110之孔徑(即寬度D)需增加(如第1D圖之虛線),因而不符合細線距(fine pitch)之需求;若將雷射鑽孔之深寬比提升至1.5,則當將銅材填入該些通孔110’中時,該通孔110’之底部無法鍍滿(即氣室12’),如第1E’圖所示,因而影響後續封裝製程良率,導致FOPOP製作成本太高。
再者,以雷射方式形成該通孔110,於形成該通孔110
之過程中所產生之殘留物(如該絕緣層11之殘膠)極易堆積於該通孔110之底部,故需於後續製程中需先清洗該通孔110內部,才能將導電材料填入該通孔110中,但因增加該絕緣層11之厚度而使該通孔110之深度H增加,以致於難以完全清除該通孔110中之殘留物,導致殘留物會影響該導電柱12電性傳輸之良率。
因此,如何克服上述習知技術的種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明提供一種電子封裝件,係包括:絕緣層,係具有相對之第一表面與第二表面,且於該絕緣層中具有至少一第一穿孔和與該第一穿孔連通之第二穿孔,其中,該第一穿孔連通至該第一表面,該第二穿孔連通至第二表面;至少一電子元件,係嵌埋於該絕緣層中;至少一第一導電體,係對應並僅設於該第一穿孔中;以及第一線路結構,係設於該絕緣層之第一表面上,且該第一線路結構電性連接該電子元件與該第一導電體。
本發明復提供一種電子封裝件之製法,係包括:提供一嵌埋有至少一電子元件之絕緣層,該絕緣層具有相對之第一表面與第二表面;於該絕緣層中形成連通至該第一表面之至少一第一穿孔;形成第一導電體於該第一穿孔中;形成第一線路結構於該絕緣層之第一表面上,且該第一線路結構電性連接該電子元件與該第一導電體;以及於該絕
緣層中形成對應連通該第一穿孔和第二表面之第二穿孔,令該第一穿孔與第二穿孔構成通孔。
前述之製法中,該絕緣層係以模壓製程或壓合製程形成者。
前述之製法中,該第一穿孔或第二穿孔係以雷射鑽孔、機械鑽孔或蝕刻方式形成者。
前述之電子封裝件及其製法中,該電子元件係具有相對之作用面與非作用面,且該作用面具有複數電極墊。例如,該第一表面與該作用面齊平;或者,該第二表面與該非作用面齊平。
前述之電子封裝件及其製法中,該第一導電體係為金屬柱或金屬球。
前述之電子封裝件及其製法中,復包括形成第二線路結構於該絕緣層之第二表面上,且該第二線路結構電性連接該第一導電體,復可電性連接該電子元件。
前述之電子封裝件及其製法中,復包括形成第二導電體於該第二穿孔中,且該第二導電體電性連接該第一導電體,而該第二導電體係為金屬柱。
另外,前述之電子封裝件及其製法中,復包括堆疊電子封裝結構於該絕緣層之第一表面或第二表面上。
由上可知,本發明之電子封裝件及其製法中,藉由兩階段製程製作該通孔,故可不受雷射鑽孔之深寬比限制,當該絕緣層之厚度變厚時,仍可將第一穿孔與第二穿孔之深寬比控制在小於1.25之範圍內,而無需增加該第一穿孔
與第二穿孔之孔徑,以符合細線距之需求。
再者,由於該第一穿孔之深寬比無需增加,故該第一導電體能有效鍍滿該第一穿孔。
又,因分別製作第一穿孔與第二穿孔,故該第一穿孔之深度及第二穿孔之深度均小於該通孔之深度,因而容易清除該第一穿孔及第二穿孔中之殘留物,以避免殘留物影響該第一導電體或第二導電體電性傳輸之良率。
因此,本發明之製法能提升封裝製程良率,以降低製作成本。
1,2,2’,3,3’‧‧‧電子封裝件
10,20‧‧‧電子元件
11,21‧‧‧絕緣層
110,110’,210‧‧‧通孔
12‧‧‧導電柱
12’‧‧‧氣室
13,231,251,251’‧‧‧線路重佈層
15‧‧‧線路結構
18‧‧‧第一承載件
180‧‧‧離形層
19‧‧‧第二承載件
190‧‧‧銅箔
20a‧‧‧作用面
20b‧‧‧非作用面
200‧‧‧電極墊
21a‧‧‧第一表面
21b‧‧‧第二表面
211‧‧‧第一穿孔
212‧‧‧第二穿孔
22,22’‧‧‧第一導電體
23‧‧‧第一線路結構
230,250‧‧‧介電層
232,252‧‧‧絕緣保護層
233,253‧‧‧電性接觸墊
24‧‧‧第二導電體
25‧‧‧第二線路結構
26,26’‧‧‧導電元件
27‧‧‧電子封裝結構
D‧‧‧寬度
H‧‧‧深度
第1A至1F圖係為習知電子封裝件之製法之剖面示意圖;其中,第1E’圖係為第1E圖之另一狀態;以及第2A至2G圖係為本發明電子封裝件之製法之剖視示意圖;其中,第2A’、2C’、2E’、2E”及2G’圖係為第2A、2C、2E及2G圖之另一方式。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功
效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明電子封裝件2,2’,3,3’之製法之剖視示意圖。
如第2A圖所示,提供一設有至少一電子元件20之承載件(圖略),再形成絕緣層21於該承載件上,以令該絕緣層21包覆該電子元件20。之後移除該承載件。
於本實施例中,該承載件可選用金屬板、半導體晶圓或玻璃板,且該承載件具有一如離形膜、黏著材、絕緣材等之間隔層,以供接合該電子元件20與該絕緣層21。
再者,該電子元件20係為主動元件、被動元件或其組合者,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。於此,該電子元件20係為半導體晶片,其具有相對之作用面20a與非作用面20b,且該作用面20a具有複數電極墊200。
又,該絕緣層21具有相對之第一表面21a及第二表面21b,且該第一表面21a與該作用面20a齊平,而該第二表面21b與該非作用面20b齊平;於其它實施例中,如第2A’圖所示,該絕緣層21覆蓋該非作用面20b。
另外,該絕緣層21係以模壓(molding)樹脂製程形
成者或壓合膜材(Laminate Dry Film Type)形成者,但並不限於此方式。
如第2B圖所示,於該絕緣層21中形成連通至第一表面21a之複數第一穿孔211,且各該第一穿孔211係位於該電子元件20周邊區域。
於本實施例中,該第一穿孔211係以雷射鑽孔、機械鑽孔、蝕刻或其它等方式形成者。
如第2C圖所示,形成第一導電體22於各該第一穿孔211中,再形成第一線路結構23於該絕緣層21之第一表面21a與該電子元件20之作用面20a上。
於本實施例中,該第一導電體22可利用電鍍、沉積或其它習知技術形成如含銅、鋁、鈦、導電膠或其至少二者之組合之導電材於該第一穿孔211中。具體地,該第一導電體22係為金屬柱,例如銅柱;或者,如第2C’圖所示,該第一導電體22’亦可為金屬球,如銅材或銲錫材料。
再者,該第一線路結構23係包含至少一介電層230、設於該介電層230上之一線路重佈層(redistribution layer,簡稱RDL)231、及設於該介電層230上並外露部分該線路重佈層231之一絕緣保護層232,且該線路重佈層231電性連接該電子元件20之電極墊200與該第一導電體22,22’。
又,該線路重佈層231具有外露於該絕緣保護層232之複數電性接觸墊233。
如第2D圖所示,於該絕緣層21中形成連通至第二表
面21b之複數第二穿孔212,且各該第二穿孔212係分別對應各該第一穿孔211之位置而與該第一穿孔211相通,令該第一穿孔211與第二穿孔212構成通孔210。
於本實施例中,該第二穿孔212係以雷射鑽孔、機械鑽孔、蝕刻或其它等方式形成者。
如第2E圖所示,形成第二導電體24於各該第二穿孔212中,再形成第二線路結構25於該絕緣層21之第二表面21b與該非作用面20b上。
於本實施例中,該第二導電體24係電性連接該第一導電體22,且該第二導電體24可利用電鍍、沉積或其它習知技術形成如含銅、鋁、鈦、導電膠或其至少二者之組合之導電材於該第二穿孔212中。具體地,該第二導電體24係為金屬柱,例如銅柱。
再者,該第二線路結構25係包含至少一介電層250、設於該介電層250上之一線路重佈層(redistribution layer,簡稱RDL)251、及設於該介電層250上並外露部分該線路重佈層251之一絕緣保護層252,其中,該線路重佈層251藉由導電盲孔電性連接該第二導電體24,且該線路重佈層251電性連接該電子元件20之非作用面20b以供散熱,該線路重佈層251並藉由該第二導電體24電性連接該第一導電體22。或者,如第2E’圖所示,該線路重佈層251’形成於各該第二穿孔212中以直接電性連接該第一導電體22,而不需形成介電層250與第二導電體24。
又,該線路重佈層251具有外露於該絕緣保護層252
之複數電性接觸墊253。
另外,亦可不形成第二導電體24與第二線路結構25,亦即該通孔210並未填滿金屬材(只填有該第一導電體22’),如接續第2C’圖製程所得之第2E’圖所示之電子封裝件2’。
於後續製程中,如第2F圖所示,形成複數如銲球、導電凸塊之導電元件26於該第一線路結構23之電性接觸墊233上。
或者,如第2G圖所示,藉由該些導電元件26堆疊該電子封裝件2與一電子封裝結構27,以形成一堆疊式電子封裝件3,且該電子封裝件2與該電子封裝結構27係藉由該些導電元件26而相互接觸與電性連接。
於本實施例中,該電子封裝結構27之構造係與該電子封裝件2之構造相同,藉以能堆疊複數個該電子封裝件2。
於另一實施例中,如第2G’圖所示,若堆疊複數個如第2E’圖所示之電子封裝件2’時,上方之電子封裝件2’(可視為電子封裝結構)之部分該些導電元件26將容置於下方之電子封裝件2’之該些第二穿孔212中,使該些導電元件26接觸並電性連接該第一導電體22’,藉以形成一堆疊式電子封裝件3’。
再者,上方之電子封裝件2’之部分該些導電元件26’可選擇性接觸或導通下方之電子封裝件2’之電子元件20之非作用面20b以進行散熱。
本發明之製法中,藉由兩階段製程(即製作第一穿孔
211與第二穿孔212)製作該通孔210,故可不受雷射鑽孔之深寬比限制,亦即當該絕緣層21之厚度變厚時,可將第一穿孔211與第二穿孔212之深寬比控制在小於1.25之範圍內,而無需增加該第一穿孔211與第二穿孔212之孔徑,以符合細線距(fine pitch)之需求。
再者,由於該第一穿孔211之深寬比無需增加,故該第一導電體22能有效鍍滿該第一穿孔211。
又,因分別製作第一穿孔211與第二穿孔212,故該第一穿孔211之深度及第二穿孔212之深度均小於該通孔210之深度,因而容易清除該第一穿孔211及第二穿孔212中之殘留物,以避免殘留物影響該第一導電體22或第二導電體24電性傳輸之良率。
因此,本發明之製法能提升封裝製程良率,以降低製作成本。
本發明提供一種電子封裝件2,2’,3,3’,係包括:一絕緣層21、至少一電子元件20、第一導電體22、以及第一線路結構23。
所述之絕緣層21係具有相對之第一表面21a與第二表面21b,且於該絕緣層21中具有至少一第一穿孔211和與該第一穿孔211連通之第二穿孔212,其中,該第一穿孔211連通至該第一表面21a,該第二穿孔212連通至第二表面21b。
所述之電子元件20係嵌埋於該絕緣層21中。
所述之第一導電體22,22’係對應並僅設於該第一穿孔
211中。該第一導電體22,22’係為金屬柱或銲錫凸塊。
所述之第一線路結構23係設於該絕緣層21之第一表面21a上,且該第一線路結構23電性連接該電子元件20之電極墊200與該第一導電體22,22’。
於一實施例中,所述之電子封裝件2,3復包括形成於該絕緣層21之第二表面21b上的第二線路結構25,其電性連接該第一導電體22,且該第二線路結構25亦可電性連接該電子元件20。
於一實施例中,所述之電子封裝件2,3復包括對應形成於該第二穿孔212中之第二導電體24,其為金屬柱並電性連接該第一導電體22。
於一實施例中,所述之電子封裝件3,3’復包括堆疊於該絕緣層21之第一表面21a或第二表面21b上之電子封裝結構27。
綜上所述,本發明之電子封裝件及其製法中,藉由兩階段製程製作該通孔,故該通孔之深寬比可依需求調整,不僅能符合細線距之需求,且能提升該導電體之電性良率。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
20‧‧‧電子元件
20b‧‧‧非作用面
21‧‧‧絕緣層
21a‧‧‧第一表面
21b‧‧‧第二表面
210‧‧‧通孔
211‧‧‧第一穿孔
212‧‧‧第二穿孔
22‧‧‧第一導電體
23‧‧‧第一線路結構
Claims (25)
- 一種電子封裝件,係包括:絕緣層,係具有相對之第一表面與第二表面,且於該絕緣層中形成有至少一第一穿孔和與該第一穿孔連通之第二穿孔,其中,該第一穿孔係連通至該第一表面,該第二穿孔則連通至該第二表面;至少一電子元件,係嵌埋於該絕緣層中;至少一第一導電體,係對應並僅設於該第一穿孔中;以及第一線路結構,係設於該絕緣層之第一表面上,且該第一線路結構電性連接該電子元件與該第一導電體。
- 如申請專利範圍第1項所述之電子封裝件,其中,該電子元件係具有相對之作用面與非作用面,且該作用面具有複數電極墊。
- 如申請專利範圍第2項所述之電子封裝件,其中,該第一表面與該作用面齊平。
- 如申請專利範圍第2項所述之電子封裝件,其中,該第二表面與該非作用面齊平。
- 如申請專利範圍第1項所述之電子封裝件,其中,該第一導電體係為金屬柱或金屬球。
- 如申請專利範圍第1項所述之電子封裝件,復包括形成於該絕緣層之第二表面上的第二線路結構,其電性連接該第一導電體。
- 如申請專利範圍第6項所述之電子封裝件,其中,該第二線路結構係電性連接該電子元件。
- 如申請專利範圍第1項所述之電子封裝件,復包括對應形成於該第二穿孔中之至少一第二導電體。
- 如申請專利範圍第8項所述之電子封裝件,其中,該第二導電體電性連接該第一導電體。
- 如申請專利範圍第8項所述之電子封裝件,其中,該第二導電體係為金屬柱。
- 如申請專利範圍第1項所述之電子封裝件,復包括堆疊於該絕緣層之第一表面或第二表面上的電子封裝結構。
- 一種電子封裝件之製法,係包括:提供一嵌埋有至少一電子元件之絕緣層,該絕緣層具有相對之第一表面與第二表面;於該絕緣層中形成連通至該第一表面之至少一第一穿孔;形成第一導電體於該第一穿孔中;形成第一線路結構於該絕緣層之第一表面上,且該第一線路結構電性連接該電子元件與該第一導電體;以及於該絕緣層中形成對應連通該第一穿孔和第二表面之第二穿孔,令該第一穿孔與第二穿孔構成通孔。
- 如申請專利範圍第12項所述之電子封裝件之製法,其中,該絕緣層係以模壓製程或壓合製程形成者。
- 如申請專利範圍第12項所述之電子封裝件之製法,其中,該電子元件係具有相對之作用面與非作用面,且該作用面具有複數電極墊。
- 如申請專利範圍第14項所述之電子封裝件之製法,其中,該第一表面與該作用面齊平。
- 如申請專利範圍第14項所述之電子封裝件之製法,其中,該第二表面與該非作用面齊平。
- 如申請專利範圍第12項所述之電子封裝件之製法,其中,該第一穿孔係以雷射鑽孔、機械鑽孔或蝕刻方式形成者。
- 如申請專利範圍第12項所述之電子封裝件之製法,其中,該第一導電體係為金屬柱或金屬球。
- 如申請專利範圍第12項所述之電子封裝件之製法,其中,該第二穿孔係以雷射鑽孔、機械鑽孔或蝕刻方式形成者。
- 如申請專利範圍第12項所述之電子封裝件之製法,復包括形成第二線路結構於該絕緣層之第二表面上,且該第二線路結構電性連接該第一導電體。
- 如申請專利範圍第20項所述之電子封裝件之製法,其中,該第二線路結構係電性連接該電子元件。
- 如申請專利範圍第12項所述之電子封裝件之製法,復包括形成第二導電體於該第二穿孔中。
- 如申請專利範圍第22項所述之電子封裝件之製法,其中,該第二導電體電性連接該第一導電體。
- 如申請專利範圍第22項所述之電子封裝件之製法,其中,該第二導電體係為金屬柱。
- 如申請專利範圍第12項所述之電子封裝件之製法,復包括堆疊電子封裝結構於該絕緣層之第一表面或第二表面上。
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TW103135624A TWI571185B (zh) | 2014-10-15 | 2014-10-15 | 電子封裝件及其製法 |
CN201410729628.5A CN105655304A (zh) | 2014-10-15 | 2014-12-04 | 电子封装件及其制法 |
US14/862,457 US9899303B2 (en) | 2014-10-15 | 2015-09-23 | Electronic package and fabrication method thereof |
US15/866,144 US10403567B2 (en) | 2014-10-15 | 2018-01-09 | Fabrication method of electronic package |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI801446B (zh) * | 2018-05-04 | 2023-05-11 | 南韓商三星電機股份有限公司 | 印刷電路板 |
TWI830566B (zh) * | 2022-12-30 | 2024-01-21 | 恆勁科技股份有限公司 | 整合有電感線路結構之封裝載板及其製造方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI571185B (zh) | 2014-10-15 | 2017-02-11 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
US20220157524A1 (en) * | 2016-02-25 | 2022-05-19 | 3D Glass Solutions, Inc. | 3D Capacitor and Capacitor Array Fabricating Photoactive Substrates |
US10529698B2 (en) * | 2017-03-15 | 2020-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of forming same |
US10504841B2 (en) * | 2018-01-21 | 2019-12-10 | Shun-Ping Huang | Semiconductor package and method of forming the same |
TWI645527B (zh) * | 2018-03-06 | 2018-12-21 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
CN111106013B (zh) * | 2019-10-31 | 2022-03-15 | 广东芯华微电子技术有限公司 | Tmv结构的制备方法、大板扇出型异构集成封装结构及其制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200820417A (en) * | 2006-10-27 | 2008-05-01 | Shinko Electric Ind Co | Semiconductor package and stacked layer type semiconductor package |
TW201136474A (en) * | 2006-02-22 | 2011-10-16 | Ibiden Co Ltd | Printed wiring board and process for producing the same |
TW201427523A (zh) * | 2012-12-27 | 2014-07-01 | Zhen Ding Technology Co Ltd | 晶片封裝結構、具有內埋元件的電路板及其製作方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1173399C (zh) * | 2001-01-04 | 2004-10-27 | 矽品精密工业股份有限公司 | 具溢胶防止装置的半导体封装件 |
JP2004179419A (ja) * | 2002-11-27 | 2004-06-24 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4226428B2 (ja) * | 2003-09-29 | 2009-02-18 | パナソニック株式会社 | 導電性ペースト充填方法、導電性ペースト充填装置 |
WO2008015228A2 (en) * | 2006-08-03 | 2008-02-07 | Basell Polyolefine Gmbh | Process for the polyolefin finishing |
US7713866B2 (en) * | 2006-11-21 | 2010-05-11 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20100044089A1 (en) * | 2007-03-01 | 2010-02-25 | Akinobu Shibuya | Interposer integrated with capacitors and method for manufacturing the same |
US8476735B2 (en) * | 2007-05-29 | 2013-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Programmable semiconductor interposer for electronic package and method of forming |
US7666711B2 (en) * | 2008-05-27 | 2010-02-23 | Stats Chippac, Ltd. | Semiconductor device and method of forming double-sided through vias in saw streets |
US20100017118A1 (en) * | 2008-07-16 | 2010-01-21 | Apple Inc. | Parking & location management processes & alerts |
US8704350B2 (en) * | 2008-11-13 | 2014-04-22 | Samsung Electro-Mechanics Co., Ltd. | Stacked wafer level package and method of manufacturing the same |
TWI492349B (zh) * | 2010-09-09 | 2015-07-11 | 矽品精密工業股份有限公司 | 晶片尺寸封裝件及其製法 |
KR101719630B1 (ko) * | 2010-12-21 | 2017-04-04 | 삼성전자 주식회사 | 반도체 패키지 및 그를 포함하는 패키지 온 패키지 |
US8552485B2 (en) * | 2011-06-15 | 2013-10-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having metal-insulator-metal capacitor structure |
US8765549B2 (en) * | 2012-04-27 | 2014-07-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor for interposers and methods of manufacture thereof |
TWI571185B (zh) * | 2014-10-15 | 2017-02-11 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
-
2014
- 2014-10-15 TW TW103135624A patent/TWI571185B/zh active
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-
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201136474A (en) * | 2006-02-22 | 2011-10-16 | Ibiden Co Ltd | Printed wiring board and process for producing the same |
TW200820417A (en) * | 2006-10-27 | 2008-05-01 | Shinko Electric Ind Co | Semiconductor package and stacked layer type semiconductor package |
TW201427523A (zh) * | 2012-12-27 | 2014-07-01 | Zhen Ding Technology Co Ltd | 晶片封裝結構、具有內埋元件的電路板及其製作方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI801446B (zh) * | 2018-05-04 | 2023-05-11 | 南韓商三星電機股份有限公司 | 印刷電路板 |
TWI830566B (zh) * | 2022-12-30 | 2024-01-21 | 恆勁科技股份有限公司 | 整合有電感線路結構之封裝載板及其製造方法 |
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US20180130727A1 (en) | 2018-05-10 |
US9899303B2 (en) | 2018-02-20 |
US10403567B2 (en) | 2019-09-03 |
TW201615066A (en) | 2016-04-16 |
US20160111359A1 (en) | 2016-04-21 |
CN105655304A (zh) | 2016-06-08 |
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