TWI548030B - 導電盲孔結構及其製法 - Google Patents
導電盲孔結構及其製法 Download PDFInfo
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Description
本發明係有關一種貫穿膠體(Through molding via,TMV)之技術,尤指一種導電盲孔結構及其製法。
貫穿膠體(Through molding via,TMV)之技術,目前已廣泛運用於半導體領域,其主要技術係利用雷射燒灼方式於封裝膠體表面進行開孔製程,以顯露出位於封裝膠體下之電性接點(如線路或電性連接墊)。
例如,製作扇出型(Fan-Out,FO)封裝堆疊(Package on Package,POP)結構時,便會使用該技術。第1A至1D圖係為習知FO-POP封裝結構之導電盲孔結構之製法的剖面示意圖。
如第1A圖所示,一具有複數線路層100之封裝基板10係設於一支撐件9上,且該封裝基板10上設有一晶片11與一封裝膠體12,並使該封裝膠體12包覆該晶片11。
如第1B圖所示,形成一介電層13於該封裝膠體12上。
如第1C圖所示,利用雷射鑽孔方式貫穿該介電層13與該封裝膠體12,以形成複數盲孔130,令最上層之部分
該線路層100(即電性連接墊)外露於該盲孔130。
如第1D圖所示,電鍍形成如銅之導電材14於該介電層13上與該盲孔130中,使該介電層13上之導電材14作為扇出型線路重佈層141,且於該盲孔130中之導電材14作為導電盲孔140,以令該導電盲孔140電性連接該線路層100與該線路重佈層141。
於後續製程中,如第1E圖所示,形成一絕緣保護層15於該線路重佈層141與該介電層13上,且該絕緣保護層15形成有複數開孔150,使該線路重佈層141之電性接觸墊142外露於該些開孔150。之後,形成一表面處理層16於該電性接觸墊142上,以結合複數如銲球之導電元件(圖略)於該表面處理層16上,俾製成半導體封裝件1。最後,移除該支撐件9。
目前該盲孔130的最大孔徑R為100至200微米(um),如第1C圖所示,隨著該半導體封裝件1之體積朝輕薄短小及功能性增強之趨勢設計,該盲孔130的孔徑將愈做愈小,且佈孔密度亦愈高,以符合裝結構體積輕薄短小、及功能性增強之需求。
惟,前述習知導電盲孔140之製法中,使用雷射鑽孔方式形成該盲孔130,使該盲孔130之壁面130a呈現不平整表面,如第1C’圖所示,該盲孔130之壁面130a之粗糙度(Ra)係為50微米(um),亦即該盲孔130之壁面130a極為粗糙,故該導電盲孔140將因粗糙之該壁面130a而形成鋸齒狀表面,如第1D圖所示,導致電荷容易集中於該
導電盲孔140之表面突起處,以致於容易因電阻過高而產生焦耳熱,進而造成線路斷路之問題。
再者,於電鍍銅時,會先濺鍍一極薄之銅材晶種層(seed layer,圖略),但銅材與該封裝膠體12的介面不親,故當該盲孔130之壁面130a極為粗糙時,該晶種層之銅材容易脫落(peeling),致使後續電鍍之導電材14無法有效附著於該盲孔130之壁面130a上而發生脫層現象,導致該半導體封裝件1之可靠度不佳。
又,遂有另一方式,係於該壁面130a上鍍覆一鈍化層(passvation layer)12’,以形成另一盲孔120,如第1C”圖所示,而藉以改善孔壁之粗糙度,之後再形成該導電材14於該盲孔120中。然而,該鈍化層12’之厚度t僅1至2微米(um),並無法有效填補該壁面130a之粗糙度,亦即該盲孔120之壁面120a仍然粗糙,即該盲孔120之壁面120a仍無法避免線路斷路與銅材脫落之問題。
因此,如何克服上述習知技術的種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明係提供一種導電盲孔結構,係包括:封裝膠體,係具有連通至該封裝膠體外部之複數穿孔;介電層,係形成於該封裝膠體上並填充該些穿孔,且於該些穿孔中形成有盲孔;以及導電材,係填充於該盲孔中。
本發明亦提供一種導電盲孔結構之製法,係包括:於
一封裝膠體中形成連通至該封裝膠體外部之複數穿孔;形成介電層於該封裝膠體上,且該介電層填滿該些穿孔;形成盲孔於該介電層上,且該盲孔係位於該些穿孔中;以及形成導電材於該盲孔中。
前述之導電盲孔結構及其製法中,該些穿孔係以雷射鑽孔方式形成者,使該些穿孔之壁面係為非平整面,且該些穿孔之壁面之平均粗糙度係為2至60微米。
前述之導電盲孔結構及其製法中,該穿孔之最大孔徑係為40至400微米。
前述之導電盲孔結構及其製法中,該介電層之材質係為感光性材質。
前述之導電盲孔結構及其製法中,該介電層於該些穿孔中之厚度係為30至50微米。
前述之導電盲孔結構及其製法中,該盲孔係以曝光方式形成者,使該盲孔之壁面係為平整面,且該盲孔之最大孔徑係為30至350微米。
前述之導電盲孔結構及其製法中,該導電材係以電鍍方式形成者,例如,該導電材係填滿該盲孔。
另外,前述之導電盲孔結構及其製法中,該導電材係為銅材。
由上可知,本發明之導電盲孔結構及其製法,係藉由先將該介電層填滿該些穿孔,再形成該盲孔於該些穿孔中之介電層中,以改善該些穿孔之壁面之粗糙度,而使該盲孔之壁面呈平整面。因此,該導電材於該盲孔中不會產生
電荷集中於孔壁突起處之現象,故能避免當電荷累積過多而產生焦耳熱以造成線路斷路之問題。
再者,由於銅材與該介電層的介面極親,故銅材不會從該盲孔之壁面上脫落,因而能避免該導電材脫層之問題。
1,2‧‧‧半導體封裝件
10‧‧‧封裝基板
100,200‧‧‧線路層
11‧‧‧晶片
12,22‧‧‧封裝膠體
12’‧‧‧鈍化層
120,130,230‧‧‧盲孔
120a,130a,220a,230a‧‧‧壁面
13,23‧‧‧介電層
14,24‧‧‧導電材
140,240,240’‧‧‧導電盲孔
141,241‧‧‧線路重佈層
142,242‧‧‧電性接觸墊
15,25‧‧‧絕緣保護層
150,250‧‧‧開孔
16,26‧‧‧表面處理層
20‧‧‧承載件
21‧‧‧電子元件
220‧‧‧穿孔
9‧‧‧支撐件
D,R,R’‧‧‧孔徑
T,t‧‧‧厚度
第1A至1D圖係為習知導電盲孔結構之製法的剖面示意圖;其中,第1C’圖係為第1C圖之局部放大圖,第1C”圖係為第1C’圖之另一方式;第1E圖係為接續第1D圖之後續製程之剖面示意圖。
第2A至2D圖係為本發明之導電盲孔結構之製法的剖面示意圖;其中,第2C’圖係為第2C圖之局部放大圖2D’;以及
第2E圖係為接續第2D圖之後續製程之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”
及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2D圖係為本發明之導電盲孔結構之製法的剖面示意圖。
如第2A圖所示,一承載件20係設於一支撐件9上,且該承載件20上設有一電子元件21與一封裝膠體22,並使該封裝膠體22包覆該電子元件21。之後,於該封裝膠體22中形成連通至該封裝膠體22外部之複數穿孔220。
於本實施例中,該承載件20係為封裝基板,其具有複數線路層200,以令最上層之部分該線路層200外露於該些穿孔220。於其它實施例中,該承載件20亦可為中介板、半導體結構或導線架等,並不限於此。
再者,該穿孔220之最大孔徑R’係為40至400微米(um),且係以雷射鑽孔方式形成該些穿孔220,故該些穿孔220之壁面220a係為非平整面,如第2C’圖所示之不規則之凹凸面,且該些穿孔220之壁面220a之平均粗糙度(Ra)係為2至60微米(um)。
又,該電子元件21係為半導體元件,如主動元件或被動元件,並可使用複數個半導體元件,且可選自主動元件、被動元件或其組合,該主動元件係例如:晶片,而該被動元件係例如:電阻、電容及電感。
另外,有關該承載件20、電子元件21與封裝膠體22之組構結合之方式繁多,並無特別限制。
如第2B圖所示,形成一介電層23於該封裝膠體22上,且該介電層23填滿該些穿孔220。
於本實施例中,該介電層23之材質係為感光性材質。
如第2C圖所示,形成複數盲孔230於該介電層23上,且該盲孔230之位置係位於該些穿孔220中。
於本實施例中,最上層之該線路層200係外露於該盲孔230。
再者,係以曝光方式形成該盲孔230,故該盲孔230之壁面230a係為平整面,如第2C’圖所示之環形弧面。
又,該盲孔230係為錐形孔,且該盲孔230之最大孔徑D係為30至350微米(um)。
另外,該介電層23於該些穿孔220中之厚度T係為30至50微米(um),如第2C’圖所示。
如第2D圖所示,形成導電材24於該介電層23上與該盲孔230中,使該介電層23上之導電材24作為一線路重佈層241(Redistribution layer,RDL),且於該盲孔230中之導電材24作為一導電盲孔240。
於本實施例中,利用電鍍或沉積方式形成該導電材24,以填滿該盲孔230。或者,於其它實施例中,如第2D’圖所示之導電盲孔240’,該導電材24未填滿該盲孔230。
再者,該導電盲孔240,240’係電性連接該最上層之該線路層200與該線路重佈層241。
又,於後續製程中,如第2E圖所示,形成一絕緣保護層25於該線路重佈層241與該介電層23上,且該絕緣
保護層25形成有複數開孔250,使該線路重佈層241之電性接觸墊242外露於該些開孔250,俾供結合複數如銲球之導電元件(圖略)於該電性接觸墊242上,以製成半導體封裝件2,且該些導電元件係用以接至其它如封裝件、半導體元件或封裝基板之電子裝置(圖略)上。最後,移除該支撐件9。
另外,亦可先形成一表面處理層26於該電性接觸墊242上,再結合該導電元件於該表面處理層26上。
本發明之製法中,係藉由先將該介電層23填滿該些穿孔220,再利用曝光方式形成該盲孔230,以改善該些穿孔220之壁面220a之粗糙度。
再者,由於利用曝光方式形成該盲孔230,使該介電層23於該些穿孔220中之厚度T夠厚,而使該盲孔230之壁面230a得以呈平整面,因而電鍍銅所製之導電盲孔240,240’不會產生電荷集中於孔壁突起處之現象,進而能避免當電荷累積過多而產生焦耳熱以造成線路斷路之問題,故相較於習知技術,該導電盲孔240,240’之品質更佳,且使該半導體封裝件2能正常運作。
又,由於銅材與該介電層23的介面極親,故於電鍍或沉積該導電材24時,所濺鍍之銅材晶種層(seed layer,圖略)之銅材不會從該盲孔230之壁面230a上脫落,使該導電材24不會脫層,因而能提升該導電盲孔240,240’之品質,以利於該半導體封裝件2之信賴性提升。
本發明係提供一種導電盲孔結構,其包括:一封裝膠
體22、形成於該封裝膠體22上之一介電層23、以及導電材24。
所述之封裝膠體22係具有連通至該封裝膠體22外部之複數穿孔220,該些穿孔220之壁面220a係為非平整面,且該些穿孔220之壁面220a之平均粗糙度係為2至60微米,又該穿孔220之最大孔徑R’係為40至400微米。
所述之介電層23之材質係為感光性材質,其復填充該些穿孔220並於該些穿孔220中形成有盲孔230,該盲孔230之壁面230a係為平整面,且該盲孔230之最大孔徑D係為30至350微米。
所述之導電材24係填充於該盲孔230中,以作為導電盲孔240,240’。
於一實施例中,該介電層23於該些穿孔220中之厚度T係為30至50微米(um)。
於一實施例中,該導電材24係填滿該盲孔230。
於一實施例中,該導電材24係為銅材。
綜上所述,本發明之導電盲孔結構及其製法,主要藉由該介電層填平該些穿孔之粗糙壁面,以形成平整壁面之盲孔,故不僅能避免線路斷路與銅材脫落之問題,以提升該導電盲孔之品質,且不會增加材料成本。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範
圍所列。
20‧‧‧承載件
200‧‧‧線路層
21‧‧‧電子元件
22‧‧‧封裝膠體
23‧‧‧介電層
230‧‧‧盲孔
24‧‧‧導電材
240‧‧‧導電盲孔
241‧‧‧線路重佈層
9‧‧‧支撐件
Claims (20)
- 一種導電盲孔結構,係包括:封裝膠體,係具有連通至該封裝膠體外部之複數穿孔;介電層,係形成於該封裝膠體上並填充該些穿孔,且於該些穿孔中形成有盲孔;以及導電材,係填充於該盲孔中。
- 如申請專利範圍第1項所述之導電盲孔結構,其中,該些穿孔之壁面係為非平整面。
- 如申請專利範圍第1項所述之導電盲孔結構,其中,該些穿孔之壁面之平均粗糙度係為2至60微米。
- 如申請專利範圍第1項所述之導電盲孔結構,其中,該穿孔之最大孔徑係為40至400微米。
- 如申請專利範圍第1項所述之導電盲孔結構,其中,該介電層之材質係為感光性材質。
- 如申請專利範圍第1項所述之導電盲孔結構,其中,該介電層於該些穿孔中之厚度係為30至50微米。
- 如申請專利範圍第1項所述之導電盲孔結構,其中,該盲孔之壁面係為平整面。
- 如申請專利範圍第1項所述之導電盲孔結構,其中,該盲孔之最大孔徑係為30至350微米。
- 如申請專利範圍第1項所述之導電盲孔結構,其中,該導電材係為銅材。
- 如申請專利範圍第1項所述之導電盲孔結構,其中, 該導電材係填滿該盲孔。
- 一種導電盲孔結構之製法,係包括:於一封裝膠體中形成連通至該封裝膠體外部之複數穿孔;形成介電層於該封裝膠體上,且該介電層填滿該些穿孔;形成盲孔於該介電層上,且該盲孔係位於該些穿孔中;以及形成導電材於該盲孔中。
- 如申請專利範圍第11項所述之導電盲孔結構之製法,其中,該些穿孔係以雷射鑽孔方式形成者。
- 如申請專利範圍第11項所述之導電盲孔結構之製法,其中,該些穿孔之壁面之平均粗糙度係為2至60微米。
- 如申請專利範圍第11項所述之導電盲孔結構之製法,其中,該穿孔之最大孔徑係為40至400微米。
- 如申請專利範圍第11項所述之導電盲孔結構之製法,其中,該介電層之材質係為感光性材質。
- 如申請專利範圍第11項所述之導電盲孔結構之製法,其中,該介電層於該些穿孔中之厚度係為30至50微米。
- 如申請專利範圍第11項所述之導電盲孔結構之製法,其中,該盲孔係以曝光方式形成者。
- 如申請專利範圍第11項所述之導電盲孔結構之製法,其中,該盲孔之最大孔徑係為30至350微米。
- 如申請專利範圍第11項所述之導電盲孔結構之製法, 其中,該導電材係為銅材。
- 如申請專利範圍第11項所述之導電盲孔結構之製法,其中,該導電材係以電鍍方式形成者。
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