TWI816267B - 內埋式封裝結構 - Google Patents

內埋式封裝結構 Download PDF

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TWI816267B
TWI816267B TW110148842A TW110148842A TWI816267B TW I816267 B TWI816267 B TW I816267B TW 110148842 A TW110148842 A TW 110148842A TW 110148842 A TW110148842 A TW 110148842A TW I816267 B TWI816267 B TW I816267B
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metal
sintered
packaging structure
sintered metal
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張景堯
王友志
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財團法人工業技術研究院
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Abstract

本發明提供一種內埋式封裝結構，包含晶片、燒結金屬層、封裝層以及導電柱。晶片包含金屬接合層。燒結金屬層接合至金屬接合層。封裝層包覆晶片。導電柱形成於封裝層的盲孔中，且導電柱經由燒結金屬層與金屬接合層電性連接。

Description

內埋式封裝結構
本發明係關於一種電子元件的封裝結構。
隨著積體電路的製造技術不斷進步，連帶相關的封裝技術也發展出許多新穎的封裝方法。近來，利用與製造電路板相關之技術的內埋式封裝(又稱嵌入式封裝，Embedded Packaging)開始被注意並廣泛應用於功率半導體元件的系統單封裝(SIP：System in Package)。因應穿戴式電子裝置和可攜式裝置是未來電子產品的發展趨勢，具備低成本且體積小等優勢的內埋式封裝富有研究前景。內埋式封裝結構通常包含埋入至介電材料內的半導體晶片以及在介電材料外部的訊號傳輸電路，並且半導體晶片和訊號傳輸電路之間的電性連接透過金屬導電柱(Via)來實現。通常，會藉由雷射鑽孔製程於介電材料中形成盲孔以顯露出半導體晶片的電性連接點，接著在盲孔中填入金屬以形成和電性連接點接觸的金屬導電柱。
在雷射鑽孔製程中，所使用之高功率雷射可能會轟擊到作為電性連接點的金屬層甚至晶片本身，因此內埋式封裝的製程包含有在金屬層上方形成雷射鑽孔阻擋層(Stop layer)之步驟。阻擋層之材料雖然具有高熔點可避免被雷射擊穿，但其低熱傳導率及高電阻的特性仍不利於半導體元件的性能表現，例如因雷射轟擊而蓄積在阻擋層的熱可能會影響半導體晶片的電性。此外，由於阻擋層是在將晶圓切割成多個晶片的步驟前就已經形成，因此晶圓切割後，阻擋層容易因為內應力導致翹曲而從晶片上脫落。
鑒於上述問題，本發明提供一種內埋式封裝結構，有助於解決現有與內埋式封裝結構之阻擋層相關的問題。
本發明一實施例所揭露之內埋式封裝結構包含一晶片、一燒結金屬層、一封裝層以及一導電柱。晶片包含一金屬接合層。燒結金屬層接合至金屬接合層。封裝層包覆晶片。導電柱形成於封裝層的一盲孔中，且導電柱經由燒結金屬層與金屬接合層電性連接。
本發明另一實施例所揭露之內埋式封裝結構包含一晶片、一燒結金屬層、一銅箔層、一封裝層以及一導電柱。晶片包含一金屬接合層。燒結金屬層接合至金屬接合層。銅箔層接合至燒結金屬層，燒結金屬層介於金屬接合層與銅箔層之間。封裝層包覆晶片。導電柱形成於封裝層的一盲孔中，且導電柱經由燒結金屬層與金屬接合層電性連接。
根據本發明揭露之內埋式封裝結構，包含有燒結金屬層接合至晶片的金屬接合層。燒結金屬層具有良好的導熱性與導電性而能作為雷射鑽孔製程的阻擋層。由於採用燒結金屬層作為阻擋層，因而能夠在晶圓切割成多個晶片後再接著於晶片上形成阻擋層，相較於現有技術必須在晶圓切割前就要形成阻擋層，燒結金屬層具有較小的內應力而不容易翹曲破裂甚至從晶片上脫落。此外，燒結金屬層具有次微米疏孔結構，其有利於增加導電柱與燒結金屬層之間的接觸面積，進而提升接合強度與封裝結構可靠度。
以上關於本發明內容之說明及以下實施方式之說明係用以示範與解釋本發明之原理，並提供本發明之專利申請範圍更進一步之解釋。
於以下實施方式中詳細敘述本發明之詳細特徵及優點，其內容足以使任何熟習相關技藝者瞭解本發明之技術內容並據以實施，且根據本說明書所揭露的內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易理解本發明。以下實施例係進一步詳細說明本發明之觀點，但非以任何觀點限制本發明之範疇。
請參照圖1和圖2，其中圖1為根據本發明一實施例之內埋式封裝結構的示意圖，圖2為圖1之內埋式封裝結構的局部放大示意圖。在本實施例中，內埋式封裝結構1a包含基座10、晶片20、燒結金屬層30、封裝層40、導電柱50、訊號傳輸電路層60以及導通孔(Plating Through Hole)70。內埋式封裝結構1a的基座10可以接合至印刷電路板(未另繪示)。
基座10例如但不限於是金屬基座，其材料可包含鋁、鉛或銅。晶片20包含主體210以及金屬接合層220。晶片20例如但不限於是功率半導體元件、RF射頻元件、絕緣柵雙極電晶體(IGBT)、功率二極體或其他含有半導體材料(如Si、GaAs、SiC、GaN、Ga 2O 3)之電子元件，其與基座10接合。進一步來說，金屬接合層220可以是晶片20的接觸電極(Contact Pad)，且主體210可以是晶片20中的含矽半導體材料部分或是除了金屬接合層220以外的其他部分。
晶片20之金屬接合層220位於主體210的表面上。詳細來說，金屬接合層220形成於主體210的頂面212。換句話說，晶片20的一側接合至基座10且相對另一側提供有金屬接合層220。金屬接合層220可包含鋁銅或鋁矽合金金屬層，其表面再由一個或兩個以上子層組成的堆疊層結構，例如包含銅層、銅/金、鎳/鈀/金、鎳/銀等堆疊層結構；金或銀為最表面層，用以保護金屬接合層避免氧化。晶片20還包含下金屬接合層230，下金屬接合層230接觸主體210的底面211，並且透過金屬黏著層21接合至基座10。金屬黏著層21可以是焊料(solder)或燒結金屬(燒結銀、燒結銅、燒結銀銅、燒結鎳)。
燒結金屬層30接合至晶片20之金屬接合層220。燒結金屬層30包含藉由加熱與壓製等作業程序而熔接在一起的金屬固體。更具體來說，燒結金屬層30可包含燒結銅、燒結銀或它們的組合。燒結金屬層30可具有適於傳輸電訊號的物理特性，例如燒結金屬層30的厚度可為60.0微米(μm)以下，燒結金屬層30的厚度可為10.0微米至30.0微米，熱傳導率可為190.0 W/m·K以上，以及電阻率可為2.50Í10 -8Ω·m至8.0Í10 -8Ω⋅m。例如燒結金屬層30的厚度可為10.0微米至30.0微米，以及電阻率可為2.0Í10 -8Ω⋅m至6.0Í10 -8Ω⋅m。圖3為根據本發明一實施例之燒結金屬層的電子顯微影像，其中燒結金屬層30具有次微米疏孔結構。
封裝層40包覆晶片20。詳細來說，封裝層40形成於基座10上並且覆蓋晶片20與燒結金屬層30。封裝層40可包含一或多層介電材料，其中介電材料例如但不限於是氧化矽或氧化氮。
導電柱50形成於封裝層40的盲孔410中。具體來說，可藉由鑽孔製程於封裝層40形成顯露出燒結金屬層30的盲孔410，接著導電柱50形成於盲孔410內，並且導電柱50經由燒結金屬層30與晶片20的金屬接合層220電性連接。
訊號傳輸電路層60形成於封裝層40與導電柱50上方，並且導電柱50與訊號傳輸電路層60電性連接。訊號傳輸電路層60可與基座10由相同金屬材料製成。訊號傳輸電路層60上方可另外覆蓋有電性絕緣材料(未另繪示)，以確保漏電流(Leakage Current)的安全設計範圍。
導通孔70延伸貫穿封裝層40。導通孔70於孔壁面上形成有金屬層將訊號傳輸電路層60連接至基座10，且此金屬層可與基座10和訊號傳輸電路層60用相同金屬材料製成。
以下描述內埋式封裝結構1a的製造方法。圖4至圖7為製造圖1之內埋式封裝結構的流程示意圖。如圖4所示，提供基座10、設置於基座10之上表面110的晶片20以及與晶片20之金屬接合層220接合的燒結金屬層30，並且燒結金屬層30作為後續雷射鑽孔製程的阻擋層。詳細來說，可將已完成積體電路製程的晶圓用鑽石刀切割以獲得晶片20，爾後將晶片20接合至基座10之上表面110，接著再於晶片20上形成燒結金屬層30。晶片20與基座10的接合例如是晶片20之主體210的底面211包含下金屬接合層230經由金屬黏著層21接合至基座10的上表面110。
可以採用下述幾種方法於晶片20上形成燒結金屬層30。一種方法係先用習知的燒結(Sintering)製程製作燒結金屬並將其塑形成片狀；接著，將片狀燒結金屬置於晶片20之金屬接合層220上，並用220℃到300℃的溫度進行熱壓以將燒結金屬層30與晶片20接合。另一種方法是將添加有金屬粉末的漿料塗布於金屬接合層220上，並接著用220℃到300℃的溫度進行熱壓，以形成接合於金屬接合層220的燒結金屬層30。對於上述兩種方法來說，片狀燒結金屬或含金屬粉末之漿料提供於設置有金屬接合層220的位置，因此燒結金屬層30與對應金屬接合層220具有實質上相同或較小的圖案面積，也就是說從俯視視角來看燒結金屬層30位置與金屬接合層220位置圖案可以重合，或燒結金屬層30位置的圖案面積小於金屬接合層220位置的圖案面積。
如圖5所示，於基座10上形成封裝層40覆蓋晶片20、燒結金屬層30和基座10，並且於封裝層40上形成金屬層61作為後續形成之訊號傳輸電路層60的一部分。封裝層40的形成可以採用現有的化學氣相沉積技術樹脂(resin)或含玻璃纖維樹脂或二者之堆疊層結構，並且金屬層61的形成可以採用銅箔壓合或濺鍍技術或電鍍技術。
如圖6所示，於封裝層40形成盲孔410和導通孔70。詳細來說，可藉由雷射鑽孔製程在指定區域移除封裝層40和金屬層61以形成盲孔(Blind Via、Blind Hole)410，以及在另一指定區域機械鑽孔移除基座10、封裝層40和金屬層61以形成導通孔(PTH，Plating Through Hole)70。其中盲孔410顯露出燒結金屬層30。燒結金屬層30具有良好導電性因而對訊號傳遞的阻礙較小。此外，燒結金屬層30還具有高熱傳導率與高熔點之特性，因而不容易被雷射擊穿，並且因雷射轟擊產生的熱能被快速傳導而不會蓄積在晶片20之金屬接合層220周圍，從而有助於增加晶片20的使用壽命。
如圖7所示，於盲孔410內形成導電柱50，並且於導通孔70的孔壁面上形成金屬層71。詳細來說，可藉由電鍍製程於盲孔410內和導通孔70孔壁面上沉積例如銅、鈦、鎢等金屬，以分別形成導電柱50和金屬層71。圖6中的金屬層61上方也會形成有金屬層71，且金屬層61、71可被進一步圖案化以形成訊號傳輸電路層60。所述圖案化可以藉由微影製程和蝕刻製程來實現。在本實施例中，相較於現有技術中使用之阻擋層包含電鍍金屬或無電鍍(又稱化學鍍，Electroless plating)金屬，燒結金屬層30具有次微米疏孔結構，其有利於增加含有電鍍銅之導電柱50與燒結金屬層30之間的接觸面積，進而提升接合強度與封裝結構可靠度。
內埋式封裝結構可進一步包含接合至燒結金屬層的銅箔。參照圖8和圖9，其中圖8為根據本發明另一實施例之內埋式封裝結構的示意圖，且圖9為圖8之內埋式封裝結構的局部放大示意圖。在本實施例中，內埋式封裝結構1b包含基座10、晶片20、燒結金屬層30、封裝層40、導電柱50、訊號傳輸電路層60以及導通孔70。上述物件的具體結構可以參照圖1以及前述與內埋式封裝結構1a有關的描述，以下將不再贅述。
本實施例之內埋式封裝結構1b進一步包含銅箔層80。銅箔層80接合至燒結金屬層30上方，銅箔層80的厚度為50.0微米(μm)至100.0微米(μm)。燒結金屬層30介於晶片20之金屬接合層220與銅箔層80之間，並且銅箔層80接觸導電柱50，。將銅箔層80與燒結金屬層30接合的方法例如有：銅箔層80貼附於片狀燒結金屬，並進行熱壓以將兩者接合；或者，銅箔層80置於添加有金屬粉末的漿料中，並進行熱壓將銅箔層80與燒結金屬層30兩者接合。以燒結金屬層30和銅箔層80所組成之雙層結構作為雷射鑽孔阻擋層能更加地防止雷射對晶片20造成熱損傷。
綜上所述，根據本發明所揭露之內埋式封裝結構，包含有燒結金屬層接合至晶片的金屬接合層。燒結金屬層具有良好的導熱性與導電性而能作為雷射鑽孔製程的阻擋層。由於採用燒結金屬層作為阻擋層，因而能夠在晶圓切割成多個晶片後再接著於晶片上形成阻擋層，相較於現有技術必須在晶圓切割前就要形成阻擋層，燒結金屬層具有較小的內應力而不容易翹曲破裂甚至從晶片上脫落。
此外，燒結金屬層具有次微米疏孔結構，其有利於增加導電柱與燒結金屬層之間的接觸面積，進而提升接合強度與封裝結構可靠度。
本發明之實施例揭露雖如上所述，然並非用以限定本發明，任何熟習相關技藝者，在不脫離本發明之精神和範圍內，舉凡依本發明申請範圍所述之形狀、構造、特徵及精神當可做些許之變更，因此本發明之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。
1a、1b:內埋式封裝結構 10:基座 110:上表面 20:晶片 210:主體 211:底面 212:頂面 220:金屬接合層 230:下金屬接合層 21:金屬黏著層 30:燒結金屬層 40:封裝層 410:盲孔 50:導電柱 60:訊號傳輸電路層 61:金屬層 70:導通孔 71:金屬層 80:銅箔層
圖1為根據本發明一實施例之內埋式封裝結構的示意圖。 圖2為圖1之內埋式封裝結構的局部放大示意圖。 圖3為根據本發明一實施例之燒結金屬層的電子顯微影像。 圖4至圖7為製造圖1之內埋式封裝結構的流程示意圖。 圖8為根據本發明另一實施例之內埋式封裝結構的示意圖。 圖9為圖8之內埋式封裝結構的局部放大示意圖。
1a:內埋式封裝結構
10:基座
110:上表面
20:晶片
210:主體
211:底面
212:頂面
220:金屬接合層
230:下金屬接合層
21:金屬黏著層
30:燒結金屬層
40:封裝層
410:盲孔
50:導電柱
60:訊號傳輸電路層
70:導通孔

Claims (15)

  1. 一種內埋式封裝結構，包含：一晶片，包含一金屬接合層；一燒結金屬層，接合至該金屬接合層；一封裝層，包覆該晶片；以及一導電柱，形成於該封裝層的一盲孔中，且該導電柱經由該燒結金屬層與該金屬接合層電性連接。
  2. 如請求項1所述之內埋式封裝結構，其中該燒結金屬層的厚度為60.0微米(μm)以下。
  3. 如請求項1所述之內埋式封裝結構，其中該燒結金屬層包含燒結銅、燒結銀或燒結銀銅。
  4. 如請求項1所述之內埋式封裝結構，其中該燒結金屬層具有與該金屬接合層實質上相同或較小的圖案面積。
  5. 如請求項1所述之內埋式封裝結構，其中該導電柱包含電鍍銅。
  6. 如請求項1所述之內埋式封裝結構，其中該封裝層的該盲孔經由雷射鑽孔形成。
  7. 如請求項1所述之內埋式封裝結構，更包含一金屬基座，其中該晶片接合至該金屬基座，該封裝層形成於該金屬基座上，該晶片的一側接合至該金屬基座且相對另一側提供有該金屬接合層。
  8. 一種內埋式封裝結構，包含： 一晶片，包含一金屬接合層；一燒結金屬層，接合至該金屬接合層；一銅箔層，接合至該燒結金屬層，其中該燒結金屬層介於該金屬接合層與該銅箔層之間；一封裝層，包覆該晶片；以及一導電柱，形成於該封裝層的一盲孔中，且該導電柱經由該銅箔層和該燒結金屬層與該金屬接合層電性連接。
  9. 如請求項8所述之內埋式封裝結構，其中該燒結金屬層的厚度為60.0微米(μm)以下。
  10. 如請求項8所述之內埋式封裝結構，其中該銅箔層的厚度為50.0微米至100.0微米。
  11. 如請求項8所述之內埋式封裝結構，其中該燒結金屬層包含燒結銅、燒結銀或燒結銀銅。
  12. 如請求項8所述之內埋式封裝結構，其中該銅箔層和該燒結金屬層具有與該金屬接合層實質上相同或較小的圖案面積。
  13. 如請求項8所述之內埋式封裝結構，其中該導電柱包含電鍍銅。
  14. 如請求項8所述之內埋式封裝結構，其中該封裝層的該盲孔經由雷射鑽孔形成。
  15. 如請求項8所述之內埋式封裝結構，更包含一金屬基座，其中該晶片接合至該金屬基座，該封裝層形成於該金 屬基座上，該晶片的一側接合至該金屬基座且相對另一側提供有該金屬接合層。
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