TW201347124A - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TW201347124A
TW201347124A TW101116157A TW101116157A TW201347124A TW 201347124 A TW201347124 A TW 201347124A TW 101116157 A TW101116157 A TW 101116157A TW 101116157 A TW101116157 A TW 101116157A TW 201347124 A TW201347124 A TW 201347124A
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Taiwan
Prior art keywords
insulating layer
semiconductor package
layer
conductive element
circuit
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TW101116157A
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English (en)
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唐紹祖
何祈慶
蔡瀛洲
藍章益
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW101116157A priority Critical patent/TW201347124A/zh
Priority to CN2012101670942A priority patent/CN103390598A/zh
Priority to US13/584,965 priority patent/US20130292832A1/en
Publication of TW201347124A publication Critical patent/TW201347124A/zh

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    • H—ELECTRICITY
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

一種半導體封裝件，包括：第一絕緣層、設於該第一絕緣層中之複數第一導電元件、設於該第一絕緣層上之第一線路層、置設於該第一絕緣層上之半導體晶片、以及形成於該第一絕緣層上之封裝膠體。本發明之第一導電元件係為銲線，因而其徑寬極小，使其於該第一絕緣層表面上之佔用面積極小，故可增加該第一線路層之佈線面積。本發明復提供該半導體封裝件之製法。

Description

半導體封裝件及其製法
本發明係關於一種半導體封裝件，更詳言之，本發明係為一種提高可靠度及佈線密度之半導體封裝件及其製法。
隨著電子產品輕薄短小及系統整合的趨勢，使得半導體封裝件之空間運用更加重要，且不斷的改良半導體封裝的製程技術，以符合現代科技產品輕薄短小的趨勢，例如：超薄無接腳封裝件(Small Leadless Package,SLP)，其製法可參閱第7435680號美國專利或如第1A至1F圖所示。
如第1A圖所示，提供一具有複數電性接觸墊100之承載板10。
如第1B圖所示，形成一為預浸材(Prepreg,PP)之介電層12於該承載板10上，且於該介電層12上藉由雷射方式形成有複數露出該電性接觸墊100之盲孔120。
如第1C圖所示，先進行銅電鍍製程以於該介電層12上全面形成銅層，且於各該盲孔120中形成導電盲孔11。再進行蝕刻製程，以形成一線路層13於該介電層12上，且各該導電盲孔11電性連接該電性接觸墊100與線路層13。
如第1D圖所示，形成一絕緣保護層14於該介電層12與該線路層13上，並於該絕緣保護層14上形成複數開孔140，以令該線路層13之部分表面對應外露於該些開孔140，俾供作為電性連接墊130。
如第1E圖所示，設置半導體晶片15於該絕緣保護層14上，且該半導體晶片15藉由銲線150電性連接該開孔140中之電性連接墊130。接著，形成封裝膠體16於該絕緣保護層14上，以包覆該電性連接墊130、該半導體晶片15與該些銲線150。
如第1F圖所示，移除該承載板10，以外露該些電性接觸墊100，俾供結合銲球(圖未示)，而可接置如電路板之電子裝置(圖未示)。
如第1F’圖所示，亦可形成線路增層結構17於該線路層13與該介電層12上，再形成該絕緣保護層14於該線路增層結構17上。其中，該線路增層結構17包含至少一介電層170、形成於該介電層170上之另一線路層171、及形成於該介電層170中之導電盲孔172，該導電盲孔172電性連接該線路層13,171，且該絕緣保護層14則形成於最外側之介電層170上，並露出該另一線路層171之部分表面供作打線墊。
惟，習知半導體封裝件1,1’之製法中，因於雷射鑽孔後會使該介電層12之盲孔120中產生膠渣，故須將該盲孔120中之膠渣清理去除，但因不易完全清除膠渣，而往往造成脫層(Delamination)，導致該線路層13,171發生接觸不良之問題。
再者，以雷射方式形成之盲孔120，其孔徑約60至80μm，使得該盲孔120於該介電層12表面上之佔用面積較大，因而減少該線路層13之佈線面積。
另外，以雷射形成盲孔120,172a之方式，當形成線路增層結構17時，上、下層之盲孔120,172a的位置必須錯開，因而使該線路層13,171之導電路徑加長，進而提高電性不良之風險。
然而，如何克服習知技術之種種問題，實為一重要課題。
為解決上述習知技術之種種問題，本發明遂揭露一種半導體封裝件，係包括：線路增層結構，係包含第一絕緣層、第一導電元件及第一線路層，該第一絕緣層具有相對之第一表面與第二表面，該第一導電元件係為銲線且設於該第一絕緣層中並外露於該第一表面，該第一線路層設於該第一絕緣層之第一表面上以電性連接該些第一導電元件；半導體晶片，係置設於該線路增層結構上方，並電性連接該第一線路層；以及封裝膠體，係形成於該線路增層結構上，且包覆該半導體晶片。
本發明復提供一種半導體封裝件之製法，係包括：形成線路增層結構，其步驟包含：形成複數第一導電元件於一承載板上，且該第一導電元件係為銲線；形成第一絕緣層於該承載板上，以包覆該些第一導電元件，該第一絕緣層具有相對之第一表面與第二表面，且該第二表面結合於該承載板上，並令該些第一導電元件外露於該第一絕緣層之第一表面；形成第一線路層於該第一絕緣層之第一表面上，且該第一線路層電性連接該第一導電元件；設置半導體晶片於該線路增層結構上方，該半導體晶片並電性連接該第一線路層；形成封裝膠體於該線路增層結構上，以包覆該半導體晶片；以及移除該承載板。
前述之半導體封裝件之製法中，該承載板可為金屬板或玻璃纖維板(FR4)。
前述之半導體封裝件之製法中，可利用研磨方式薄化該第一絕緣層之厚度，使該第一導電元件外露於該第一絕緣層之第一表面。
前述之半導體封裝件之製法可包括移除該承載板之後，進行切單製程。
前述之半導體封裝件及其製法，該承載板上可具有電性接觸墊，以令該些第一導電元件形成於該電性接觸墊上。當移除該承載板之後，該電性接觸墊之表面可齊平該第一絕緣層之第二表面，亦即該些電性接觸墊係外露於該第一絕緣層之第二表面，可供形成銲球於該些電性接觸墊上。
前述之半導體封裝件及其製法，該第一導電元件之表面可齊平該第一絕緣層之第一表面。
前述之半導體封裝件及其製法，該第一導電元件可為球型線頭或楔型線頭。
前述之半導體封裝件及其製法，形成該線路增層結構之步驟復包含：形成第二導電元件於該第一線路層上，再形成一第二絕緣層於該第一絕緣層之第一表面上，以包覆該第二導電元件與該第一線路層，復於該第二絕緣層上形成第二線路層，使該第二導電元件電性連接該第一與第二線路層。其中，該第二導電元件係為球型線頭或楔型線頭。
前述之半導體封裝件及其製法，該第一與第二絕緣層之材質係為封裝膠體、預浸材(Prepreg,PP)或Ajinomoto build up film(ABF)。
另外，前述之半導體封裝件及其製法，復包括設置該半導體晶片之前，形成絕緣保護層於該線路增層結構上，並於該絕緣保護層上形成開孔，以令該第一線路層之部分表面外露於該開孔。因此，該半導體晶片係可置設於該絕緣保護層上。
由上可知，本發明半導體封裝件及其製法，係藉由先形成第一導電元件，再形成第一絕緣層，因而無需形成雷射開孔，故相較於習知技術，本發明之製法無須清除膠渣，因而可避免發生脫層，以有效避免第一線路層發生接觸不良之問題。
再者，本發明係藉由銲線作為第一導電元件以取代習知導電盲孔，因該銲線之寬度約18μm，係遠小於習知導電盲孔之徑寬，故相較於習知技術，本發明之銲線於該第一絕緣層之第一表面上之佔用面積極小，因而大幅增加該第一線路層可利用之佈線面積。
另外，本發明以銲線取代習知導電盲孔，因而本發明之製法無需以雷射形成盲孔，故當形成線路增層結構時，上、下層之銲線的位置可重疊，亦即無須錯開，因而可減短該第一線路層之導電路徑，以降低電性不良之風險。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
以下係配合第2A至2I圖詳細說明本發明之半導體封裝件2之製法。
如第2A圖所示，提供一具有複數電性接觸墊200之承載板20。於本實施例中，該承載板20係為金屬板或玻璃纖維板(FR4)。
如第2B圖所示，形成複數第一導電元件21於該些電性接觸墊200上，且該第一導電元件21係為銲線。
於本實施例中，該第一導電元件21係為楔型線頭(Wedge Bond)，可選用銅材、金材、銀材或鋁材。於另一實施例中，如第2B’圖所示，該第一導電元件21’可為球型線頭(Ball Bond)，且該球型線頭分為球部21a與線段21b，令該球部21a結合該電性接觸墊200。
如第2C圖所示，接續第2B圖之製程，形成第一絕緣層22’於該承載板20上，以包覆該些電性接觸墊200與第一導電元件21。
於本實施例中，該第一絕緣層22’具有相對之第一表面22a’與第二表面22b，且該第二表面22b結合於該承載板20與電性接觸墊200上。
再者，該第一絕緣層22’之材質係為封裝膠體、預浸材(Prepreg,PP)或Ajinomoto build up film(ABF)。
如第2D圖所示，利用研磨(grinding)方式薄化該第一絕緣層22’之厚度，使該第一導電元件21之表面齊平該第一絕緣層22之第一表面22a，以令該第一導電元件21外露於該第一絕緣層22之第一表面22a。
如第2E圖所示，先進行銅電鍍製程以於該第一絕緣層22之第一表面22a上全面形成銅層，再進行蝕刻製程，以形成一第一線路層23於該第一絕緣層22之第一表面22a上，且該第一線路層23電性連接該些第一導電元件21，令該第一絕緣層22、第一導電元件21及第一線路層23作為線路增層結構27。
本發明之製法藉由先形成第一導電元件21，再形成第一絕緣層22’，並薄化該第一絕緣層22’，因而無需形成雷射開孔，故本發明之製法無須清除膠渣，因而可避免發生脫層，以有效避免第一線路層23發生接觸不良之問題。
再者，因該銲線之寬度約18μm，其遠小於習知導電盲孔之徑寬，故該第一導電元件21於該第一絕緣層22之第一表面22a上之佔用面積極小，因而大幅增加該第一線路層23可利用之佈線面積。
如第2F圖所示，形成一絕緣保護層24於該第一絕緣層22之第一表面22a與該第一線路層23上，並於該絕緣保護層24上形成複數開孔240，以令該第一線路層23之部分表面對應外露於該些開孔240，俾供作為電性連接墊230。
如第2G圖所示，設置半導體晶片25於該絕緣保護層24上，且該半導體晶片25藉由銲線250電性連接該開孔240中之電性連接墊230。
於本實施例中，該些電性連接墊230係為打線墊，而於其他實施例中，該些電性連接墊230可為覆晶銲墊，使該半導體晶片25藉由導電凸塊(圖未示)以覆晶方式電性連接該第一線路層23。再者，該銲線250係為金線或銅線。
接著，藉由模壓製程形成封裝膠體26於該絕緣保護層24上，以包覆該第一線路層23、該半導體晶片25與該些銲線250(或導電凸塊)。
如第2H或2H’圖所示，移除該承載板20，以外露該些電性接觸墊200。
如第2I圖所示，形成銲球28於該些電性接觸墊200(或球部21a)上，再依需求進行切單製程，以接置如電路板之電子裝置(圖未示)。
再者，如第2I’圖所示，形成該絕緣保護層24之前，亦可形成第二導電元件21a’於該第一線路層23上，再形成一第二絕緣層22”於該第一絕緣層22之第一表面22a上，以包覆該第二導電元件21a’與該第一線路層23，復於該第二絕緣層22”上形成第二線路層23a，使該第二導電元件21a’電性連接該第一與第二線路層23,23a，令該線路增層結構27”復包含該第二絕緣層22”及該第二導電元件21a’。
於本實施例中，該第二導電元件21a’係為銲線，且該絕緣保護層24形成於最外側之第二絕緣層22”上，並露出形成於該第二絕緣層22”上之該第二線路層23a之部分表面供作打線墊或覆晶銲墊。
再者，該第二絕緣層22”之材質係為封裝膠體、預浸材(Prepreg,PP)或Ajinomoto build up film(ABF)。
因此，藉由銲線(即第一導電元件21,21’及第二導電元件21a’)取代習知導電盲孔，當形成多層之線路增層結構27”時，上、下層之銲線(即第一導電元件21,21’及第二導電元件21a’)的位置可重疊，亦即無須錯開，因而可減短該第一與第二線路層23,23a之導電路徑，亦即直線向上傳遞，以降低電性不良之風險。
另外，如第2I”圖所示，形成該絕緣保護層24’時，可露出該第一絕緣層22之部分第一表面22a，以設置該半導體晶片25’於該第一絕緣層22之部分第一表面22a上。亦可依需求，將該半導體晶片25設於該第二絕緣層22”上，亦即只要設於該第一絕緣層22之第一表面22a上方即可。
本發明復提供一種半導體封裝件2,2’，其包括：線路增層結構27,27’、設於該線路增層結構27,27’上之絕緣保護層24、置設於該線路增層結構27,27’上方之半導體晶片25、以及形成於該絕緣保護層24上之封裝膠體26。
所述之線路增層結構27,27’係包含具有相對之第一表面22a與第二表面22b的第一絕緣層22、設於該第一絕緣層22中之第一導電元件21,21’、及設於該第一表面22a上之第一線路層23。
所述之第一絕緣層22之第二表面22b上具有結合該第一導電元件21,21’之電性接觸墊200，以結合銲球28，且該電性接觸墊200之表面係齊平該第二表面22b，又該第一絕緣層22之材質係為封裝膠體、預浸材(Prepreg,PP)或Ajinomoto build up film(ABF)。
所述之第一導電元件21,21’之表面係齊平該第一表面22a，以外露於該第一表面22a，且該第一導電元件21,21’係為銲線，例如球型線頭或楔型線頭。
所述之第一線路層23係電性連接該些第一導電元件21,21’。
所述之絕緣保護層24係設於該第一絕緣層22上，且形成有複數開孔240，以令該第一線路層23之部分表面外露於該開孔240。
所述之半導體晶片25係置設於該絕緣保護層24上，且藉由銲線250或導電凸塊(圖略)電性連接該開孔240中之第一線路層23。
所述之封裝膠體26係包覆該半導體晶片25與該銲線250(或導電凸塊)。
於其中一種半導體封裝件2”中，該線路增層結構27”復包含至少一形成於該第一絕緣層22上之第二絕緣層22”、形成於該第二絕緣層22”中之第二導電元件21a’、及形成於該第二絕緣層22”上之第二線路層23a，而該第二導電元件21a’亦電性連接該第一與第二線路層23,23a，使該最上側之第二線路層23a之部分表面外露於該開孔240，以藉由銲線250或導電凸塊電性連接該半導體晶片25。其中，該第二導電元件21a’可為銲線，且該第二絕緣層22”之材質係為封裝膠體、預浸材(Prepreg,PP)或Ajinomoto build up film(ABF)。
於另一種半導體封裝件3中，該絕緣保護層24’係露出該第一絕緣層22之部分第一表面22a，使該半導體晶片25’設置於該第一絕緣層22之部分第一表面22a上。
綜上所述，本發明之半導體封裝件及其製法，主要藉由先形成導電元件，再形成封裝膠體，以免用雷射開孔，故可避免發生脫層，以避免線路層發生接觸不良之問題。再者，以銲線取代習知導電盲孔，不僅可增加佈線面積，且於形成線路增層結構時可減短線路之導電路徑，因而有效降低電性不良之風險。因此，本發明之半導體封裝件及其製法可提升產品之可靠度。
上述該些實施樣態僅例示性說明本發明之功效，而非用於限制本發明，任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述該些實施態樣進行修飾與改變。此外，在上述該些實施態樣中之元件的數量僅為例示性說明，亦非用於限制本發明。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
1,1’,2,2’,2”,3．．．半導體封裝件
10,20．．．承載板
100,200．．．電性接觸墊
11,172．．．導電盲孔
12,170．．．介電層
120,172a．．．盲孔
13,171．．．線路層
130,230．．．電性連接墊
14,24,24’．．．絕緣保護層
140,240．．．開孔
15,25,25’．．．半導體晶片
150,250．．．銲線
16．．．封裝膠體
17,27,27’,27”．．．線路增層結構
21,21’．．．第一導電元件
21a．．．球部
21b．．．線段
21a’．．．第二導電元件
22,22’．．．第一絕緣層
22”．．．第二絕緣層
22a,22a’．．．第一表面
22b．．．第二表面
23．．．第一線路層
23a．．．第二線路層
26．．．封裝膠體
28．．．銲球
第1A至1F圖係顯示習知半導體封裝件之製法之剖面示意圖；其中，第1F’圖係為第1F圖之另一態樣；以及
第2A至2I圖係為本發明半導體封裝件之剖面示意圖；其中，第2B’圖係為第2B圖之另一實施例，第2H’圖係為第2H圖之另一實施例，第2I’及2I”圖係為第2I圖之其它不同實施例。
2．．．半導體封裝件
200．．．電性接觸墊
21．．．第一導電元件
22．．．第一絕緣層
22a．．．第一表面
22b．．．第二表面
23．．．第一線路層
230．．．電性連接墊
24．．．絕緣保護層
240．．．開孔
25．．．半導體晶片
250．．．銲線
26．．．封裝膠體
27．．．線路增層結構

Claims (27)

  1. 一種半導體封裝件，係包括：線路增層結構，係包含一第一絕緣層、第一導電元件及第一線路層，該第一絕緣層具有相對之第一表面與第二表面，該第一導電元件係為銲線且設於該第一絕緣層中並外露於該第一表面，該第一線路層設於該第一絕緣層之第一表面上以電性連接該些第一導電元件；半導體晶片，係置設於該線路增層結構上方，並電性連接該第一線路層；以及封裝膠體，係形成於該線路增層結構上，且包覆該半導體晶片。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一導電元件之表面係齊平該第一絕緣層之第一表面。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一導電元件係為球型線頭或楔型線頭。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一絕緣層之第二表面上具有電性接觸墊，並電性連接該第一導電元件。
  5. 如申請專利範圍第4項所述之半導體封裝件，其中，該電性接觸墊設有銲球。
  6. 如申請專利範圍第4項所述之半導體封裝件，其中，該電性接觸墊之表面係齊平該第一絕緣層之第二表面。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該線路增層結構復包含至少一形成於該第一絕緣層之第一表面上之第二絕緣層、形成於該第二絕緣層中之第二導電元件、及形成於該第二絕緣層上之第二線路層，該第二導電元件電性連接該第一及第二線路層。
  8. 如申請專利範圍第7項所述之半導體封裝件，其中，該第二導電元件係為球型線頭或楔型線頭。
  9. 如申請專利範圍第7項所述之半導體封裝件，其中，該第二絕緣層之材質係為封裝膠體、預浸材(Prepreg,PP)或Ajinomoto build up film(ABF)。
  10. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一絕緣層之材質係為封裝膠體、預浸材(Prepreg,PP)或Ajinomoto build up film(ABF)。
  11. 如申請專利範圍第1項所述之半導體封裝件，復包括絕緣保護層，係設於該線路增層結構上，並形成有複數開孔，以外露部分該第一線路層。
  12. 如申請專利範圍第11項所述之半導體封裝件，其中，該半導體晶片係置設於該絕緣保護層上。
  13. 一種半導體封裝件之製法，係包括：形成線路增層結構，其步驟包含：形成複數第一導電元件於一承載板上，且該第一導電元件係為銲線；形成一第一絕緣層於該承載板上，以包覆該些第一導電元件，該第一絕緣層具有相對之第一表面與第二表面，且該第二表面結合於該承載板上，並令該些第一導電元件外露於該第一絕緣層之第一表面；及形成第一線路層於該第一絕緣層之第一表面上，且該第一線路層電性連接該第一導電元件；設置半導體晶片於該線路增層結構上方，該半導體晶片並電性連接該第一線路層；形成封裝膠體於該線路增層結構上，以包覆該半導體晶片；以及移除該承載板。
  14. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該第一導電元件之表面係齊平該第一絕緣層之第一表面。
  15. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該第一導電元件係為球型線頭或楔型線頭。
  16. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，利用研磨方式薄化該第一絕緣層之厚度，使該第一導電元件外露於該第一絕緣層之第一表面。
  17. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，形成該線路增層結構之步驟復包含：形成第二導電元件於該第一線路層上，再形成一第二絕緣層於該第一絕緣層之第一表面上，以包覆該第二導電元件與該第一線路層，復於該第二絕緣層上形成第二線路層，使該第二導電元件電性連接該第一與第二線路層。
  18. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該第二導電元件係為球型線頭或楔型線頭。
  19. 如申請專利範圍第17項所述之半導體封裝件之製法，其中，該第二絕緣層之材質係為封裝膠體、預浸材(Prepreg,PP)或Ajinomoto build up film(ABF)。
  20. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該第一絕緣層之材質係為封裝膠體、預浸材(Prepreg,PP)或Ajinomoto build up film(ABF)。
  21. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該承載板係為金屬板或玻璃纖維板(FR4)。
  22. 如申請專利範圍第13項所述之半導體封裝件之製法，其中，該承載板上具有電性接觸墊，以令該些第一導電元件形成於該電性接觸墊上。
  23. 如申請專利範圍第22項所述之半導體封裝件之製法，其中，移除該承載板之後，該些電性接觸墊係外露於該第一絕緣層之第二表面。
  24. 如申請專利範圍第23項所述之半導體封裝件之製法，復包括移除該承載板之後，形成銲球於該些電性接觸墊上。
  25. 如申請專利範圍第13項所述之半導體封裝件之製法，復包括設置該半導體晶片之前，形成絕緣保護層於該線路增層結構上，並於該絕緣保護層上形成開孔，以令該第一線路層之部分表面外露於該開孔。
  26. 如申請專利範圍第25項所述之半導體封裝件之製法，其中，該半導體晶片係置設於該絕緣保護層上。
  27. 如申請專利範圍第13項所述之半導體封裝件之製法，復包括移除該承載板之後，進行切單製程。
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