TW201436132A - 封裝基板、封裝基板製作方法及封裝結構 - Google Patents
封裝基板、封裝基板製作方法及封裝結構 Download PDFInfo
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- TW201436132A TW201436132A TW102102540A TW102102540A TW201436132A TW 201436132 A TW201436132 A TW 201436132A TW 102102540 A TW102102540 A TW 102102540A TW 102102540 A TW102102540 A TW 102102540A TW 201436132 A TW201436132 A TW 201436132A
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- conductive
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- 239000000758 substrate Substances 0.000 title claims abstract description 136
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 139
- 238000007747 plating Methods 0.000 claims description 92
- 229910000679 solder Inorganic materials 0.000 claims description 75
- 230000004888 barrier function Effects 0.000 claims description 59
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 230000000903 blocking effect Effects 0.000 claims description 11
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 6
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 27
- 239000008393 encapsulating agent Substances 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000011112 process operation Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- CLDVQCMGOSGNIW-UHFFFAOYSA-N nickel tin Chemical compound [Ni].[Sn] CLDVQCMGOSGNIW-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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Abstract
一種封裝基板,其包括電路基板、多個第一導電柱及多個第二導電柱,所述電路基板具有第一基底及形成於第一基底一個表面的第一導電線路圖形,所述第一導電柱及第二導電柱均與第一導電線路圖形相互電連接,並自第一導電線路圖形向遠離第一導電線路圖形的方向延伸,所述第二導電柱的高度大於所述第一導電柱的高度。本發明還提供所述封裝基板的製作方法及包括所述封裝基板的封裝結構。
Description
本發明涉及一種半導體封裝技術,特別涉及一種封裝基板、封裝基板製作方法及封裝結構。
隨著半導體器件尺寸的不斷減小,具有半導體器件的層疊封裝結構也逐漸地備受關注。層疊封裝結構一般通過層疊製作方法製成,即在封裝基板上中心部位通過較小的焊球封裝一個晶片,然後再採用較大的焊球與連接基板相互結合,所述的連接基板上結合有另外的晶片,從而得到層疊封裝結構。由於僅採用焊球實現封裝基板與晶片及連接基板之間的電連接,容易由於焊球與封裝基板、連接基板及晶片的連接處產生裂縫,從而導致得到的層疊封裝結構的品質較差。
有鑒於此,有必要提供一種封裝基板及其製作方法、封裝結構,以克服上述不足。
一種封裝基板,其包括電路基板、多個第一導電柱及多個第二導電柱,所述電路基板具有第一基底及形成於第一基底一個表面的第一導電線路圖形,所述第一導電柱及第二導電柱均與第一導電線路圖形相互電連接,並自第一導電線路圖形向遠離第一導電線路圖形的方向延伸,所述第二導電柱的高度大於所述第一導電柱的高度。
一種封裝基板的製作方法,包括步驟:提供一電路基板,所述電路基板包括第一基底、形成於第一基底一側表面的第一導電線路圖形以及形成於第一導電線路圖形表面的第一防焊層,所述第一防焊層具有多個第一開口和第二開口,部分所述第一導電線路圖形從所述第一開口和第二開口露出;在第一防焊層的表面形成金屬種子層;在所述金屬種子層的表面形成第一電鍍層;在所述第一電鍍層的表面形成第二電鍍阻擋圖形,所述第二電鍍阻擋圖形內有與所述第一開口相對應的第一開孔;在從所述第一開孔露出的第一電鍍層的表面形成第一蝕刻阻擋圖形;去除所述第二電鍍阻擋圖形;在第一電鍍層及蝕刻阻擋圖形的表面形成第二電鍍層;在第二電鍍層的表面形成第二蝕刻阻擋圖形,所述第二蝕刻阻擋圖形與第二開口相對應;以及對第一電鍍層和第二電鍍層進行蝕刻,使得被第二蝕刻阻擋圖形覆蓋的部分第一電鍍層和第二電鍍層形成與第二開口相對應的第二導電柱,使得被第一阻擋圖形覆蓋的部分第一電鍍銅層形成與第一開口相對應的第一導電柱。
一種封裝結構,包括第一封裝體和封裝於第一封裝體的第二封裝體,所述第一封裝體包括第一晶片和所述的封裝基板,所述第一晶片具有與第一導電柱一一對應的多個第一電極墊,所述第一電極墊與第一導電柱通過第一焊球相互電導通,所述第二封裝體包括連接基板及封裝於連接基板的第二晶片,所述連接基板具有與第二導電柱相對應的電性接觸墊,所述第二導電柱與對應的電性接觸墊通過第二焊球相互電導通。
本技術方案提供的封裝基板及其製作方法,通過在形成第一電鍍層之後,設置與欲形成的第一導電柱相對應的第一蝕刻阻擋圖形,並在第一電鍍層及第一蝕刻阻擋圖形表面形成第二電鍍層,然後,採用一次性蝕刻即可得到高度不同的第一導電柱和第二導電柱。所述第一導電柱的高度可以通過控制第一電鍍層的厚度進行控制,第二導電柱的高度可以通過第一電鍍層和第二電鍍層的厚度之和進行控制,工藝操作簡單。
本技術方案中,由於封裝基板的第一導電柱的高度小於第二導電柱的高度,在進行封裝時,第一晶片通過第一導電柱封裝於封裝基板,而第二封裝體通過第二導電柱封裝於封裝基板。由於第一導電柱的高度與第二導電柱的高度不等,可以使得第一晶片厚度與第一導電柱的高度之和與第二導電柱的高度大致相等,從而可以減少封裝結構的厚度,進而減小封裝結構的體積。並且,由於封裝基板與連接基板之間通過第二導電柱與第二焊球相結合的方式進行結合,第一晶片與封裝基板之間通過第一導電柱與第一焊球相結合的方式進行結合,相比於現有技術中僅採用焊球進行封裝,能夠提升封裝結構的品質。
10...封裝結構
100a,100b...封裝基板
111...第一基底
1111...第一表面
1112...第二表面
112...第一導電線路圖形
113...第二導電線路圖形
114...第一防焊層
1141...第一開口
1142...第二開口
115...第二防焊層
1151...第三開口
120...金屬種子層
130...第一電鍍阻擋圖形
140...第一電鍍層
150...第二電鍍阻擋圖形
151...第一開孔
160...第一蝕刻阻擋圖形
170...第二電鍍層
180...第二蝕刻阻擋圖形
191...第一導電柱
192...第二導電柱
193...焊帽
171...光致抗蝕劑層
172...第二開孔
131...第三開孔
194...保護層
11...第一封裝體
12...第二封裝體
200...第一晶片
210...第一電極墊
101...第一焊球
102...第一封裝膠體
103...第二焊球
104...第二封裝膠體
105...第三封裝膠體
106...第三焊球
300...連接基板
310...第二基厎
320...第一電性接觸墊
330...第二電性接觸墊
340...第一導電孔
350...第三防焊層
360...第四防焊層
400...第二晶片
410...第二電極墊
420...鍵合導線
圖1至圖12為本技術方案第一實施例提供的封裝基板製作過程的剖面示意圖。
圖13至圖16為本技術方案第二實施例提供的封裝基板製作過程的剖面示意圖。
圖17為本技術方案提供的封裝結構的剖面示意圖。
下面將結合附圖及實施例,對本技術方案提供的封裝結構及其製作方法作進一步的詳細說明。
本技術方案第一實施例提供一種封裝基板的製作方法,所述封裝基板的製作方法包括步驟:
請參閱圖1,第一步,提供一電路基板110。
電路基板110為形成有導電線路並兩側均形成有防焊層的電路基板。電路基板110可以為多層電路板。電路基板110包括第一基底111、第一導電線路圖形112、第二導電線路圖形113、第一防焊層114及第二防焊層115。
本實施例中,第一基底111為多層基板,包括交替排列的多層樹脂層與多層導電線路圖形(圖未示)。第一基底111包括相對的第一表面1111及第二表面1112,該第一導電線路圖形112設置於該第一基底111的第一表面1111上,該第二導電線路圖形113設置於該第一基底111的第二表面1112上。該第一基底111的多層導電線路圖形之間及該第一基底111的多層導電線路圖形與該第一導電線路圖形112和第二導電線路圖形113分別通過導電孔(圖未示)電連接。
該第一防焊層114覆蓋部分該第一導電線路圖形112及從該第一導電線路圖形112露出的第一表面1111,所述第一防焊層114內形成有多個第一開口1141及多個第二開口1142,多個第一開口1141位於第一防焊層114的中心區域,並陣列排布。第二開口1142環繞多個第一開口1141設置。第一開口1141的橫截面積小於第二開口1142的橫截面積。部分該第一導電線路圖形112從該第一防焊層114的第一開口1141和第二開口1142露出。
該第二防焊層115覆蓋部分該第二導電線路圖形113及從該第二導電線路圖形113露出的第二表面1112,所述第二防焊層115內形成有多個第三開口1151,使部分該第二導電線路圖形113從該第二防焊層115露出。
第二步,請參閱圖2,在第一防焊層114的表面形成金屬種子層120。
本實施例中,可以通過濺鍍金屬銅的方式,在第一防焊層114的表面形成金屬種子層120。可以理解的是,在進行濺鍍的過程中,從第一防焊層114的空隙露出的第一導電線路圖形112的表面也可以形成金屬種子層120。
第三步,請參閱圖3,在第二防焊層115表面及從第二防焊層115露出的第二導電線路圖形113的表面形成第一電鍍阻擋圖形130。
本步驟中,可以採用印刷可剝膠等方式形成第一電鍍阻擋圖形130,使得第二防焊層115表面及從第二防焊層115露出的第二導電線路圖形113的表面完全被第一電鍍阻擋圖形130覆蓋。
第四步,請參閱圖4,在所述金屬種子層120的表面及第一導電線路圖形112表面形成第一電鍍層140。
第一電鍍層140覆蓋金屬種子層120及從所述第一開口1141和第二開口1142露出的第一導電線路圖形112的表面。
第五步,請參閱圖5,在所述第一電鍍層140的表面形成第二電鍍阻擋圖形150。
所述第二電鍍阻擋圖形150的中心區域具有多個第一開孔151,第一電鍍層140從第一開孔151的底部露出。所述多個第一開孔151可以陣列排布,所述多個第一開孔151開設的位置應與欲形成的封裝基板需要封裝的晶片的電極墊的分佈相互對應。每個第一開孔151均與一個第一開口1141相對應。所述第一開孔151可以在通過貼合乾膜形成整片的電鍍阻擋層後經過鐳射燒蝕形成。
第六步,請參閱圖6,在從所述第一開孔151露出的第一電鍍層140的表面形成第一蝕刻阻擋圖形160。
本實施例中,採用電鍍錫或鎳的方式在從所述第一開孔151露出的第一電鍍層140的表面形成第一蝕刻阻擋圖形160。所述第一蝕刻阻擋圖形160與第一開孔151相對應。因為,當對第一電鍍層140進行蝕刻時,蝕刻銅的蝕刻液並不能與錫或鎳發生反應,從而使得被錫或鎳的第一電鍍層140不被蝕刻。可以理解的是, 第一蝕刻阻擋圖形160也可以採用其他在蝕刻第一電鍍層140時不被蝕刻的金屬製成。
第七步,請參閱圖7,去除所述第二電鍍阻擋圖形150。
本步驟中,可以採用剝膜的方式,將所述第二電鍍阻擋圖形150去除。
第八步,請參閱圖8,在第一電鍍層140及第一蝕刻阻擋圖形160的表面形成第二電鍍層170。
本步驟還可以採用電鍍銅的方式形成第二電鍍層170。第二電鍍層170的厚度大於所述第一蝕刻阻擋圖形160的厚度,使得第一蝕刻阻擋圖形160完全被覆蓋。
第九步,請參閱圖9,在第二電鍍層170的表面形成第二蝕刻阻擋圖形180。
所述第二蝕刻阻擋圖形180與第二開口1142相對應。所述第二蝕刻阻擋圖形180可以採用貼合乾膜,然後曝光、顯影的方式形成。
第十步,請參閱圖10,對第一電鍍層140和第二電鍍層170進行蝕刻,使得被第二蝕刻阻擋圖形180覆蓋的部分第一電鍍層140和第二電鍍層170形成第二導電柱192,使得被第一蝕刻阻擋圖形160覆蓋的部分第一電鍍層140形成第一導電柱191。
在本步驟中,優選採用蝕刻因數大於4的蝕刻液進行蝕刻,以減少蝕刻過程中產生的側蝕。被第二蝕刻阻擋圖形180覆蓋的部分第一電鍍層140和第二電鍍層170沒有被蝕刻,形成通過第二開口1142與第一導電線路圖形112相互連接的第二導電柱192。所述第二導電柱192的高度等於第一電鍍層140和第二電鍍層170的厚度之和。位於第一蝕刻阻擋圖形160表面的第二電鍍層170被蝕刻,而被第一蝕刻阻擋圖形160覆蓋的部分第一電鍍層140未被蝕刻,從而形成通過第一開口1141與第一導電線路圖形112相互連接的第一導電柱191。
第十一步,請參閱圖11,去除第一電鍍阻擋圖形130、第一蝕刻阻擋圖形160和第二蝕刻阻擋圖形180,從而得到封裝基板100a。
由於第一電鍍阻擋圖形130和第二蝕刻阻擋圖形180可均採用乾膜形成,在去除時,可以採用剝膜的方式同時去除。
可以理解的是,請參閱圖12,本步驟中,第一蝕刻阻擋圖形160也可以不去除。由於第一蝕刻阻擋圖形160採用錫或者鎳製成,可以採用紅外回流焊(IR-Relow)處理,使得第一蝕刻阻擋圖形160熔融後形成覆蓋在第一導電柱191端部的焊帽193。
本技術方案第二實施例也提供一種封裝基板的製作方法,所述封裝基板的製作方法與第一實施例提供的封裝基板的製作方法相近,其中,第一步至第八步的操作與第一實施例相同,以下從第九步及之後的製作步驟進行說明。
第九步,請參閱圖13,在第二電鍍層170的表面形成光致抗蝕劑層171,所述光致抗蝕劑層171中形成有與第二開口1142相對應的第二開孔172,所述第二電鍍層170從第二開孔172底部露出。並在第一電鍍阻擋圖形130中形成多個第三開孔131,使得部分第二導電線路圖形113從第三開孔131露出。
第十步,請參閱圖14,在從第二開孔172露出的第二電鍍層170表面電鍍鎳金形成第二蝕刻阻擋圖形180。
本步驟中,同時在從第三開孔131露出的部分第二導電線路圖形113表面進行電鍍鎳金形成保護層194。
第十一步,請參閱圖15,去除光致抗蝕劑層171及第一電鍍阻擋圖形130,並對第一電鍍層140和第二電鍍層170進行蝕刻,從而得到第一導電柱191和第二導電柱192,得到封裝基板100b。
其中,第二導電柱192遠離第一導電線路圖形112的一端形成有電鍍鎳金形成的第二蝕刻阻擋圖形180。每個第一導電柱191的一端形成有電鍍鎳或錫形成的第一蝕刻阻擋圖形160。
可以理解的是,請參閱圖16,本實施例中也可以進一步包括採用紅外回流焊(IR-Relow)處理,使得第一蝕刻阻擋圖形160熔融後形成覆蓋在第一導電柱191端部的焊帽193。第二蝕刻阻擋圖形180可以作為第二導電柱192遠離第一導電線路圖形112的一端的保護層。
請參閱圖12,本技術方案第三實施例提供一種封裝基板100a,所述封裝基板100a包括電路基板110、多個第一導電柱191及多個第二導電柱192。
所述電路基板包括第一基底111、第一導電線路圖形112、第二導電線路圖形113、第一防焊層114及第二防焊層115。第一基底111為多層基板,包括交替排列的多層樹脂層與多層導電線路圖形(圖未示)。第一基底111包括相對的第一表面1111及第二表面1112,該第一導電線路圖形112設置於該第一基底111的第一表面1111上,該第二導電線路圖形113設置於該第一基底111的第二表面1112上。該第一基底111的多層導電線路圖形之間及該第一基底111的多層導電線路圖形與該第一導電線路圖形112和第二導電線路圖形113分別通過導電孔(圖未示)電連接。
該第一防焊層114覆蓋部分該第一導電線路圖形112及從該第一導電線路圖形112露出的第一表面1111,所述第一防焊層114內形成有多個第一開口1141及多個第二開口1142,多個第一開口1141位於第一防焊層114的中心區域,並陣列排布。第二開口1142環繞多個第一開口1141設置。第一開口1141的橫截面積小於第二開口1142的橫截面積。部分該第一導電線路圖形112從該第一防焊層114的第一開口1141和第二開口1142露出。
該第二防焊層115覆蓋部分該第二導電線路圖形113及從該第二導電線路圖形113露出的第二表面1112,所述第二防焊層115內形成有多個第三開口1151,使部分該第二導電線路圖形113從該第二防焊層115露出。
所述第一導電柱191通過第一開口1141與第一導電線路圖形112相互電連接。第二導電柱192通過第二開口1142與第二導電線路圖形113與第一導電線路圖形112相互電連接。第一導電柱191的高度小於第二導電柱192的高度。在所述第一導電柱191遠離第一導電線路圖形112的一端,還形成有鎳錫製成的焊帽193。
可以理解的是,本技術方案提供的封裝基板還可以包括形成在第二導電柱192遠離第一導電線路圖形112一端及從第二防焊層115露出第二導電線路圖形113的表面還可以包括由鎳金製成的保護層。
本技術方案提供的封裝基板及其製作方法,通過在形成第一電鍍層之後,設置與欲形成的第一導電柱相對應的第一蝕刻阻擋圖形,並在第一電鍍層及第一蝕刻阻擋圖形表面形成第二電鍍層,然後,採用一次性蝕刻即可得到高度不同的第一導電柱和第二導電柱。所述第一導電柱的高度可以通過控制第一電鍍層的厚度進行控制,第二導電柱的高度可以通過第一電鍍層和第二電鍍層的厚度之和進行控制,工藝操作簡單。
請參閱圖17,本技術方案第四實施例提供一種封裝結構10,所述封裝結構10包括第一封裝體11和封裝於第一封裝體11的第二封裝體12。
其中,第一封裝體11包括所述的封裝基板100a及第一晶片200。第一晶片200的橫截面積小於封裝基板100a的橫截面積。第一晶片200具有與多個第一導電柱191相對應的多個第一電極墊210。每個第一電極墊210與一個對應的第一導電柱191通過第一焊球101相互電連接。每個第一焊球101環繞對應的第一導電柱191並與第一電極墊210相互接觸。為了使得第一晶片200與封裝基板100a牢固結合,在第一晶片200與封裝基板100a之間,設置有第一封裝膠體102。
第二封裝體12包括連接基板300及至少一個第二晶片400。連接基板300封裝於封裝基板100a的第一導電線路圖形112的一側。連接基板300包括第二基底310、多個第一電性接觸墊320及多個第二電性接觸墊330。第一電性接觸墊320及第二電性接觸墊330形成於第二基底310的相對兩個表面。第二基底310內形成有多個第一導電孔340,每個第一電性接觸墊320通過對應的一個第一導電孔340與第二電性接觸墊330相互電連接。
所述連接基板300還包括第三防焊層350和第四防焊層360。所述第三防焊層350和第四防焊層360形成於第二基底310的相對兩個表面。第三防焊層350內形成有開口,每個第一電性接觸墊320從對應的開口露出。第四防焊層360內也形成有開口,每個第二電性接觸墊330從對應的開口露出。所述第一電性接觸墊320與第二導電柱192一一對應並電連接。本實施例中,每個第一電性接觸墊320與第二導電柱192通過第二焊球103相互電導通。每個第二焊球103環繞對應的第二導電柱192並與第一電性接觸墊320相互接觸。
本實施例中,有兩個第二晶片400封裝於連接基板300。兩個第二晶片400之間通過介電膠片600相互連接。每個第二晶片400具有第二電極墊410,每個第二電極墊410通過鍵合導線420與一個第二電性接觸墊330相互電連接。
為了使得與連接基板300相鄰的第二晶片400與連接基板300牢固結合,在第二晶片400與連接基板300之間,設置有第二封裝膠體104。
在連接基板300的一側及兩個第二晶片400的周圍,還通過模制的方式形成有第三封裝膠體105,以包覆第二晶片400、連接基板300的第二電性接觸墊330及鍵合導線420。
本實施例提供的封裝結構10還包括第三焊球106,第三焊球106形成於封裝基板100a從第三開口1151露出的第二導電線路圖形113的表面,用於將封裝結構10與其他元件進行連接。
可以理解的是,本實施例中的封裝基板也可以採用本技術方案第二實施例提供的封裝基板100b。
本技術方案中,由於封裝基板100a的第一導電柱191的高度小於第二導電柱192的高度,在進行封裝時,第一晶片200通過第一導電柱191封裝於封裝基板100a,而第二封裝體12通過第二導電柱192封裝於封裝基板100a。由於第一導電柱191的高度與第二導電柱192的高度不等,可以使得第一晶片200厚度與第一導電柱191的高度之和與第二導電柱192的高度大致相等,從而可以減少封裝結構的厚度,進而減小封裝結構的體積。並且,由於封裝基板100a與連接基板300之間通過第二導電柱192與第二焊球103相結合的方式進行結合,第一晶片200與封裝基板100a之間通過第一導電柱191與第一焊球相結合的方式進行結合,相比於現有技術中僅採用焊球進行封裝,能夠提升封裝結構的品質。
綜上所述,本發明確已符合發明專利之要件,遂依法提出專利申請。惟,以上所述者僅為本發明之較佳實施方式,自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化,皆應涵蓋於以下申請專利範圍內。
100a...封裝基板
110...電路基板
111...第一基底
112...第一導電線路圖形
191...第一導電柱
192...第二導電柱
Claims (15)
- 一種封裝基板,其包括電路基板、多個第一導電柱及多個第二導電柱,所述電路基板具有第一基底及形成於第一基底一個表面的第一導電線路圖形,所述第一導電柱及第二導電柱均與第一導電線路圖形相互電連接,並自第一導電線路圖形向遠離第一導電線路圖形的方向延伸,所述第二導電柱的高度大於所述第一導電柱的高度。
- 根據申請專利範圍第1項所述的封裝基板,其中,所述第一導電柱遠離第一導電線路圖形的一端形成有焊帽。
- 根據申請專利範圍第1項所述的封裝基板,其中,所述第二導電柱遠離第一導電線路圖形一端具有鎳金製成的保護層。
- 根據申請專利範圍第3項所述的封裝基板,其中所述電路基板還包括形成於第一基底另一表面的第二導電線路圖形及第二防焊層,所述第二防焊層內形成有多個第三開口,部分第二導電線路圖形第三開口露出,在從第三開口露出的第二導電線路圖形表面也形成鎳金製成的保護層。
- 根據申請專利範圍第1項所述的封裝基板,其中,所述電路基板還包括第一防焊層,所述第一防焊層形成於第一導電線路圖形的一側,所述第一防焊層內形成有多個第一開口和多個第二開口,所述第一導電柱穿過所述第一開口與第一導電線路圖形相互電連接,所述第二導電柱穿過第二開口與第一導電線路圖形相互電連接。
- 根據申請專利範圍第1項所述的封裝基板,其中,所述多個第二導電柱環繞所述多個第一導電柱設置。
- 一種封裝基板的製作方法,包括步驟:
提供一電路基板,所述電路基板包括第一基底、形成於第一基底一側表面的第一導電線路圖形以及形成於第一導電線路圖形表面的第一防焊層,所述第一防焊層具有多個第一開口和第二開口,部分所述第一導電線路圖形從所述第一開口和第二開口露出;
在第一防焊層的表面形成金屬種子層;
在所述金屬種子層的表面形成第一電鍍層;
在所述第一電鍍層的表面形成第二電鍍阻擋圖形,所述第二電鍍阻擋圖形內有與所述第一開口相對應的第一開孔;
在從所述第一開孔露出的第一電鍍層的表面形成第一蝕刻阻擋圖形;
去除所述第二電鍍阻擋圖形;
在第一電鍍層及蝕刻阻擋圖形的表面形成第二電鍍層;
在第二電鍍層的表面形成第二蝕刻阻擋圖形,所述第二蝕刻阻擋圖形與第二開口相對應;以及
對第一電鍍層和第二電鍍層進行蝕刻,使得被第二蝕刻阻擋圖形覆蓋的部分第一電鍍層和第二電鍍層形成與第二開口相對應的第二導電柱,使得被第一阻擋圖形覆蓋的部分第一電鍍銅層形成與第一開口相對應的第一導電柱。 - 根據申請專利範圍第7項所述的封裝基板的製作方法,其中,所述第二蝕刻阻擋圖形採用貼合乾膜,然後曝光及顯影的方式形成,在形成第一導電柱和第二導電柱之後,還包括去除第二蝕刻阻擋圖形的步驟。
- 根據申請專利範圍第7項所述的封裝基板的製作方法,其中,在在第一防焊層的表面形成金屬種子層之間,還包括在電路基板的另一側表面形成第一電鍍阻擋圖形的步驟,在形成第一導電柱和第二導電柱之後,還包括去除第一電鍍阻擋圖形的步驟。
- 根據申請專利範圍第7項所述的封裝基板的製作方法,其中,所述第一蝕刻阻擋圖形採用電鍍錫或者電鍍鎳的方式形成。
- 根據申請專利範圍第10項所述的封裝基板的製作方法,其中,在形成第一導電柱和第二導電柱之後,還包括對所述第一蝕刻阻擋圖形進行紅外回流焊處理,從而在每個第一導電柱表面形成焊帽的步驟。
- 根據申請專利範圍第7項所述的封裝基板的製作方法,其中,在形成第一導電柱和第二導電柱之後,還包括去除第一蝕刻阻擋圖形的步驟。
- 根據申請專利範圍第7項所述的封裝基板的製作方法,其中,在所述第一電鍍層及蝕刻阻擋圖形的表面形成第二電鍍層之後,在第二電鍍層的表面形成光致抗蝕劑層,所述光致抗蝕劑層中形成有與第二開口相對應的第二開孔;在從第二開孔露出的第二電鍍層表面電鍍鎳金形成第二蝕刻阻擋層;去除光致抗蝕劑層並對第一電鍍層和第二電鍍層進行蝕刻,從而得到所述第一導電柱和第二導電柱。
- 一種封裝結構,包括第一封裝體和封裝於第一封裝體的第二封裝體,所述第一封裝體包括第一晶片和申請專利範圍第1至6任一項所述的封裝基板,所述第一晶片具有與第一導電柱一一對應的多個第一電極墊,所述第一電極墊與第一導電柱通過第一焊球相互電導通,所述第二封裝體包括連接基板及封裝於連接基板的第二晶片,所述連接基板具有與第二導電柱相對應的電性接觸墊,所述第二導電柱與對應的電性接觸墊通過第二焊球相互電導通。
- 根據申請專利範圍第14項所述的封裝結構,其中,所述第一晶片的厚度與第一導電柱的高度之和與第二導電柱的高度相等。
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2012
- 2012-12-28 CN CN201210582244.6A patent/CN103904050B/zh active Active
-
2013
- 2013-01-23 TW TW102102540A patent/TW201436132A/zh unknown
- 2013-12-05 US US14/097,251 patent/US9173298B2/en active Active
-
2015
- 2015-09-09 US US14/848,504 patent/US20150380391A1/en not_active Abandoned
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TWI570861B (zh) * | 2014-12-03 | 2017-02-11 | 恆勁科技股份有限公司 | 封裝結構及其製法 |
TWI770854B (zh) * | 2020-03-27 | 2022-07-11 | 南亞科技股份有限公司 | 雙晶粒半導體封裝結構及其製備方法 |
US11469216B2 (en) | 2020-03-27 | 2022-10-11 | Nanya Technology Corporation | Dual-die semiconductor package and manufacturing method thereof |
Also Published As
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US9173298B2 (en) | 2015-10-27 |
CN103904050A (zh) | 2014-07-02 |
US20140185259A1 (en) | 2014-07-03 |
CN103904050B (zh) | 2017-04-19 |
US20150380391A1 (en) | 2015-12-31 |
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