TWI533424B - 封裝載板 - Google Patents

封裝載板 Download PDF

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Publication number
TWI533424B
TWI533424B TW101114932A TW101114932A TWI533424B TW I533424 B TWI533424 B TW I533424B TW 101114932 A TW101114932 A TW 101114932A TW 101114932 A TW101114932 A TW 101114932A TW I533424 B TWI533424 B TW I533424B
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Taiwan
Prior art keywords
layer
dielectric layer
disposed
package carrier
circuit
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TW101114932A
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English (en)
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TW201344865A (zh
Inventor
孫世豪
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旭德科技股份有限公司
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Application filed by 旭德科技股份有限公司 filed Critical 旭德科技股份有限公司
Priority to TW101114932A priority Critical patent/TWI533424B/zh
Priority to CN201210212661.1A priority patent/CN103378047B/zh
Priority to US13/584,784 priority patent/US8766463B2/en
Priority to JP2012278719A priority patent/JP5611315B2/ja
Publication of TW201344865A publication Critical patent/TW201344865A/zh
Application granted granted Critical
Publication of TWI533424B publication Critical patent/TWI533424B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

封裝載板
本發明是有關於一種封裝結構，且特別是有關於一種封裝載板。
晶片封裝的目的是提供晶片適當的訊號路徑、導熱路徑及結構保護。傳統的打線(wire bonding)技術通常採用導線架(leadframe)作為晶片的承載器(carrier)。隨著晶片的接點密度逐漸提高，導線架已無法再提供更高的接點密度，故可利用具有高接點密度的封裝載板(package carrier)來取代，並藉由金屬導線或凸塊(bump)等導電媒體，將晶片封裝至封裝載板上。
一般來說，封裝載板的製作通常是以核心(core)介電層作為蕊材，並利用全加成法(fully additive process)、半加成法(semi-additive process)、減成法(subtractive process)或其他方式，將線路層與介電層交錯堆疊於核心介電層上。然而，隨著元件尺寸縮小以及線路複雜度增加，核心介電層上通常必須堆疊有多層的線路層與介電層，且因此核心介電層需要具有一定的厚度。如此一來，封裝載板具有相當大的整體厚度，因而在封裝結構的厚度縮減上產生極大的障礙。
本發明提供一種封裝載板，其具有較薄的厚度。
本發明提出一種封裝載板，其包括金屬基板、銲墊、第一介電層以及第一線路層。金屬基板具有彼此相對的第一表面與第二表面。銲墊配置於第一表面上。第一介電層配置於第一表面上，且覆蓋銲墊。第一介電層的厚度小於150 μm。第一線路層內埋於第一介電層中，且與銲墊連接。
依照本發明實施例所述之封裝載板，上述之第一線路層的線寬例如小於15 μm。
依照本發明實施例所述之封裝載板，更包括保護層，其配置於第一介電層上，且暴露出第一線路層。
依照本發明實施例所述之封裝載板，更包括表面處理層，其配置於第一線路層上。
依照本發明實施例所述之封裝載板，更包括導電層，其包覆金屬基板。
依照本發明實施例所述之封裝載板，更包括第二介電層、第二線路層以及導通孔。第二介電層配置於第一介電層上，且覆蓋第一線路層。第二線路層內埋於第二介電層中。導通孔配置於第二介電層中，且連接第一線路層與第二線路層。
依照本發明實施例所述之封裝載板，上述之第二線路層的線寬例如小於15 μm。
依照本發明實施例所述之封裝載板，更包括保護層，其配置於第二介電層上，且暴露出第二線路層。
依照本發明實施例所述之封裝載板，更包括表面處理層，其配置於第二線路層上。
本發明另提出一種封裝載板，其包括金屬基板、銲墊、第一介電層、第一線路層以及第一導通孔。金屬基板具有彼此相對的第一表面與第二表面。銲墊配置於第一表面上。第一介電層配置於第一表面上，且覆蓋銲墊。第一介電層的厚度小於150 μm。第一線路層配置於第一介電層上。第一導通孔配置於第一介電層中，且連接第一線路層與銲墊。
依照本發明實施例所述之封裝載板，上述之第一線路層的線寬例如大於或等於15 μm。
依照本發明實施例所述之封裝載板，更包括保護層，其配置於第一介電層上，且暴露出第一線路層。
依照本發明實施例所述之封裝載板，更包括表面處理層，其配置於第一線路層上。
依照本發明實施例所述之封裝載板，更包括導電層，其包覆金屬基板。
依照本發明實施例所述之封裝載板，更包括第二介電層、第二線路層以及第二導通孔。第二介電層配置於第一介電層上，且覆蓋第一線路層。第二線路層配置於第二介電層上。第二導通孔配置於第二介電層中，且連接第一線路層與第二線路層。
依照本發明實施例所述之封裝載板，上述之第二線路層的線寬例如大於或等於15 μm。
依照本發明實施例所述之封裝載板，更包括保護層，其配置於第二介電層上，且暴露出第二線路層。
依照本發明實施例所述之封裝載板，更包括表面處理層，其配置於第二線路層上。
基於上述，在本發明的封裝載板中，介電層的厚度小於150 μm，因此封裝載板以及藉由此封裝載板所形成的晶片封裝結構可以具有較薄的厚度。此外，當內埋於介電層中的線路層為超細線路時，或者當配置於介電層上的線路層為細線路時，可以進一步提高封裝載板中的佈線密度以及減少線路的層數，因此亦可達到減少封裝載板以及藉由此封裝載板所形成的晶片封裝結構的厚度的目的。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1為依照本發明一實施例所繪示的封裝載板之剖面示意圖。請參照圖1，封裝載板10包括金屬基板100、導電層102、銲墊104、介電層106以及線路層108。在本實施例中，僅繪示出二個銲墊104，但本發明並不以此為限。金屬基板100具有彼此相對的表面100a與表面100b。金屬基板100的材料例如為鋁、銅或其合金，但本發明並不以此為限。導電層102包覆金屬基板100。銲墊104配置於表面100a上。導電層102例如是化學銅層，其作為以電鍍方式形成銲墊104時的種子層(seed layer)。當然，在另一實施例中，銲墊104亦可利用沈積的方式形成於表面100a上。在此情況下，則不需要導電層102。
介電層106配置於表面100a上，且覆蓋銲墊104。介電層106的厚度小於150 μm。介電層106的材料例如為含有玻璃顆粒的環氧樹脂(如ABF樹脂)。線路層108內埋於介電層106中，且與銲墊104連接。
此外，在本實施例中，封裝載板10還包括保護層110與表面處理層112。保護層110配置於介電層106上，且暴露出線路層108。保護層110可作為防焊層。表面處理層112配置於線路層108上。表面處理層112例如為鎳層、金層、銀層或鎳鈀金層，但本發明並不以此為限。表面處理層112可在後續利用打線接合的方式裝設晶片時使導線容易地與線路層108電性連接。當然，在其他實施例中，亦可視實際需求而選擇性地省略保護層110和/或表面處理層112。
在本實施例中，線路層108的線寬例如小於15 μm，也就是所謂的超細線路。如此一來，可以有效地提高介電層106中的佈線密度，且因此可以減少封裝載板以及藉由封裝載板所形成的晶片封裝結構中的線路層的層數。
此外，在晶片接合於封裝載板10以及形成封裝膠體之後，會將金屬基板100與導電層102移除，然後於銲墊104上形成銲球(solder ball)，以形成晶片封裝結構。以下將以圖2對此晶片封裝結構作說明。
如圖2所示，在晶片封裝結構20中，晶片114配置於部分線路層108上，且藉由導線116與表面處理層112連接，藉此電性連接至線路層108。此外，晶片114下方配置有黏著層118，以使晶片114固著於線路層108上。封裝膠體120覆蓋保護層110、表面處理層112、晶片114與導線116。銲球122配至於銲墊104上，用以使晶片封裝結構20連接至外部電子元件。
在晶片封裝結構20中，由於介電層介電層106的厚度小於150 μm，因此晶片封裝結構20可具有較薄的厚度。此外，由於線路層108可為超細線路，因此可以提高介電層106中的佈線密度，進而減少晶片封裝結構20中的線路層的層數，以減少晶片封裝結構20的整體厚度。
另外一提的是，在封裝載板10中，介電層106中內埋有銲墊104與線路層108，亦即封裝載板10為具有二層線路的結構，但本發明並不以此為限。在其他實施例中，封裝載板亦可為具有三層或更多層線路的結構。
圖3為依照本發明另一實施例所繪示的封裝載板之剖面示意圖。在圖3中，與圖1相同的元件將以相同的標號表示，於此不再另行說明。請參照圖3，封裝載板30與封裝載板10的差異在於：封裝載板30更包括介電層300、線路層302以及導通孔304。介電層300配置於介電層106上，且覆蓋線路層108。介電層300的材料例如為含有玻璃顆粒的環氧樹脂(如ABF樹脂)。線路層302內埋於介電層300中。導通孔304配置於介電層300中，且連接線路層108與線路層302。保護層110配置於介電層300上，且暴露出線路層302。表面處理層112配置於線路層302上。
在本實施例中，介電層106與介電層300的厚度皆小於150 μm，且線路層108與線路層302的線寬皆例如小於15 μm。如此一來，具有三層線路的封裝載板30亦可具有較低的厚度以及較高的佈線密度。
在上述實施例中，線路層皆是內埋於介電層中。然而，在其他實施例中，線路層也可以是配置於介電層上。
圖4為依照本發明又一實施例所繪示的封裝載板之剖面示意圖。請參照圖4，封裝載板40與封裝載板10的差異在於：在封裝載板40中，線路層408配置於介電層406上，且藉由導通孔410而與銲墊104連接。線路層408的線寬例如大於或等於15 μm，也就是所謂的細線路。如此一來，可以有效地提高介電層406上的佈線密度。介電層406的厚度小於150 μm。由於線路層408配置於介電層406上，而非內埋於介電層406中，因此介電層406可不限於ABF樹脂。當然，在其他實施例中，亦可視實際需求而選擇性地省略保護層110和/或表面處理層112。
同樣地，在晶片接合於封裝載板40以及形成封裝膠體之後，會將金屬基板100與導電層102移除，然後於銲墊104上形成銲球，以形成晶片封裝結構50，如圖5所示。在圖5中，與圖2相同的元件將以相同的標號表示，於此不再另行說明。請參照圖5，在晶片封裝結構50中，由於介電層406的厚度小於150 μm，因此晶片封裝結構50可具有較薄的厚度。此外，由於線路層408可為細線路，因此可以提高介電層406上的佈線密度，進而減少晶片封裝結構50中的線路層的層數，以減少晶片封裝結構50的整體厚度。
圖6為依照本發明又一實施例所繪示的封裝載板之剖面示意圖。在圖6中，與圖4相同的元件將以相同的標號表示，於此不再另行說明。請參照圖6，封裝載板60與封裝載板40的差異在於：封裝載板60更包括介電層600、線路層602以及導通孔604。介電層600配置於介電層406上，且覆蓋線路層408。介電層600的材料例如與介電層406相同。線路層602配置於於介電層600上。導通孔604配置於介電層600中，且連接線路層408與線路層602。保護層110配置於介電層600上，且暴露出線路層602。表面處理層112配置於線路層602上。
在本實施例中，介電層406與介電層600的厚度皆小於150 μm，且線路層408與線路層602的線寬皆大於或等於15 μm，也就是所謂的細線路。如此一來，具有三層線路的封裝載板60亦可具有較低的厚度以及較高的佈線密度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10、30、40、60．．．封裝載板
20、50．．．晶片封裝結構
100．．．金屬基板
100a、100b．．．表面
102．．．導電層
104．．．銲墊
106、300、406、600．．．介電層
108、302、408、602．．．線路層
110．．．保護層
112．．．表面處理層
114．．．晶片
116．．．導線
118．．．黏著層
120．．．封裝膠體
122．．．銲球
304、410、604．．．導通孔
圖1為依照本發明一實施例所繪示的封裝載板之剖面示意圖。
圖2為依照本發明一實施例所繪示的晶片封裝結構之剖面示意圖。
圖3為依照本發明另一實施例所繪示的封裝載板之剖面示意圖。
圖4為依照本發明又一實施例所繪示的封裝載板之剖面示意圖。
圖5為依照本發明又一實施例所繪示的晶片封裝結構之剖面示意圖。
圖6為依照本發明又一實施例所繪示的封裝載板之剖面示意圖。
10．．．封裝載板
100．．．金屬基板
100a、100b．．．表面
102．．．導電層
104．．．銲墊
106．．．介電層
108．．．線路層
110．．．保護層
112．．．表面處理層

Claims (12)

  1. 一種封裝載板，包括：一金屬基板，具有彼此相對的一第一表面與一第二表面；一銲墊，配置於該第一表面上；一第一介電層，配置於該第一表面上，且覆蓋該銲墊，該第一介電層的厚度小於150μm；一第一線路層，內埋於該第一介電層中，且與該銲墊連接，其中該第一線路層的線寬小於15μm；一第二介電層，配置於該第一介電層上，且覆蓋該第一線路層；一第二線路層，內埋於該第二介電層中，其中該第二線路層的線寬小於15μm；以及一導通孔，配置於該第二介電層中，且連接該第一線路層與該第二線路層。
  2. 如申請專利範圍第1項所述之封裝載板，更包括一保護層，配置於該第一介電層上，且暴露出該第一線路層。
  3. 如申請專利範圍第1項所述之封裝載板，更包括一表面處理層，配置於該第一線路層上。
  4. 如申請專利範圍第1項所述之封裝載板，更包括一導電層，包覆該金屬基板。
  5. 如申請專利範圍第1項所述之封裝載板，更包括一保護層，配置於該第二介電層上，且暴露出該第二線路層。
  6. 如申請專利範圍第1項所述之封裝載板，更包括一 表面處理層，配置於該第二線路層上。
  7. 一種封裝載板，包括：一金屬基板，具有彼此相對的一第一表面與一第二表面；一銲墊，配置於該第一表面上；一第一介電層，配置於該第一表面上，且覆蓋該銲墊，該第一介電層的厚度小於150μm；一第一線路層，配置於該第一介電層上，其中該第一線路層的線寬大於或等於15μm；一第一導通孔，配置於該第一介電層中，且連接該第一線路層與該銲墊；一第二介電層，配置於該第一介電層上，且覆蓋該第一線路層；一第二線路層，配置於該第二介電層上，其中該第二線路層的線寬大於或等於15μm；以及一第二導通孔，配置於該第二介電層中，且連接該第一線路層與該第二線路層。
  8. 如申請專利範圍第7項所述之封裝載板，更包括一保護層，配置於該第一介電層上，且暴露出該第一線路層。
  9. 如申請專利範圍第7項所述之封裝載板，更包括一表面處理層，配置於該第一線路層上。
  10. 如申請專利範圍第7項所述之封裝載板，更包括一導電層，包覆該金屬基板。
  11. 如申請專利範圍第7項所述之封裝載板，更包括一保護層，配置於該第二介電層上，且暴露出該第二線路層。
  12. 如申請專利範圍第7項所述之封裝載板，更包括一表面處理層，配置於該第二線路層上。
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