TWI614861B - 電子封裝結構及其製法 - Google Patents

電子封裝結構及其製法 Download PDF

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TWI614861B
TWI614861B TW104103172A TW104103172A TWI614861B TW I614861 B TWI614861 B TW I614861B TW 104103172 A TW104103172 A TW 104103172A TW 104103172 A TW104103172 A TW 104103172A TW I614861 B TWI614861 B TW I614861B
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layer
packaging structure
conductive
electronic packaging
item
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TW201628145A (zh
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白裕呈
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矽品精密工業股份有限公司
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Priority to TW104103172A priority Critical patent/TWI614861B/zh
Priority to CN201510095684.2A priority patent/CN105990268B/zh
Priority to US14/981,043 priority patent/US9607860B2/en
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Abstract

一種電子封裝結構之製法，係先形成線路層於導體件上；設置電子元件於該線路層上；形成絕緣層於該導體件上以包覆該電子元件與該線路層；以及移除部分該導體件，使該導體件成為複數導電凸塊，故當該電子封裝結構以表面黏著技術(SMT)設於電路板上時，該些導電凸塊容易對位於該電路板上之接點，因而能有效降低SMT製程之不良率。

Description

電子封裝結構及其製法
本發明係有關一種封裝技術，尤指一種電子封裝結構之製法。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係朝降低承載晶片之封裝基板的厚度發展。
第1A至1D圖係為習知無核心層(coreless)之半導體封裝件1之製法之剖視示意圖。
如第1A圖所示，形成一線路層11於一載板10上，其中，該線路層11包含一置晶墊111與複數電性連接墊112，該些該電性連接墊112圍繞該置晶墊111。
如第1B圖所示，將一半導體晶片12接置於該線路層11之置晶墊111上，並利用複數銲線120電性連接該半導體晶片12與該線路層11之電性連接墊112。之後，形成用以包覆該半導體晶片12與該些銲線120之絕緣層13。
如第1C圖所示，移除該載板10，以外露出該線路層 11與該絕緣層13底部。
如第1D圖所示，形成一表面處理層14於該線路層11之外露表面上，再形成一絕緣保護層15於該絕緣層11底部，且令該表面處理層14外露於該絕緣保護層15。之後，形成複數如銲球之導電元件16於該表面處理層14上，並進行切單作業。
惟，於習知半導體封裝件1之製法中，該線路層11之外露表面係齊平該該絕緣層13底部，故當該半導體封裝件1以表面黏著技術(Surface Mounting Technology，簡稱SMT)設於電路板上時，該些線路層11上之導電元件16不易對位於該電路板上之接點，導致SMT製程之不良率提高。
因此，如何克服上述習知技術之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝結構，係包括：絕緣層，係具有相對之第一表面與第二表面；線路層，係自該第二表面嵌埋於該絕緣層中；至少一電子元件，係埋設於該絕緣層中並設於該線路層上，且該電子元件係電性連接至該線路層；以及複數導電凸塊，係設於該線路層上並外露出該絕緣層之第二表面。
本發明復提供一種電子封裝結構之製法，係包括：形成線路層於一導體件上；設置至少一電子元件於該線路層上，且令該電子元件電性連接該線路層；形成絕緣層於該 導體件上，以令該絕緣層包覆該電子元件與該線路層，其中，該絕緣層具有相對之第一表面與第二表面，且該絕緣層以其第二表面結合至該導體件上；以及移除部分該導體件，使該導體件之保留部分成為複數導電凸塊，且外露出該絕緣層之第二表面。
前述之電子封裝結構及其製法中，該導電凸塊係自該絕緣層之第二表面凸出。
前述之電子封裝結構及其製法中，該導電凸塊之位置未對齊該電性連接墊之位置。
前述之電子封裝結構及其製法中，復包括於設置該電子元件前，形成表面處理層於該線路層上。
前述之電子封裝結構及其製法中，復包括於設置該電子元件前，形成表面處理層於該導體件上，以於移除部分該導體件後，該表面處理層係位於該導電凸塊上。
前述之電子封裝結構及其製法中，復包括於移除部分該導體件後，形成表面處理層於該導電凸塊上。
前述之電子封裝結構及其製法中，復包括於移除部分該導體件後，形成絕緣保護層於該絕緣層之第二表面上，且令該些導電凸塊外露於該絕緣保護層。
另外，前述之電子封裝結構及其製法中，復包括於形成該線路層前，將該導體件覆蓋於一止蝕層上，以於移除部分該導體件後，該止蝕層係位於該導電凸塊上。
由上可知，本發明之電子封裝結構及其製法中，主要藉由移除部分該導體件，使該導體件成為複數導電凸塊， 故相較於習知技術，當該電子封裝結構以表面黏著技術(SMT)設於電路板上時，該些導電凸塊上之導電元件容易對位於該電路板上之接點，因而能有效降低SMT製程之不良率。
1‧‧‧半導體封裝件
10‧‧‧載板
11,21‧‧‧線路層
111,210‧‧‧置晶墊
112,211,412‧‧‧電性連接墊
12‧‧‧半導體晶片
120,220‧‧‧銲線
13,23‧‧‧絕緣層
14,24‧‧‧表面處理層
15,25‧‧‧絕緣保護層
16‧‧‧導電元件
2,2’,3‧‧‧電子封裝結構
20‧‧‧導體件
20’,20”‧‧‧導電凸塊
20a,30a‧‧‧上側
20b,30b‧‧‧下側
200‧‧‧水平部
201‧‧‧直立部
22‧‧‧電子元件
23a‧‧‧第一表面
23b‧‧‧第二表面
30‧‧‧承載件
36‧‧‧止蝕層
410‧‧‧導電跡線
S‧‧‧切割路徑
第1A至1D圖係為習知無核心層之半導體封裝件之製法之剖視示意圖；第2A至2F圖係為本發明之電子封裝結構之第一實施例之製法之剖視示意圖；其中，第2E’至2F’圖係為第2E至2F圖之另一方式；第3A至3F圖係為本發明之電子封裝結構之第二實施例之製法之剖視示意圖；以及第4圖係為本發明之電子封裝結構之線路層之上視圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術 內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“底”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之電子封裝結構2之第一實施例之製法之剖視示意圖。
如第2A圖所示，提供一具有上側20a與下側20b之導體件20。於本實施例中，該導體件20係為銅箔，但不限於此。
如第2B圖所示，以電鍍或沉積銅材方式形成一線路層21於該導體件20之上側20a上。
於本實施例中，該線路層21具有至少一置晶墊210與複數電性連接墊211。
於其它實施例中，該線路層21之佈設可如第4圖所示。具體地，該線路層21包含複數圍繞該置晶墊210之導電跡線410、一置晶墊210與複數電性連接墊211,412，該導電跡線410可依需求蜿蜒而呈現出多變及複雜的圖形，且部分該電性連接墊211圍繞該置晶墊210，而部分該電性連接墊412位於該導電跡線410之外端。
如第2C圖所示，形成一表面處理層24於該線路層21之電性連接墊211與該導體件20之下側20b之部分表面上。
於本實施例中，該表面處理層24係為有機保銲膜 (Organic Solderability Preservatives，簡稱OSP)、鎳、鈀、金或銀層等。
再者，於形成該表面處理層24前，可先形成一阻障層(圖略)於該線路層21上，以避免該表面處理層24之金材與線路層21之銅材之間產生遷移(Migration)或擴散(Diffusion)效應。
如第2D圖所示，設置至少一電子元件22於該線路層21之置晶墊210上，且令該電子元件22電性連接該線路層21之電性連接墊211。接著，形成一絕緣層23於該導體件20之上側20a與該線路層21上，以令該絕緣層23包覆該電子元件22。
於本實施例中，該電子元件22係藉由打線(即複數如金線之銲線220)電性連接該些電性連接墊211，且該絕緣層23包覆該些銲線220。
再者，該電子元件22係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於此，該電子元件22係為主動元件。
又，該絕緣層23係為模壓(molding)製程製作之封裝膠體，且該絕緣層23具有相對之第一表面23a與第二表面23b，並以該第二表面23b結合至該導體件20之上側20a上。
另外，於其它實施例中，該電子元件22亦可藉由複數如銲球之導電凸塊(圖略)電性連接該些電性連接墊211， 故於形成該絕緣層23後，可透過研磨該絕緣層23，使該電子元件22之背面外露於該絕緣層23之第一表面23a，以供散熱之用。
如第2E圖所示，移除部分該導體件20，使該導體件20之保留部分成為複數導電凸塊20’，且令該絕緣層23之第二表面23b外露。
於本實施例中，該導電凸塊20’係自該絕緣層23之第二表面23b凸出。
再者，以蝕刻方式移除部分該導體件20，故該絕緣層23之第二表面23b會呈凹狀，且該表面處理層24可作為蝕刻用之阻層，即保留該表面處理層24所覆蓋之導體件20材質，以作為該些導電凸塊20’，使該表面處理層24位於該導電凸塊20’之端面上。
又，於另一實施例中，亦可於移除部分該導體件20後，再形成該表面處理層24於該導電凸塊20’上，故於移除部分該導體件20前，需先形成蝕刻用之阻層(圖略)。
另外，如第2E’圖所示，亦可以半蝕刻(half etch)方式移除該導體件20，使該導電凸塊20”位於該線路層21之外端，即該導電凸塊20”之位置未對齊該電性連接墊211之位置。
如第2F圖所示，接續第2E圖之製程，形成一絕緣保護層25於該絕緣層23之第二表面23b上，且令該些導電凸塊20’凸出並外露於該絕緣保護層25。之後，沿如第2E圖所示之切割路徑S進行切單作業。
於本實施例中，該絕緣保護層25係為防銲層，故於後續製程中，可形成複數如銲球之導電元件(圖略)於各該導電凸塊20’上。
再者，若接續第2E’圖之製程，將得到第2F’圖所示之電子封裝結構2’。
本發明之製法藉由該些導電凸塊20’,20”凸出該絕緣層23之第二表面23b，故當該電子封裝結構2,2’以表面黏著技術(SMT)設於電路板(圖略)上時，該些導電凸塊20’,20”上之導電元件(圖略)容易對位於該電路板上之接點，因而能有效降低SMT製程之不良率。
第3A至3F圖係為本發明之電子封裝結構3之第二實施例之製法之剖視示意圖。本實施例與第一實施例之差異僅在於新增止蝕層之製程，其它製程大致相同，故以下僅詳細說明差異處，而不再贅述相同處。
如第3A圖所示，提供一具有上側30a與下側30b之承載件30，且該承載件30之上側具有一止蝕層36。
如第3B圖所示，形成一導體件20於該承載件30上，以令該導體件20包覆該止蝕層36；再形成一線路層21於該導體件20上。
如第3C圖所示，形成一表面處理層24於該線路層21之電性連接墊211上。
如第3D圖所示，設置至少一電子元件22於該線路層21之置晶墊210上，且令該電子元件22電性連接該線路層21之電性連接墊211。接著，形成一絕緣層23於該導 體件20與該線路層21上，以令該絕緣層23包覆該電子元件22，且該絕緣層23具有相對之第一表面23a與第二表面23b，並以該第二表面23b結合至該導體件20上。
如第3E圖所示，移除該承載件30與部分該導體件20，使該導體件20之保留部分成為複數導電凸塊20’，且令該絕緣層23之第二表面23b外露。
於本實施例中，以蝕刻方式移除部分該導體件20，故該止蝕層36係作為蝕刻用之阻層，即保留該止蝕層36所覆蓋之導體件20，以作為該些導電凸塊20’，使該止蝕層36位於該導電凸塊20’之端面上。
如第3F圖所示，形成一絕緣保護層25於該絕緣層23之第二表面23b上，且令該些導電凸塊20’外露於該絕緣保護層25。之後，進行切單作業。
本發明提供一種電子封裝結構2,2’,3，係包括：一絕緣層23、一線路層21、一電子元件22以及複數導電凸塊20’,20”。
所述之絕緣層23係具有相對之第一表面23a與第二表面23b。
所述之線路層21係自該第二表面23b嵌埋於該絕緣層23中。
所述之電子元件22係埋設於該絕緣層23中並設於該線路層21上，且令該電子元件22電性連接該線路層21。
所述之導電凸塊20’,20”係設於該線路層21上並外露出該絕緣層23之第二表面23b。
於一實施例中，該導電凸塊20’,20”係自該絕緣層23之第二表面23b凸出。
於一實施例中，該電子封裝結構2,2’,3復包括形成於該線路層21上之一表面處理層24。
於一實施例中，該電子封裝結構2,2’復包括形成於該導電凸塊20’,20”上之一表面處理層24。
於一實施例中，該電子封裝結構2,2’,3復包括一絕緣保護層25，係形成於該絕緣層23之第二表面23b上，且令該些導電凸塊20’外露於該絕緣保護層25。
於一實施例中，該電子封裝結構3復包括形成於該導電凸塊20’上之一止蝕層36。
綜上所述，本發明之電子封裝結構及其製法，係藉由移除部分該導體件，使該導體件成為複數導電凸塊，故當該電子封裝結構以表面黏著技術(SMT)設於電路板上時，該些導電凸塊上之導電元件容易對位於該電路板上之接點，因而能有效降低SMT製程之不良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
20’‧‧‧導電凸塊
21‧‧‧線路層
22‧‧‧電子元件
220‧‧‧銲線
23‧‧‧絕緣層
23a‧‧‧第一表面
23b‧‧‧第二表面
24‧‧‧表面處理層
S‧‧‧切割路徑

Claims (17)

  1. 一種電子封裝結構，係包括：絕緣層，係具有相對之第一表面與第二表面；線路層，係自該第二表面嵌埋於該絕緣層中，包括複數電性連接墊；阻障層，係形成於該線路層上；表面處理層，係形成於該阻障層上；至少一電子元件，係埋設於該絕緣層中並設於該線路層上，該電子元件之一表面位置高於該些電性連接墊，且該電子元件係電性連接至該線路層；以及複數導電凸塊，係設於該線路層上，直接接觸該電性連接墊並外露出該絕緣層之第二表面。
  2. 如申請專利範圍第1項所述之電子封裝結構，其中，該導電凸塊係自該絕緣層之第二表面凸出。
  3. 如申請專利範圍第1項所述之電子封裝結構，其中，至少一該導電凸塊之位置未對齊該電性連接墊之位置。
  4. 如申請專利範圍第1項所述之電子封裝結構，復包括形成於該導電凸塊上之表面處理層。
  5. 如申請專利範圍第1項所述之電子封裝結構，復包括絕緣保護層，係形成於該絕緣層之第二表面上，且令該些導電凸塊外露於該絕緣保護層。
  6. 如申請專利範圍第1項所述之電子封裝結構，復包括形成於該導電凸塊上之一止蝕層。
  7. 如申請專利範圍第1項所述之電子封裝結構，其中，該線路層復包括一置晶墊與複數圍繞該置晶墊之導電跡線，該些導電跡線呈現蜿蜒之圖形。
  8. 一種電子封裝結構之製法，係包括：形成線路層於一導體件上，該線路層包括複數電性連接墊；形成阻障層於該線路層上；形成表面處理層於該阻障層上；設置至少一電子元件於該線路層上，該電子元件之一表面位置高於該些電性連接墊，且令該電子元件電性連接該線路層；形成絕緣層於該導體件上，以令該絕緣層包覆該電子元件與該線路層，其中，該絕緣層具有相對之第一表面與第二表面，且該絕緣層以其第二表面結合至該導體件上；以及移除部分該導體件，使該導體件之保留部分成為複數導電凸塊，該導電凸塊直接接觸該電性連接墊且外露出該絕緣層之第二表面。
  9. 如申請專利範圍第8項所述之電子封裝結構之製法，其中，該導電凸塊係自該絕緣層之第二表面凸出。
  10. 如申請專利範圍第8項所述之電子封裝結構之製法，其中，至少一該導電凸塊之位置未對齊該電性連接墊之位置。
  11. 如申請專利範圍第8項所述之電子封裝結構之製法， 復包括於設置該電子元件前，形成表面處理層於該導體件上。
  12. 如申請專利範圍第11項所述之電子封裝結構之製法，其中，於移除部分該導體件後，該表面處理層係位於該導電凸塊上。
  13. 如申請專利範圍第8項所述之電子封裝結構之製法，復包括於移除部分該導體件後，形成表面處理層於該導電凸塊上。
  14. 如申請專利範圍第8項所述之電子封裝結構之製法，復包括於移除部分該導體件後，形成絕緣保護層於該絕緣層之第二表面上，且令該些導電凸塊外露於該絕緣保護層。
  15. 如申請專利範圍第8項所述之電子封裝結構之製法，復包括於形成該線路層前，將該導體件覆蓋於一止蝕層上。
  16. 如申請專利範圍第15項所述之電子封裝結構之製法，其中，於移除部分該導體件後，該止蝕層係位於該導電凸塊上。
  17. 如申請專利範圍第8項所述之電子封裝結構之製法，其中，該線路層復包括一置晶墊與複數圍繞該置晶墊之導電跡線，該些導電跡線呈現蜿蜒之圖形。
TW104103172A 2015-01-30 2015-01-30 電子封裝結構及其製法 TWI614861B (zh)

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