TWI548050B - 封裝結構及其製法與封裝基板 - Google Patents

封裝結構及其製法與封裝基板 Download PDF

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TWI548050B
TWI548050B TW103138011A TW103138011A TWI548050B TW I548050 B TWI548050 B TW I548050B TW 103138011 A TW103138011 A TW 103138011A TW 103138011 A TW103138011 A TW 103138011A TW I548050 B TWI548050 B TW I548050B
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package
insulating protective
protective layer
package structure
opening
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TW103138011A
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TW201618254A (zh
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張佐嘉
謝承祐
江連成
黃富堂
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矽品精密工業股份有限公司
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Priority to TW103138011A priority Critical patent/TWI548050B/zh
Priority to CN201410657556.8A priority patent/CN105679735B/zh
Priority to US14/837,841 priority patent/US20160126176A1/en
Publication of TW201618254A publication Critical patent/TW201618254A/zh
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Description

封裝結構及其製法與封裝基板
本發明係有關一種封裝結構，尤指一種提高良率之封裝結構及其製法。
隨著電子產業的發達，現今的電子產品已趨向輕薄短小與功能多樣化的方向設計，半導體封裝技術亦隨之開發出不同的封裝型態。為滿足半導體裝置之高積集度(Integration)、微型化(Miniaturization)以及高電路效能等需求，遂而發展出封裝堆疊(Package On Package，簡稱POP)之技術。
第1A圖係為習知堆疊式封裝結構1之剖視示意圖。如第1A圖所示，該封裝結構1係包括相堆疊之上封裝件1a與下封裝件1b。該下封裝件1b係將晶片11以導線12電性連接該第一承載板10；該上封裝件1a係以複數銲球14疊設於該下封裝件1b上，且該些銲球14電性連接該上封裝件1a之第二承載板13與該第一承載板10，又該第二承載板13上側設置複數電子元件16。另外，形成封裝膠體15於該第一承載板10與該第二承載板13之間，使該封 裝膠體15包覆該晶片11、導線12及銲球14，以完成習知封裝結構1。
於習知上封裝件1a中，該第二承載板13之板體131具有上表面131a與下表面131b，且形成複數線路層132於該上表面131a與該下表面131b上，並分別形成上防銲層133a與下防銲層133b於該上表面131a與該下表面131b上，又該上防銲層133a與下防銲層133b分別具有外露部分該線路層132之複數上開孔1331與複數下開孔1332。另外，該些銲球14係設於該些下開孔1332中之線路層132上，而該些電子元件16係藉由銲錫凸塊17電性連接該些上開孔1331中之線路層132。
惟，於習知第二承載板13中，該上防銲層133a因需結合該些電子元件16而需配合該些電子元件16之接點，故該上防銲層133a需形成數量較多之上開孔1331(如第1B圖所示，各區域均佈設有上開孔1331)，而該下防銲層133b因只需結合該些銲球14，故該下防銲層133b僅需形成數量較少之下開孔1332(如第1C圖所示，中央區域A未形成任何開孔)。
因此，於該下防銲層133b僅於周圍形成該些下開孔1332而其中央區域A未形成任何開孔之情況下(如第1C圖所示)，致使該上防銲層133a所佔據該上表面131a之面積(開孔多)遠小於該下防銲層133b所佔據該下表面131b之面積(開孔少)，導致於進行熱處理製程期間(thermal cycle)，該上防銲層133a與下防銲層133b無法 均勻分散熱應力，造成該板體131之上表面131a與下表面131b之熱應力分布不均勻，而使該第二承載板13發生翹曲(warpage)，進而降低產品之良率。
因此，如何克服上述習知技術之問題，實已成為目前業界亟待克服之難題。
鑑於上述習知技術之種種缺失，本發明係提供一種封裝基板，係包括：板體，係具有相對之第一表面與第二表面，且該板體之第一表面與第二表面均定義有第一區域與第二區域，該第二區域係相鄰該第一區域；第一線路層，係形成於該板體之第一表面上；第二線路層，係形成於該板體之第二表面上；第一絕緣保護層，係形成於該第一線路層與該板體之第一表面上，且該第一絕緣保護層具有外露部分該第一線路層之複數第一開孔，該些第一開孔係位於該第一與第二區域；以及第二絕緣保護層，係形成於該第二線路層與該板體之第二表面上，且該第二絕緣保護層具有外露部分該第二線路層之複數第二開孔、及位於該第一區域之至少一開口，該些第二開孔係位於該第二區域。
本發明亦提供一種封裝結構，係包括：封裝件；複數導電元件，係設於該封裝件上並電性連接該封裝件；以及前述之封裝基板，係設於該些導電元件上，以令該封裝基板堆疊於該封裝件上，且該些導電元件係結合於該些第二開孔中之第二線路層上並電性連接該第二線路層。
本發明復提供一種封裝結構之製法，係包括：提供一 封裝件；以及堆疊前述之封裝基板於該封裝件上，且藉由複數導電元件結合該封裝件與該些第二開孔中之第二線路層上，並使該些導電元件電性連接該第二線路層。
前述之封裝結構及其製法，該第二區域係圍繞該第一區域。
前述之封裝結構及其製法，該第一絕緣保護層於該板體上之體積與該第二絕緣保護層於該板體上之體積係為大致相同。
前述之封裝結構及其製法中，該開口之形狀係為幾何圖形。
前述之封裝結構及其製法，該封裝件包含承載體與設於該承載體上之第一電子元件，且該第一電子元件電性連接該承載體。
前述之封裝結構及其製法中，部分該導電元件復設於該開口中。
前述之封裝結構及其製法中，復包括設置第二電子元件於該第一絕緣保護層上，且該第二電子元件電性連接該第一開孔中之第一線路層。
另外，前述之封裝結構及其製法中，復包括形成封裝材於該封裝件與該第二絕緣保護層之間。例如，該封裝材復形成於該開口中。
由上可知，本發明之封裝結構及其製法與封裝基板，主要藉由該第二絕緣保護層形成有對應該第一區域上之至少一開口，以減少該第二絕緣保護層佔據該第二表面之面 積，故相較於習知技術，本發明於後續熱處理製程期間，該第一絕緣保護層與第二絕緣保護層大致能均勻分散熱應力，以避免該封裝基板發生翹曲之情況，因而能提高產品之良率。
1,3‧‧‧封裝結構
1a‧‧‧上封裝件
1b‧‧‧下封裝件
10‧‧‧第一承載板
11‧‧‧晶片
12,33‧‧‧導線
13‧‧‧第二承載板
131,20‧‧‧板體
131a,31a‧‧‧上表面
131b,31b‧‧‧下表面
132,32‧‧‧線路層
133a‧‧‧上防銲層
133b‧‧‧下防銲層
1331‧‧‧上開孔
1332‧‧‧下開孔
14‧‧‧銲球
15‧‧‧封裝膠體
16‧‧‧電子元件
17,37‧‧‧銲錫凸塊
2‧‧‧封裝基板
20a‧‧‧第一表面
20b‧‧‧第二表面
21a‧‧‧第一線路層
21b‧‧‧第二線路層
22‧‧‧第一絕緣保護層
221‧‧‧第一開孔
23‧‧‧第二絕緣保護層
232‧‧‧第二開孔
233,233’,233”‧‧‧開口
3a‧‧‧封裝件
30‧‧‧第一電子元件
31‧‧‧承載體
33’‧‧‧導電凸塊
34,34’,34”‧‧‧導電元件
35‧‧‧封裝材
36‧‧‧第二電子元件
A‧‧‧中央區域
B‧‧‧第一區域
C‧‧‧第二區域
第1A圖係為習知封裝結構之剖視示意圖；第1B圖係為第1A圖之第二承載板之俯視圖；第1C圖係為第1A圖之第二承載板之仰視圖；第2及2’圖係為本發明封裝基板之剖視示意圖；第2A圖係為第2圖之俯視圖；第2B圖係為第2圖之仰視圖；其中，第2B’及2B”圖係為第2B圖之其它實施例；以及第3A至3C圖係為本發明封裝結構之製法之剖視示意圖；其中，第3B’及3C’圖係為第3B及3C圖之另一實施例。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功 效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2圖係為本發明之封裝基板2之剖視示意圖。如第2圖所示，所述之封裝基板2係包括：一板體20、一第一線路層21a、一第二線路層21b、一第一絕緣保護層22、以及一第二絕緣保護層23。
所述之板體20係具有相對之第一表面20a與第二表面20b，且該板體20之第一表面20a與第二表面20b係定義有第一區域B(可視為中央區域)與第二區域C(可視為邊緣區域)，該第二區域C係圍繞該第一區域B並相鄰接該第一區域B。具體地，該第一區域B及第二區域C於該第一表面20a上與該第一區域B及第二區域C於該第二表面20b上係為相對應之位置。
所述之第一線路層21a係形成於該板體20之第一表面20a上。
所述之第二線路層21b係形成於該板體20之第二表面20b上。
所述之第一絕緣保護層22係為防銲層，其形成於該第一線路層21a與該板體20之第一表面20a上，且該第一絕緣保護層22具有外露部分該第一線路層21a之複數第一開 孔221，該些第一開孔221係位於該第一區域B與第二區域C，如第2A圖所示。
所述之第二絕緣保護層23係為防銲層，其形成於該第二線路層21b與該板體20之第二表面20b上，且該第二絕緣保護層23具有外露部分該第二線路層21b之複數第二開孔232、及位於該第一區域B之複數開口233，該些第二開孔232係位於該第二區域C，如第2B圖所示。
於本實施例中，該第一表面20a之面積與該第二表面20b之面積係相同，且該第一絕緣保護層22之厚度與該第二絕緣保護層23之厚度相同，故藉由該開口233之佈設，使該第一絕緣保護層22所佔據該第一表面20a之面積與該第二絕緣保護層23所佔據該第二表面20b之面積相同，亦即該第一絕緣保護層22於該板體20上之體積與該第二絕緣保護層23於該板體20上之體積係為相同。
再者，該開口233,233’,233”之形狀係為幾何圖形，如第2B圖所示之圓形開口233、如第2B’圖所示之矩形開口233’、如第2B”圖所示之多邊形開口233”、或其它任意圖形等，並無特別限制。
又，該開口233係外露該板體20之部分第二表面20b；該開口233亦可外露部分該第二線路層21b，如第2’圖所示，因此，該開口233可依需求作功能性之設計，並無特別限制。
本發明之封裝基板2藉由該第二絕緣保護層23形成有對應該第一區域B上之至少一開口233,233’,233”，使該第 一絕緣保護層22於該板體20上之體積與該第二絕緣保護層23於該板體20上之體積係為相同，以於後續熱處理製程期間(thermal cycle)，該第一絕緣保護層22與第二絕緣保護層23能均勻分散熱應力，以避免該封裝基板2發生翹曲(warpage)。
第3A至3B圖係為本發明封裝結構3之製法之剖面示意圖。
如第3A圖所示，提供一封裝件3a，其包含一承載體31與設於該承載體31上之一第一電子元件30，且該第一電子元件30電性連接該承載體31。
於本實施例中，該承載體31係為習知封裝基板或如本發明之封裝基板2，其具有上表面31a與下表面31b，且於該上表面31a與下表面31b上形成有線路層32，使該第一電子元件30藉由複數導線33電性連接該上表面31a之線路層32。
再者，該第一電子元件30係為主動元件、被動元件或其組合者，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容或電感。
如第3B圖所示，形成複數導電元件34於該承載體31之上表面31a上，且該些導電元件34係電性連接該承載體31上之線路層32。
於本實施例中，該導電元件34係為銲球或如銅柱之導電柱。
如第3C圖所示，設置該封裝基板2於該些導電元件 34上，使該封裝基板2堆疊於該封裝件3a上，且該些導電元件34係結合於該些第二開孔232中之第二線路層21b上並電性連接該第二線路層21b。
接著，形成封裝材35於該封裝件3a與該第二絕緣保護層23之間，以令該封裝材35包覆該第一電子元件30、導線33與導電元件34。
於本實施例中，該封裝材35復形成於該開口233中。
再者，可設置至少一第二電子元件36於該第一絕緣保護層22上，且該第二電子元件36藉由複數銲錫凸塊37或複數導線(圖略)電性連接該第一開孔221中之第一線路層21a。具體地，該第二電子元件36係為封裝件、主動元件、被動元件或其組合者，該封裝件係為習知半導體封裝件，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容或電感
又，如第3C’圖所示該第一電子元件30亦可藉由複數導電凸塊33’電性連接該線路層32。
另外，該導電元件34’,34”復設於該開口233中，如第3C’圖所示，且該導電元件34’,34”可選擇性地電性連接該第二線路層21b(如第3C’圖所示之導電元件34’)或絕緣連接該第二線路層21b(如第3C’圖所示之導電元件34”)。
於其它實施例中，如第3B’圖所示，亦可形成複數導電元件34於該些第二開孔232中之第二線路層21b上，再將該封裝基板2藉由該些導電元件34堆疊於該封裝件3a上。
本發明之製法中，藉由該第一絕緣保護層22所佔據該第一表面20a之面積與該第二絕緣保護層23所佔據該第二表面20b之面積相同，以於熱處理製程期間，該第一絕緣保護層22與第二絕緣保護層23能均勻分散熱應力，因而該板體20之第一表面20a與第二表面20b之熱應力分布均勻，故能避免該封裝基板2發生翹曲，以提高產品之良率。
本發明復提供一種封裝結構3，係包括：一封裝件3a、設於該封裝件3a上之複數導電元件34、以及設於該些導電元件34上之封裝基板2。
所述之封裝件3a係包含一承載體31與設於該承載體31上之第一電子元件30，且該第一電子元件30電性連接該承載體31。
所述之導電元件34係設於該承載體31上並電性連接該承載體31。
所述之封裝基板2係堆疊於該封裝件3a上，且該些導電元件34係結合於該些第二開孔232中之第二線路層21b上並電性連接該第二線路層21b。
於一實施例中，該導電元件34復設於該開口233中。
於一實施例中，所述之封裝結構3復包括至少一第二電子元件36，係設於該第一絕緣保護層22上並電性連接該第一開孔221中之第一線路層21a。
於一實施例中，所述之封裝結構3復包括封裝材35，係形成於該封裝件3a與該第二絕緣保護層23之間，且該封裝材35復形成於該開口233中。
綜上所述，本發明之封裝結構及其製法與封裝基板，藉由形成該開口，以減少該第二絕緣保護層佔據該第二表面之面積，使該封裝基板於進行熱處理製程期間能避免發生翹曲之情況，故能提高該封裝結構之製造良率，以提升該封裝結構之可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝基板
20‧‧‧板體
20a‧‧‧第一表面
20b‧‧‧第二表面
21a‧‧‧第一線路層
21b‧‧‧第二線路層
22‧‧‧第一絕緣保護層
221‧‧‧第一開孔
23‧‧‧第二絕緣保護層
232‧‧‧第二開孔
233‧‧‧開口
B‧‧‧第一區域
C‧‧‧第二區域

Claims (22)

  1. 一種封裝基板，係包括：板體，係具有相對之第一表面與第二表面，且該板體之第一表面與第二表面均定義有第一區域與第二區域，該第二區域係相鄰該第一區域；第一線路層，係形成於該板體之第一表面上；第二線路層，係形成於該板體之第二表面上；第一絕緣保護層，係形成於該第一線路層與該板體之第一表面上，且該第一絕緣保護層具有外露部分該第一線路層之複數第一開孔，該些第一開孔係位於該第一與第二區域；以及第二絕緣保護層，係形成於該第二線路層與該板體之第二表面上，且該第二絕緣保護層具有外露部分該第二線路層之複數第二開孔及位於該第一區域之至少一開口，該些第二開孔並係位於該第二區域；其中，該第一絕緣保護層於該板體上之體積與該第二絕緣保護層於該板體上之體積係為大致相同。
  2. 如申請專利範圍第1項所述之封裝基板，其中，該第二區域係圍繞該第一區域。
  3. 如申請專利範圍第1項所述之封裝基板，其中，至少一該開口未與導電元件連接。
  4. 如申請專利範圍第1項所述之封裝基板，其中，該開口之形狀係為幾何圖形。
  5. 一種封裝結構，係包括： 封裝件；複數導電元件，係設於該封裝件上並電性連接該封裝件；以及如申請專利範圍第1項所述之封裝基板，係設於該些導電元件上，以令該封裝基板堆疊於該封裝件上，且該些導電元件係結合於該些第二開孔中之第二線路層上並電性連接該第二線路層；其中，該第一絕緣保護層於該板體上之體積與該第二絕緣保護層於該板體上之體積係為大致相同。
  6. 如申請專利範圍第5項所述之封裝結構，其中，該第二區域係圍繞該第一區域。
  7. 如申請專利範圍第5項所述之封裝結構，其中，至少一該開口未與該導電元件連接。
  8. 如申請專利範圍第5項所述之封裝結構，其中，該開口之形狀係為幾何圖形。
  9. 如申請專利範圍第5項所述之封裝結構，其中，該封裝件係包含承載體與設於該承載體上之第一電子元件，且該第一電子元件電性連接該承載體。
  10. 如申請專利範圍第5項所述之封裝結構，其中，部分該導電元件復設於該開口中。
  11. 如申請專利範圍第5項所述之封裝結構，復包括第二電子元件，係設於該第一絕緣保護層上並電性連接該第一開孔中之第一線路層。
  12. 如申請專利範圍第5項所述之封裝結構，復包括封裝 材，係形成於該封裝件與該第二絕緣保護層之間。
  13. 如申請專利範圍第12項所述之封裝結構，其中，該封裝材復形成於該開口中。
  14. 一種封裝結構之製法，係包括：提供一封裝件；以及堆疊如申請專利範圍第1項所述之封裝基板於該封裝件上，且藉由複數導電元件結合該封裝件與該些第二開孔中之第二線路層上，並使該些導電元件電性連接該第二線路層；其中，該第一絕緣保護層於該板體上之體積與該第二絕緣保護層於該板體上之體積係為大致相同。
  15. 如申請專利範圍第14項所述之封裝結構之製法，其中，該第二區域係圍繞該第一區域。
  16. 如申請專利範圍第14項所述之封裝結構之製法，其中，至少一該開口未與該導電元件連接。
  17. 如申請專利範圍第14項所述之封裝結構之製法，其中，該開口之形狀係為幾何圖形。
  18. 如申請專利範圍第14項所述之封裝結構之製法，其中，該封裝件包含承載體與設於該承載體上之第一電子元件，且該第一電子元件電性連接該承載體。
  19. 如申請專利範圍第14項所述之封裝結構之製法，其中，部分該導電元件復設於該開口中。
  20. 如申請專利範圍第14項所述之封裝結構之製法，復包括設置第二電子元件於該第一絕緣保護層上，且該第 二電子元件電性連接該第一開孔中之第一線路層。
  21. 如申請專利範圍第14項所述之封裝結構之製法，復包括形成封裝材於該封裝件與該第二絕緣保護層之間。
  22. 如申請專利範圍第21項所述之封裝結構之製法，其中，該封裝材復形成於該開口中。
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