CN105679735A - 封装结构及其制法与封装基板 - Google Patents

封装结构及其制法与封装基板 Download PDF

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CN105679735A
CN105679735A CN201410657556.8A CN201410657556A CN105679735A CN 105679735 A CN105679735 A CN 105679735A CN 201410657556 A CN201410657556 A CN 201410657556A CN 105679735 A CN105679735 A CN 105679735A
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insulating protective
packaging
protective layer
area
line layer
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CN105679735B (zh
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张佐嘉
谢承祐
江连成
黄富堂
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Siliconware Precision Industries Co Ltd
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Abstract

一种封装结构及其制法与封装基板，该封装基板，包括：具有相对的第一表面与第二表面的板体，其第一与第二表面均定义有相邻的第一区域与第二区域；第一与第二线路层分别形成于该第一与第二表面上；第一绝缘保护层形成于该第一表面上且具有位于该第一与第二区域的第一开孔；以及第二绝缘保护层形成于该第二表面上且具有位于该第二区域的第二开孔及位于该第一区域的开口，藉由形成该开口以减少该第二绝缘保护层的体积，所以于进行热处理制程时，该第一与第二绝缘保护层能均匀分散热应力。

Description

封装结构及其制法与封装基板
技术领域
本发明涉及一种封装结构，尤指一种提高良率的封装结构及其制法。
背景技术
随着电子产业的发达，现今的电子产品已趋向轻薄短小与功能多样化的方向设计，半导体封装技术也随之开发出不同的封装型态。为满足半导体装置的高积集度(Integration)、微型化(Miniaturization)以及高电路效能等需求，遂而发展出封装堆栈(PackageOnPackage，简称POP)的技术。
图1A为现有堆栈式封装结构1的剖视示意图。如图1A所示，该封装结构1包括相堆栈的上封装件1a与下封装件1b。该下封装件1b将芯片11以导线12电性连接该第一承载板10；该上封装件1a以多个焊球14迭设于该下封装件1b上，且该些焊球14电性连接该上封装件1a的第二承载板13与该第一承载板10，又该第二承载板13上侧设置多个电子组件16。另外，形成封装胶体15于该第一承载板10与该第二承载板13之间，使该封装胶体15包覆该芯片11、导线12及焊球14，以完成现有封装结构1。
于现有上封装件1a中，该第二承载板13的板体131具有上表面131a与下表面131b，且形成多个线路层132于该上表面131a与该下表面131b上，并分别形成上防焊层133a与下防焊层133b于该上表面131a与该下表面131b上，又该上防焊层133a与下防焊层133b分别具有外露部分该线路层132的多个上开孔1331与多个下开孔1332。另外，该些焊球14设于该些下开孔1332中的线路层132上，而该些电子组件16藉由焊锡凸块17电性连接该些上开孔1331中的线路层132。
然而，于现有第二承载板13中，该上防焊层133a因需结合该些电子组件16而需配合该些电子组件16的接点，所以该上防焊层133a需形成数量较多的上开孔1331(如图1B所示，各区域均布设有上开孔1331)，而该下防焊层133b因只需结合该些焊球14，所以该下防焊层133b仅需形成数量较少的下开孔1332(如图1C所示，中央区域A未形成任何开孔)。
因此，于该下防焊层133b仅于周围形成该些下开孔1332而其中央区域A未形成任何开孔的情况下(如图1C所示)，致使该上防焊层133a所占据该上表面131a的面积(开孔多)远小于该下防焊层133b所占据该下表面131b的面积(开孔少)，导致于进行热处理制程期间(thermalcycle)，该上防焊层133a与下防焊层133b无法均匀分散热应力，造成该板体131的上表面131a与下表面131b的热应力分布不均匀，而使该第二承载板13发生翘曲(warpage)，进而降低产品的良率。
因此，如何克服上述现有技术的问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种封装结构及其制法与封装基板，于进行热处理制程时，第一与第二绝缘保护层能均匀分散热应力。
本发明的封装基板，包括：板体，其具有相对的第一表面与第二表面，且该板体的第一表面与第二表面均定义有第一区域与第二区域，该第二区域相邻该第一区域；第一线路层，其形成于该板体的第一表面上；第二线路层，其形成于该板体的第二表面上；第一绝缘保护层，其形成于该第一线路层与该板体的第一表面上，且该第一绝缘保护层具有外露部分该第一线路层的多个第一开孔，该些第一开孔位于该第一与第二区域；以及第二绝缘保护层，其形成于该第二线路层与该板体的第二表面上，且该第二绝缘保护层具有外露部分该第二线路层的多个第二开孔、及位于该第一区域的至少一开口，该些第二开孔位于该第二区域。
本发明还提供一种封装结构，包括：封装件；多个导电组件，其设于该封装件上并电性连接该封装件；以及前述的封装基板，其设于该些导电组件上，以令该封装基板堆栈于该封装件上，且该些导电组件结合于该些第二开孔中的第二线路层上并电性连接该第二线路层。
本发明还提供一种封装结构的制法，包括：提供一封装件；以及堆栈前述的封装基板于该封装件上，且藉由多个导电组件结合该封装件与该些第二开孔中的第二线路层上，并使该些导电组件电性连接该第二线路层。
前述的封装结构及其制法，该第二区域围绕该第一区域。
前述的封装结构及其制法，该第一绝缘保护层于该板体上的体积与该第二绝缘保护层于该板体上的体积为大致相同。
前述的封装结构及其制法中，该开口的形状为几何图形。
前述的封装结构及其制法，该封装件包含承载体与设于该承载体上的第一电子组件，且该第一电子组件电性连接该承载体。
前述的封装结构及其制法中，部分该导电组件还设于该开口中。
前述的封装结构及其制法中，还包括设置第二电子组件于该第一绝缘保护层上，且该第二电子组件电性连接该第一开孔中的第一线路层。
另外，前述的封装结构及其制法中，还包括形成封装材于该封装件与该第二绝缘保护层之间。例如，该封装材还形成于该开口中。
由上可知，本发明的封装结构及其制法与封装基板，主要藉由该第二绝缘保护层形成有对应该第一区域上的至少一开口，以减少该第二绝缘保护层占据该第二表面的面积，所以相较于现有技术，本发明于后续热处理制程期间，该第一绝缘保护层与第二绝缘保护层大致能均匀分散热应力，以避免该封装基板发生翘曲的情况，因而能提高产品的良率。
附图说明
图1A为现有封装结构的剖视示意图；
图1B为图1A的第二承载板的俯视图；
图1C为图1A的第二承载板的仰视图；
图2及图2’为本发明封装基板的剖视示意图；
图2A为图2的俯视图；
图2B为图2的仰视图；其中，图2B’及图2B”为图2B的其它实施例；以及
图3A至图3C为本发明封装结构的制法的剖视示意图；其中，图3B’及图3C’为图3B及图3C的另一实施例。
主要组件符号说明
1,3封装结构
1a上封装件
1b下封装件
10第一承载板
11芯片
12,33导线
13第二承载板
131,20板体
131a,31a上表面
131b,31b下表面
132,32线路层
133a上防焊层
133b下防焊层
1331上开孔
1332下开孔
14焊球
15封装胶体
16电子组件
17,37焊锡凸块
2封装基板
20a第一表面
20b第二表面
21a第一线路层
21b第二线路层
22第一绝缘保护层
221第一开孔
23第二绝缘保护层
232第二开孔
233,233’,233”开口
3a封装件
30第一电子组件
31承载体
33’导电凸块
34,34’,34”导电组件
35封装材
36第二电子组件
A中央区域
B第一区域
C第二区域。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”、及“一”等的用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2为本发明的封装基板2的剖视示意图。如图2所示，所述的封装基板2包括：一板体20、一第一线路层21a、一第二线路层21b、一第一绝缘保护层22、以及一第二绝缘保护层23。
所述的板体20具有相对的第一表面20a与第二表面20b，且该板体20的第一表面20a与第二表面20b定义有第一区域B(可视为中央区域)与第二区域C(可视为边缘区域)，该第二区域C围绕该第一区域B并相邻接该第一区域B。具体地，该第一区域B及第二区域C于该第一表面20a上与该第一区域B及第二区域C于该第二表面20b上为相对应的位置。
所述的第一线路层21a形成于该板体20的第一表面20a上。
所述的第二线路层21b形成于该板体20的第二表面20b上。
所述的第一绝缘保护层22为防焊层，其形成于该第一线路层21a与该板体20的第一表面20a上，且该第一绝缘保护层22具有外露部分该第一线路层21a的多个第一开孔221，该些第一开孔221位于该第一区域B与第二区域C，如图2A所示。
所述的第二绝缘保护层23为防焊层，其形成于该第二线路层21b与该板体20的第二表面20b上，且该第二绝缘保护层23具有外露部分该第二线路层21b的多个第二开孔232、及位于该第一区域B的多个开口233，该些第二开孔232位于该第二区域C，如图2B所示。
于本实施例中，该第一表面20a的面积与该第二表面20b的面积为相同，且该第一绝缘保护层22的厚度与该第二绝缘保护层23的厚度相同，所以藉由该开口233的布设，使该第一绝缘保护层22所占据该第一表面20a的面积与该第二绝缘保护层23所占据该第二表面20b的面积相同，也就是该第一绝缘保护层22于该板体20上的体积与该第二绝缘保护层23于该板体20上的体积为相同。
此外，该开口233,233’,233”的形状为几何图形，如图2B所示的圆形开口233、如图2B’所示的矩形开口233’、如图2B”所示的多边形开口233”、或其它任意图形等，并无特别限制。
又，该开口233外露该板体20的部分第二表面20b；该开口233也可外露部分该第二线路层21b，如图2’所示，因此，该开口233可依需求作功能性的设计，并无特别限制。
本发明的封装基板2藉由该第二绝缘保护层23形成有对应该第一区域B上的至少一开口233,233’,233”，使该第一绝缘保护层22于该板体20上的体积与该第二绝缘保护层23于该板体20上的体积为相同，以于后续热处理制程期间(thermalcycle)，该第一绝缘保护层22与第二绝缘保护层23能均匀分散热应力，以避免该封装基板2发生翘曲(warpage)。
图3A至图3B为本发明封装结构3的制法的剖面示意图。
如图3A所示，提供一封装件3a，其包含一承载体31与设于该承载体31上的一第一电子组件30，且该第一电子组件30电性连接该承载体31。
于本实施例中，该承载体31为现有封装基板或如本发明的封装基板2，其具有上表面31a与下表面31b，且于该上表面31a与下表面31b上形成有线路层32，使该第一电子组件30藉由多个导线33电性连接该上表面31a的线路层32。
此外，该第一电子组件30为主动组件、被动组件或其组合者，且该主动组件例如为半导体芯片，而该被动组件例如为电阻、电容或电感。
如图3B所示，形成多个导电组件34于该承载体31的上表面31a上，且该些导电组件34电性连接该承载体31上的线路层32。
于本实施例中，该导电组件34为焊球或如铜柱的导电柱。
如图3C所示，设置该封装基板2于该些导电组件34上，使该封装基板2堆栈于该封装件3a上，且该些导电组件34结合于该些第二开孔232中的第二线路层21b上并电性连接该第二线路层21b。
接着，形成封装材35于该封装件3a与该第二绝缘保护层23之间，以令该封装材35包覆该第一电子组件30、导线33与导电组件34。
于本实施例中，该封装材35还形成于该开口233中。
此外，可设置至少一第二电子组件36于该第一绝缘保护层22上，且该第二电子组件36藉由多个焊锡凸块37或多个导线(图略)电性连接该第一开孔221中的第一线路层21a。具体地，该第二电子组件36为封装件、主动组件、被动组件或其组合者，该封装件为现有半导体封装件，且该主动组件例如为半导体芯片，而该被动组件例如为电阻、电容或电感
又，如图3C’所示该第一电子组件30也可藉由多个导电凸块33’电性连接该线路层32。
另外，该导电组件34’,34”还设于该开口233中，如图3C’所示，且该导电组件34’,34”可选择性地电性连接该第二线路层21b(如图3C’所示的导电组件34’)或绝缘连接该第二线路层21b(如图3C’所示的导电组件34”)。
于其它实施例中，如图3B’所示，也可形成多个导电组件34于该些第二开孔232中的第二线路层21b上，再将该封装基板2藉由该些导电组件34堆栈于该封装件3a上。
本发明的制法中，藉由该第一绝缘保护层22所占据该第一表面20a的面积与该第二绝缘保护层23所占据该第二表面20b的面积相同，以于热处理制程期间，该第一绝缘保护层22与第二绝缘保护层23能均匀分散热应力，因而该板体20的第一表面20a与第二表面20b的热应力分布均匀，所以能避免该封装基板2发生翘曲，以提高产品的良率。
本发明还提供一种封装结构3，包括：一封装件3a、设于该封装件3a上的多个导电组件34、以及设于该些导电组件34上的封装基板2。
所述的封装件3a包含一承载体31与设于该承载体31上的第一电子组件30，且该第一电子组件30电性连接该承载体31。
所述的导电组件34设于该承载体31上并电性连接该承载体31。
所述的封装基板2堆栈于该封装件3a上，且该些导电组件34结合于该些第二开孔232中的第二线路层21b上并电性连接该第二线路层21b。
于一实施例中，该导电组件34还设于该开口233中。
于一实施例中，所述的封装结构3还包括至少一第二电子组件36，其设于该第一绝缘保护层22上并电性连接该第一开孔221中的第一线路层21a。
于一实施例中，所述的封装结构3还包括封装材35，其形成于该封装件3a与该第二绝缘保护层23之间，且该封装材35还形成于该开口233中。
综上所述，本发明的封装结构及其制法与封装基板，藉由形成该开口，以减少该第二绝缘保护层占据该第二表面的面积，使该封装基板于进行热处理制程期间能避免发生翘曲的情况，所以能提高该封装结构的制造良率，以提升该封装结构的可靠度。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (22)

1.一种封装基板，包括：
板体，其具有相对的第一表面与第二表面，且该板体的第一表面与第二表面均定义有第一区域与第二区域，该第二区域相邻该第一区域；
第一线路层，其形成于该板体的第一表面上；
第二线路层，其形成于该板体的第二表面上；
第一绝缘保护层，其形成于该第一线路层与该板体的第一表面上，且该第一绝缘保护层具有外露部分该第一线路层的多个第一开孔，该些第一开孔位于该第一与第二区域；以及
第二绝缘保护层，其形成于该第二线路层与该板体的第二表面上，且该第二绝缘保护层具有外露部分该第二线路层的多个第二开孔及位于该第一区域的至少一开口，该些第二开孔并位于该第二区域。
2.如权利要求1所述的封装基板，其特征为，该第二区域围绕该第一区域。
3.如权利要求1所述的封装基板，其特征为，该第一绝缘保护层于该板体上的体积与该第二绝缘保护层于该板体上的体积为大致相同。
4.如权利要求1所述的封装基板，其特征为，该开口的形状为几何图形。
5.一种封装结构，包括：
封装件；
多个导电组件，其设于该封装件上并电性连接该封装件；以及
如权利要求1所述的封装基板，其设于该些导电组件上，以令该封装基板堆栈于该封装件上，且该些导电组件结合于该些第二开孔中的第二线路层上并电性连接该第二线路层。
6.如权利要求5所述的封装结构，其特征为，该第二区域围绕该第一区域。
7.如权利要求5所述的封装结构，其特征为，该第一绝缘保护层于该板体上的体积与该第二绝缘保护层于该板体上的体积为大致相同。
8.如权利要求5所述的封装结构，其特征为，该开口的形状为几何图形。
9.如权利要求5所述的封装结构，其特征为，该封装件包含承载体与设于该承载体上的第一电子组件，且该第一电子组件电性连接该承载体。
10.如权利要求5所述的封装结构，其特征为，部分该导电组件还设于该开口中。
11.如权利要求5所述的封装结构，其特征为，还包括第二电子组件，设于该第一绝缘保护层上并电性连接该第一开孔中的第一线路层。
12.如权利要求5所述的封装结构，其特征为，还包括封装材，其形成于该封装件与该第二绝缘保护层之间。
13.如权利要求12所述的封装结构，其特征为，该封装材还形成于该开口中。
14.一种封装结构的制法，包括：
提供一封装件；以及
堆栈如权利要求1所述的封装基板于该封装件上，且藉由多个导电组件结合该封装件与该些第二开孔中的第二线路层上，并使该些导电组件电性连接该第二线路层。
15.如权利要求14所述的封装结构的制法，其特征为，该第二区域围绕该第一区域。
16.如权利要求14所述的封装结构的制法，其特征为，该第一绝缘保护层于该板体上的体积与该第二绝缘保护层于该板体上的体积为大致相同。
17.如权利要求14所述的封装结构的制法，其特征为，该开口的形状为几何图形。
18.如权利要求14所述的封装结构的制法，其特征为，该封装件包含承载体与设于该承载体上的第一电子组件，且该第一电子组件电性连接该承载体。
19.如权利要求14所述的封装结构的制法，其特征为，部分该导电组件还设于该开口中。
20.如权利要求14所述的封装结构的制法，其特征为，还包括设置第二电子组件于该第一绝缘保护层上，且该第二电子组件电性连接该第一开孔中的第一线路层。
21.如权利要求14所述的封装结构的制法，其特征为，还包括形成封装材于该封装件与该第二绝缘保护层之间。
22.如权利要求21所述的封装结构的制法，其特征为，该封装材还形成于该开口中。
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