CN107785344A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN107785344A
CN107785344A CN201610836468.3A CN201610836468A CN107785344A CN 107785344 A CN107785344 A CN 107785344A CN 201610836468 A CN201610836468 A CN 201610836468A CN 107785344 A CN107785344 A CN 107785344A
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CN
China
Prior art keywords
substrate
packing piece
conducting element
electronic packing
preparation
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Pending
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CN201610836468.3A
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English (en)
Inventor
林长甫
姚进财
余国华
黄富堂
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN107785344A publication Critical patent/CN107785344A/zh
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Abstract

一种电子封装件及其制法，包括：第一基板、设于该第一基板上的第一电子元件、通过第一与第二导电元件堆叠于该第一基板上并通过结合层结合至该第一电子元件上的第二基板、以及形成于该第一基板与第二基板之间的第一封装层，通过不同构造的第一导电元件与第二导电元件支撑该第二基板，以于模压过程中，避免该第一封装层的模流产生向上推挤力，而造成该第二基板发生破裂。

Description

电子封装件及其制法
技术领域
本发明关于一种封装结构，特别是关于一种电子封装件及其制法。
背景技术
随着近年来可携式电子产品的蓬勃发展，各类相关产品也逐渐朝向高密度、高性能以及轻、薄、短、小的趋势发展，为因应此趋势，半导体封装业界遂开发各式样的堆叠封装(package on package，PoP)技术，以期能符合轻薄短小与高密度的要求。
如图1所示，其为现有堆叠式电子封装件1的剖视示意图。该电子封装件1包括两相迭的第一封装结构1a与第二封装结构1b、及黏固该第一封装结构1a与第二封装结构1b的封装胶体13。该第一封装结构1a包含第一基板10、以多个导电凸块110覆晶结合该第一基板10的第一电子元件11(如半导体晶片)、及包覆该些导电凸块110的底胶111。该第二封装结构1b包含第二基板12、以多个导电凸块140覆晶结合该第二基板12的第二电子元件14(如半导体晶片)、及包覆该些导电凸块140的底胶141。该第二基板12通过焊锡球120支撑且电性连接于该第一基板10上，且该封装胶体13形成于该第一基板10与第二基板12之间以包覆该些焊锡球120。
然而，现有电子封装件1中，当该第一基板10与第二基板12堆叠时，经过回焊该些焊锡球120之后，温度升降所产生的应力会导致该第二基板12局部凹凸不平，使得后续的模压过程中，该第二基板12的表面无法有效接触模具表面，导致形成该封装胶体13的封装材流入该第一基板10与第二基板12之间时，模流会产生向上推挤力，造成该些焊锡球120与该第二基板12之间发生破裂(crack)，使得电性接触不良。
此外，该焊锡球120于回焊后的体积及高度的公差大，不仅接点容易产生缺陷，导致电性连接品质不良，而且该焊锡球120所排列成的栅状阵列(grid array)容易产生共面性(coplanarity)不良，导致接点应力(stress)不平衡而容易造成该第一与第二封装结构1a,1b之间呈倾斜接置，甚至产生接点偏移的问题。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种电子封装件及其制法，可避免第一封装层的模流产生向上推挤力，而造成第二基板发生破裂。
本发明的电子封装件，包括：第一基板；第一电子元件，其设于该第一基板上；第二基板，其通过多个第一导电元件与第二导电元件堆叠于该第一基板上并通过结合层结合至该第一电子元件上，其中，该第一导电元件的构造与该第二导电元件的构造不同；以及第一封装层，其设于该第一基板与第二基板之间，且令该第一封装层包覆该第一电子元件、该第一导电元件与该第二导电元件。
本发明还提供一种电子封装件的制法，包括：提供第一基板及第二基板，其中，该第一基板上设有第一电子元件；将该第二基板通过第一导电元件与第二导电元件堆叠于该第一基板上，并使该第二基板通过结合层结合至该第一电子元件上，且该第一导电元件的构造与该第二导电元件的构造不同；以及形成第一封装层于该第一基板与第二基板之间，以令该第一封装层包覆该第一电子元件、该第一导电元件与该第二导电元件。
前述的电子封装件及其制法中，该第一导电元件与该第二导电元件的数量比例为1：0.5～1：1.5。
前述的电子封装件及其制法中，该第一导电元件为金属块，或者，该第一导电元件具有金属块与包覆该金属块的导电材。
前述的电子封装件及其制法中，该第二导电元件为焊锡凸块。
前述的电子封装件及其制法中，该结合层为薄膜(film)或散热材。
前述的电子封装件及其制法中，该第一基板的表面定义有一置晶区、及环绕该置晶区的第一堆叠区与第二堆叠区，该置晶区设有该第一电子元件，且该第一堆叠区与该第二堆叠区设有多个电性接点，以结合该第一导电元件及/或该第二导电元件，其中，该第一堆叠区的电性接点的密度大于该第二堆叠区的电性接点的密度。
前述的电子封装件及其制法中，该第一基板具有定位垫。
前述的电子封装件及其制法中，该第一导电元件与该第二导电元件为交错排列。
前述的电子封装件及其制法中，还包括设置支撑件于该第一与第二基板之间。例如，该支撑件未电性连接该第一与第二基板。
前述的电子封装件及其制法中，还包括设置第二电子元件于该第二基板上。又包括形成第二封装层于该第二基板上，且该第二封装层包覆该第二电子元件。
前述的电子封装件及其制法中，还包括设置封装件于该第二基板上。
由上可知，本发明的电子封装件及其制法中，通过不同构造的第一导电元件(包含有金属块)与第二导电元件支撑该第二基板，经过回焊该些导电元件之后，能分散温度升降所产生的应力集中，以避免该第二基板发生局部凹凸不平，故相比于现有技术，本发明于模压过程中，该第二基板的表面可有效接触模具表面，以避免该第一封装层的模流产生向上推挤力，而造成该第二基板发生破裂的问题。
再者，通过该第二基板结合至该第一电子元件上，使该第二基板与该第一基板之间的距离得以固定，故相比于现有技术，本发明于回焊该些第一与第二导电元件后，该些第一与第二导电元件所构成的接点能维持良好的电性连接品质，且该些第一与第二导电元件所排列成的栅状阵列的共面性良好，因而接点应力保持平衡而不会造成该第一与第二基板的间呈倾斜接置，以避免产生接点偏移的问题。
附图说明
图1为现有堆叠式电子封装件的剖面示意图；
图2A至图2C为本发明电子封装件的制法的剖面示意图；其中，图2B’为图2B的另一实施例；
图2D及图2D’为图2C的其它实施例的剖面示意图；
图3为本发明的电子封装件的第一基板的上视示意图；以及
图4为本发明的电子封装件的第一基板设有第一与第二导电元件的局部上视示意图。
符号说明：
1,2,2’,2” 电子封装件
1a 第一封装结构
1b 第二封装结构
10,20 第一基板
11,21 第一电子元件
110,140,210 导电凸块
111,141 底胶
12,22 第二基板
120 焊锡球
13 封装胶体
14,24 第二电子元件
20a,20b 第一线路层
200 电性接触垫
201,202,220,221 电性接点
203 植球垫
22a,22b 第二线路层
23 第一封装层
240 焊线
241 黏着层
25 第二封装层
26 封装件
260 载体
261 第三电子元件
262 封装体
263,28 焊球
27 支撑件
270,280 金属块
271,281 导电材
28a 第一导电元件
28b 第二导电元件
29 结合层
30 定位垫
S 切割路径
A 第一堆叠区
B 第二堆叠区
C 置晶区。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2C为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，提供一第一基板20与一第二基板22。该第一基板20上设有至少一第一电子元件21，且该第二基板22下侧形成有多个第一导电元件28a、多个第二导电元件28b与一如薄膜(film)或散热材的结合层29。
于本实施例中，该第一基板20与第二基板22为线路板，其分别具有多个第一线路层20a,20b与多个第二线路层22a,22b，该第一线路层20a,20b包含电性接触垫200、电性接点201,202与植球垫203，且该第二线路层22a,22b包含电性接点220,221。应可理解地，该第一基板20与第二基板22亦可为其它承载晶片的承载件，并不限于上述。
此外，该第一电子元件21通过多个导电凸块210以覆晶方式设于该第一基板20上侧的电性接触垫200上。
又，该第一导电元件28a形成于该第二基板22下侧的电性接点220上，且该第一导电元件28a具有金属块280与包覆该金属块280的导电材281，抑或该第一导电元件28a仅为金属块280(不含导电材)，其中，该金属块280为铜球，且该导电材281为焊锡材，如镍锡、锡铅或锡银，但不限于此。
另外，该第二导电元件28b形成于该第二基板22下侧的电性接点221上，且该第二导电元件28b为焊锡凸块。具体地，该第一导电元件28a与该第二导电元件28b的数量比例可为1：0.5～1：1.5，较佳为1：1。有关该些导电元件的实施例不限于上述。
如图2B所示，将该第二基板22堆叠于该第一基板20上，其中，该第二基板22通过该结合层29结合于该第一电子元件21上，并令该些第一导电元件28a与第二导电元件28b电性连接该第一基板20的电性接点201,202，使该第二基板22通过该些第一导电元件28a与第二导电元件28b电性连接该第一基板20。
又，如图3所示，该第一基板20(或该第二基板22)的表面定义有一置晶区C、及环绕该置晶区C的第一堆叠区A与第二堆叠区B，该置晶区C设有多个电性接触垫200(图3未显示)，且该第一堆叠区A与该第二堆叠区B设有多个电性接点201,202，其中，该第一堆叠区A的电性接点201,202的密度大于该第二堆叠区B的电性接点202的密度。
另外，于该第一堆叠区A中，部分该电性接点201上结合该第一导电元件28a，而部分该电性接点202上结合该第二导电元件28b，且如图4所示，该些第一导电元件28a与该些第二导电元件28b为交错排列，以通过该第一导电元件28a(例如具有金属块280与包覆该金属块280的导电材281)的结构特征，不仅可提供支撑效果，且能避免桥接(solder ballbridge)。于该第二堆叠区B中，该些电性接点202上均结合该第二导电元件28b(例如为焊锡凸块)，以降低成本。
应可理解地，如图2B’所示，亦可先将该结合层29设于该第一电子元件21上，另该第一导电元件28a与第二导电元件28b先设于该第一基板20的电性接点201,202上，再堆叠该第二基板22于该第一基板20上，以呈现图2B的状态。
如图2C所示，形成第一封装层23于该第一基板20上侧与该第二基板22下侧之间，使该第一封装层23包覆该第一电子元件21、该些第一导电元件28a与第二导电元件28b、该结合层29与该些导电凸块210。
接着，沿切割路径S进行切单制造方法，以制成多个电子封装件2。
于本实施例中，由于该结合层29形成于该第二基板22与该第一电子元件21之间，故该第一封装层23不会填入该第二基板22与该第一电子元件21之间。
此外，该第一基板20下侧的植球垫203上可形成有如焊球28的导电元件，以供接置如电路板或另一线路板的电子结构。
于另一实施例中，如图2D所示的电子封装件2’中，可通过一黏着层241设置至少一第二电子元件24于该第二基板22上侧上，再形成第二封装层25于该第二基板22上侧，且该第二封装层25包覆该第二电子元件24。例如，该第二电子元件24通过多个焊线240以打线方式电性连接该第二基板22上侧的第二线路层22a，且该第二封装层25还包覆该些焊线240。于其它实施例中，该第二电子元件24也可以覆晶方式设于该第二基板22上侧。
或者，如图2D’所示，亦可设置至少一封装件26于该第二基板22上。例如，该封装件26包含一载体260、设置并电性连接至该载体260的第三电子元件261、及包覆该第三电子元件261的封装体262。具体地，该封装件26通过多个如焊球263的导电元件电性连接该第二基板22，且该第三电子元件261的封装方式可为打线(如图2D’所示)、覆晶或嵌埋等，但并无特别限制。
于另一实施例中，如图2D所示，也可设置至少一支撑件27于该第一与第二基板20,22之间，使该第二基板22通过该支撑件27堆叠于该第一基板20上，且该第一封装层23还包覆该支撑件27。
具体地，该支撑件27的构造类似该第一导电元件28a的构造，即具有金属块270与包覆该金属块270的导电材271，其中，该金属块270为铜球，且该导电材271为焊锡材，如镍锡、锡铅或锡银，但不限于此。
此外，于制造方法中，该支撑件27可与该第一导电元件28a一同制作，且该第一基板20与第二基板22可通过定位垫30的设计，以利于该支撑件27的定位。具体地，该定位垫30未电性连接该第一基板20的第一线路层20a,20b与该第二基板22的第二线路层22a,22b，致使该支撑件27未电性连接该第一基板20与第二基板22，因而该支撑件27可视为虚设金属件(dummy metal member)。应可理解地，如图2D’所示，该支撑件27也可直接设于该第一基板20的表面与该第二基板22的表面，而省略该定位垫30的制作。
又，如图3所示，该定位垫30(或该支撑件27)位于该第一堆叠区A与该第二堆叠区B的交界处(或该第一基板20的表面的四个角落处)。应可理解地，该定位垫30(或该支撑件27)可位于该第一基板20的表面的任一处，并不限于上述。
另外，上述电子元件(如第一电子元件21、第二电子元件24或第三电子元件261)为主动元件、被动元件或其二者组合等，其中，该主动元件例如为半导体晶片，且该被动元件例如为电阻、电容及电感。
本发明的制法中，通过不同构造的第一导电元件28a与第二导电元件28b支撑该第二基板22，经过回焊该些第二导电元件28b(及第一导电元件28a，视其是否含有焊锡材料)之后，能分散温度升降所产生的应力集中，以避免该第二基板22发生局部凹凸不平，故相比于现有技术，本发明于模压过程中，该第二基板22的表面可有效接触模具表面，以避免该第一封装层23的模流产生向上推挤力。因此，本发明的制法不仅能避免该些第一导电元件28a与第二导电元件28b发生桥接的问题，且能减少应力集中以避免该第二基板22发生破裂(crack)。
此外，通过将该第二基板22通过该结合层29结合至该第一电子元件21上，以得到较佳的支撑效果。具体地，该第二基板22与该第一基板20之间的距离得以固定，因而能控制该些第一与第二导电元件28a,28b的高度与体积，故相比于现有技术，于回焊该些第二导电元件28b(及第一导电元件28a)后，该些第一与第二导电元件28a,28b所构成的接点能维持良好的电性连接品质，且该些第一与第二导电元件28a,28b所排列成的栅状阵列(gridarray)的共面性(coplanarity)良好，致使接点应力(stress)保持平衡而不会造成该第一与第二基板20,22之间呈倾斜接置，以避免产生接点偏移的问题。因此，本发明的制法能提高产品良率。
又，通过该结合层29的设计，以于形成该第一封装层23的模压过程中，于该第一封装层23的封装材产生向上推挤力时，该结合层29亦可吸收应力，以减少该些第一与第二导电元件28a,28b所承受的应力，故能避免该些第一与第二导电元件28a,28b发生破裂。
另外，该支撑件27也能提供支撑的效果，以避免该第二基板22发生崩塌而导致该些第二导电元件28b(及第一导电元件28a)发生桥接的问题。
本发明提供一种电子封装件2,2’,2”，其包括：第一基板20、设于该第一基板20上的第一电子元件21、通过多个第一导电元件28a与第二导电元件28b堆叠于该第一基板20上的第二基板22、以及设于该第一基板20与第二基板22之间的第一封装层23。
所述的第一电子元件21通过多个导电凸块210设于该第一基板20上。
所述的第二基板22通过该些第一导电元件28a与第二导电元件28b电性连接该第一基板20并通过结合层29结合至该第一电子元件21上，且该第一导电元件28a的构造与该第二导电元件28b的构造不同。例如，该第一导电元件28a为金属块、或具有金属块280与包覆该金属块280的导电材281，且该第二导电元件28b为焊锡凸块。
所述的第一封装层23包覆该第一电子元件21、该些第一导电元件28a与第二导电元件28b。
于一实施例中，该第一导电元件28a与该第二导电元件28b的数量比例为1：0.5～1：1.5。
于一实施例中，该结合层29为薄膜(film)或散热材。
于一实施例中，该第一基板20的表面定义有一置晶区C、及环绕该置晶区C的第一堆叠区A与第二堆叠区B，该置晶区C设有该第一电子元件21，且该第一堆叠区A与该第二堆叠区B设有多个电性接点201,202，以结合该第一导电元件28a及/或该第二导电元件28b，其中，其中，该第一堆叠区A的电性接点201,202的密度大于该第二堆叠区B的电性接点202的密度。
于一实施例中，该第一基板20具有定位垫30。
于一实施例中，该第一导电元件28a与该第二导电元件28b为交错排列。
于一实施例中，该电子封装件2’,2”还包括至少一支撑件27，其设于该第一与第二基板20,22之间。例如，该支撑件27未电性连接该第一与第二基板20,22。
于一实施例中，该电子封装件2’还包括设于该第二基板22上的第二电子元件24及第二封装层25，且该第二封装层25包覆该第二电子元件24。
于一实施例中，该电子封装件2”还包括设于该第二基板22上的至少一封装件26。
综上所述，本发明的电子封装件及其制法，主要通过不同构造的第一与第二导电元件支撑该第二基板，以于模压过程中，避免该些导电元件发生桥接的问题，且避免该第二基板发生破裂。
此外，通过该第二基板结合至该第一电子元件上，以得到较佳的支撑效果，且能提高产品良率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (28)

1.一种电子封装件，其特征为，该电子封装件包括：
第一基板；
第一电子元件，其设于该第一基板上；
第二基板，其通过多个第一导电元件与第二导电元件堆叠于该第一基板上并通过结合层结合至该第一电子元件上，其中，该第一导电元件的构造与该第二导电元件的构造不同；以及
第一封装层，其形成于该第一基板与第二基板之间，以包覆该第一电子元件、该第一导电元件与该第二导电元件。
2.如权利要求1所述的电子封装件，其特征为，该第一导电元件与该第二导电元件的数量比例为1：0.5～1：1.5。
3.如权利要求1所述的电子封装件，其特征为，该第一导电元件为金属块。
4.如权利要求1所述的电子封装件，其特征为，该第一导电元件具有金属块与包覆该金属块的导电材。
5.如权利要求1所述的电子封装件，其特征为，该第二导电元件为焊锡凸块。
6.如权利要求1所述的电子封装件，其特征为，该结合层为薄膜(film)或散热材。
7.如权利要求1所述的电子封装件，其特征为，该第一基板的表面定义有一置晶区、及环绕该置晶区的第一堆叠区与第二堆叠区，该置晶区设有该第一电子元件，且该第一堆叠区与该第二堆叠区设有多个电性接点，以结合该第一导电元件及/或该第二导电元件，其中，该第一堆叠区的电性接点的密度大于该第二堆叠区的电性接点的密度。
8.如权利要求1所述的电子封装件，其特征为，该第一基板具有定位垫。
9.如权利要求1所述的电子封装件，其特征为，该第一导电元件与该第二导电元件为交错排列。
10.如权利要求1所述的电子封装件，其特征为，该电子封装件还包括设于该第一与第二基板之间的支撑件。
11.如权利要求10所述的电子封装件，其特征为，该支撑件未电性连接该第一与第二基板。
12.如权利要求1所述的电子封装件，其特征为，该电子封装件还包括设于该第二基板上的第二电子元件。
13.如权利要求12所述的电子封装件，其特征为，该电子封装件还包括形成于该第二基板上且包覆该第二电子元件的第二封装层。
14.如权利要求1所述的电子封装件，其特征为，该电子封装件还包括设于该第二基板上的封装件。
15.一种电子封装件的制法，其特征为，该制法包括：
提供第一基板及第二基板，该第一基板上设有第一电子元件；
将该第二基板通过第一导电元件与第二导电元件堆叠于该第一基板上，并使该第二基板通过结合层结合至该第一电子元件上，且该第一导电元件的构造与该第二导电元件的构造不同；以及
形成第一封装层于该第一基板与第二基板之间，以包覆该第一电子元件、该第一导电元件与该第二导电元件。
16.如权利要求15所述的电子封装件的制法，其特征为，该第一导电元件与该第二导电元件的数量比例为1：0.5～1：1.5。
17.如权利要求15所述的电子封装件的制法，其特征为，该第一导电元件为金属块。
18.如权利要求15所述的电子封装件的制法，其特征为，该第一导电元件具有金属块与包覆该金属块的导电材。
19.如权利要求15所述的电子封装件的制法，其特征为，该第二导电元件为焊锡凸块。
20.如权利要求15所述的电子封装件的制法，其特征为，该结合层为薄膜(film)或散热材。
21.如权利要求15所述的电子封装件的制法，其特征为，该第一基板的表面定义有一置晶区、及环绕该置晶区的第一堆叠区与第二堆叠区，该置晶区设有该第一电子元件，且该第一堆叠区与该第二堆叠区设有多个电性接点，以结合该第一导电元件及/或该第二导电元件，其中，该第一堆叠区的电性接点的密度大于该第二堆叠区的电性接点的密度。
22.如权利要求15所述的电子封装件的制法，其特征为，该第一基板具有定位垫。
23.如权利要求15所述的电子封装件的制法，其特征为，该第一导电元件与该第二导电元件为交错排列。
24.如权利要求15所述的电子封装件的制法，其特征为，该制法还包括设置支撑件于该第一与第二基板之间。
25.如权利要求24所述的电子封装件的制法，其特征为，该支撑件未电性连接该第一与第二基板。
26.如权利要求15所述的电子封装件的制法，其特征为，该制法还包括设置第二电子元件于该第二基板上。
27.如权利要求26所述的电子封装件的制法，其特征为，该制法还包括形成第二封装层于该第二基板上，以包覆该第二电子元件。
28.如权利要求15所述的电子封装件的制法，其特征为，该制法还包括设置封装件于该第二基板上。
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