JP3858854B2 - 積層型半導体装置 - Google Patents

積層型半導体装置 Download PDF

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Publication number
JP3858854B2
JP3858854B2 JP2003180200A JP2003180200A JP3858854B2 JP 3858854 B2 JP3858854 B2 JP 3858854B2 JP 2003180200 A JP2003180200 A JP 2003180200A JP 2003180200 A JP2003180200 A JP 2003180200A JP 3858854 B2 JP3858854 B2 JP 3858854B2
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Prior art keywords
semiconductor device
wiring board
wiring
stacked semiconductor
semiconductor element
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Expired - Fee Related
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JP2003180200A
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JP2005019568A (ja
Inventor
隆雄 西村
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to JP2003180200A priority Critical patent/JP3858854B2/ja
Priority to US10/867,722 priority patent/US7217993B2/en
Priority to TW093117314A priority patent/TWI282153B/zh
Priority to CNB2004100597875A priority patent/CN1326234C/zh
Priority to KR1020040046997A priority patent/KR100627099B1/ko
Publication of JP2005019568A publication Critical patent/JP2005019568A/ja
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Publication of JP3858854B2 publication Critical patent/JP3858854B2/ja
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に係わり、特に複数の半導体装置および半導体素子を積層した三次元構造を有する積層型半導体装置に関する。
【０００２】
【従来の技術】
近年の電子機器の発達に伴い、電子機器に使用される半導体装置には、小型化、薄型化、多機能化、高機能化、高密度化が益々要求されるようになっている。
このような要求に対処すべく、半導体パッケージの構造は、複数の半導体装置あるいは複数の半導体素子を積層した三次元構造の積層型半導体装置に移行しつつある（例えば、特許文献１参照。）。
【０００３】
ところで、近年の電子機器の発達により、電子機器が他の電子機器から発する不要電波により誤動作する可能性が無視できない問題として現実化しつつあり、ＥＭＩ（Electro Magnetic Interference/電磁妨害放射規制: 電子機器が他の電子機器への妨害を排除するために電子機器から電磁気的雑音( 電波) の放射，伝搬を規制するもの）に対応した電子機器が求められるようになってきている。
【０００４】
複数の半導体装置および半導体素子を積層した構造の積層型半導体装置において、例えばＲＦ（Radio Frequency)系アナログ信号用半導体装置のような高周波回路素子を混載する場合には、放出される電磁放射( 不要輻射/ 輻射電磁ノイズ/ 電波ノイズ) を極力小さなレベルに抑制する必要がある。
このような電磁放射に対処した従来の積層型半導体装置の例として、特許文献２に記載されている積層型半導体装置について図９を用いて説明する。図９に示す積層型半導体装置は、キャビティ部２に高周波回路素子３を搭載し、かつ金属ベース８上に形成された第１の誘電体基板１上に、裏面にグランド導体を設け、かつ高周波回路素子４を搭載した第２の誘電体基板５が積層されている。第１の誘電体基板１上に、第２の誘電体基板５を覆うように金属カバー６を設け、金属カバーの端部が第１の誘電体基板１に設けられたビアホール７と接続され、金属カバー６が導電性接着剤等を用いて第１の誘電体基板１と接続されている。金属カバー６が高周波回路素子４を電磁的にシールドし、高周波回路素子４および高周波回路素子３を気密封止している。
【０００５】
【特許文献１】
特開２００１−２２３２９７号公報（第８頁、第１５図）
【０００６】
【特許文献２】
特開２０００−１７４２０４号公報（第３−５頁、第２図）
【０００７】
【発明が解決しようとする課題】
しかし、上記特許文献１に記載された積層型半導体装置においては、ＥＭＩ規制対策としての電磁シールドについて特に記載されていない。また上記特許文献２に記載されている積層型半導体装置は、ＥＭＩ規制対策について考慮されているが、基板１の形状が掘り込み形状（キャビティ）であり、また気密封止を行う構造のため高価となる。さらに金属カバーを用いる構造のため装置を薄型化することが困難であるという問題がある。そこで、高周波回路素子を混載した積層型半導体装置において、高周波回路素子からの電磁放射のレベルを極力小さく抑制でき、かつ安価で小型化を実現した積層型半導体装置が要望される。
【０００８】
【課題を解決するための手段】
上記課題を解決するため、本発明の一観点によれば、上面に半導体素子が実装されている第１の配線基板と、この第１の配線基板と電気的に接続される複数の電極端子を介して該第１の配線基板の上に積層される第２の配線基板と、該半導体素子の周囲に配設され、かつ第１の配線基板および第２の配線基板に設けられた接地配線層と接続された導体支持部材を有し、複数の電極端子は，半導体素子に対して該導体支持部材よりも外側に配置されている積層型半導体装置が提供される。
【０００９】
本発明は、このような構成にすることにより、混載されている高周波回路素子からの電磁放射レベルを抑制した積層型半導体装置の構造を従来に比べ薄型化（小型化）かつ安価にでき、また配線基板間を接続している電極端子以外に、導体支持部材によっても配線基板間が接続されるので配線基板の反り等に起因する電極端子接続部の製造不良を低減でき、配線基板間の接続信頼性を向上した積層型半導体装置を提供できる。
【００１０】
【発明の実施の形態】
図１は、本発明の第１の実施例による積層型半導体装置の断面図、図２は、図１の積層型半導体装置における導体支持部材１２の形状を説明するための平面図、図３は図１の積層型半導体装置における接地配線層２６のパターン形状を説明するための平面図である。図において、９，１８は配線基板、１１，２６は接地配線層、１２は導体支持部材、１３，１５，１７，２０，２５，２７は接続パッド、１０，２１，２２，２３は半導体素子、２４はワイヤを示す。
【００１１】
本発明の第１の実施例による積層型半導体装置において、配線基板９は、ガラスエポキシ樹脂、またはセラミック等の材料で構成され、配線基板９の上面には半導体素子１０がフリップチップ実装され、半導体素子１０はエポキシ等の絶縁樹脂により配線基板９の上面に接着されている。ここで半導体素子１０は例えばＲＦ系アナログ信号用半導体装置のような高周波回路素子である。配線基板９の内部には接地配線層１１が埋設されていて、この接地配線層１１は、導体支持部材１２を接続するための接続パッド１３およびグランド端子１４との接続パッド１５に接続されている。なお、接続パッド１３は配線基板９上面の半導体素子１０の実装されている周囲に枠状に形成されている。外部回路との接続を行うための外部電極端子１６は接続パッド１７上に半田ボール形成されている。また、配線基板９の周囲には配線基板９と配線基板１８間を電極端子としての半田ボール１９を介して電気的に接続するための多数の接続パッド２０が配列されている。
【００１２】
配線基板１８は、ガラスエポキシ樹脂、またはセラミック等の材料で構成された多層配線基板である。配線基板１８の上面には半導体素子２１がフリップチップ実装され、半導体素子２１はエポキシ等の絶縁樹脂により配線基板１８の上面に接着されている。そして、半導体素子２１の上に半導体素子２２が接着剤で接着され、さらにその上に半導体素子２３が接着剤で接着されている。半導体素子２２および半導体素子２３と配線基板１８間の回路接続は金のワイヤ２４により配線基板１８の接続パッド２５にワイヤボンディングされている。配線基板１８上の半導体素子２１、半導体素子２２、半導体素子２３は全体をエポキシ等で樹脂封止される。
【００１３】
図３に示すように配線基板１８の下面には、銅（Cu）、ニッケル（Ni）、モリブデン（Mo）、マンガン（Mn）等の金属からなる接地配線層２６が設けられている。この接地配線層２６は、めっき法、ラミネート法、印刷法、蒸着法等により形成される。図３（A ）は接地配線層２６をベタのパターンで形成したもので、図３（B ）は接地配線層２６をメッシュのパターンで形成したものである。配線基板１８の上面と下面の導体配線密度の違いにより、配線基板１８が反ることがあるので、設計上、図３（B ）のメッシュパターンを採用した方が良い場合がある。また、配線基板１８の下面の周囲には配線基板１８と配線基板９を半田ボール１９介して電気的に接続するための多数の接続パッド２７が配列されている。図３において２８は半導体素子１０が実装される領域を示している。
【００１４】
半導体支持部材１２は、アルミ（Al）、銅、ニッケル、チタン（Ti）、コバルト（Co）、タングステン（W ）、鉄（Fe）等の金属、またはこれらの金属の合金からなるシートから、打ち抜きまたはエッチングにより、図２に示すように枠状に形成する。枠状の導体支持部材１２は配線基板９上面の接続パッド１３および配線基板１８下面の接地配線層２６と導電性接着剤により接合する。また同時に、配線基板９の接続パッド２０および配線基板１８下面の接続パッド２７間を半田ボール１９で接続する。
【００１５】
本発明の第１の実施例による積層型半導体装置は、このような構成により半導体素子１０が接地電位の導体により上面、下面および側面を囲まれているので、半導体素子１０から発生する不要輻射を遮断して、他の素子への悪影響を低減できる。 また、導体支持部材１２により配線基板９および配線基板１８が固定され、両配線基板間の距離が一定に保たれるので、積層型半導体装置の組立て時における、基板の反りに起因する半田ボール１９接続部分の製造不良が低減できる。また、両配線基板が枠状の導体支持部材１２によって接続固定されるので積層型半導体装置完成体の両配線基板間の接続信頼性が向上する。そして配線基板に実装されている半導体素子からの不要輻射を遮断できる構造を具備した積層型半導体装置の薄型化（小型化）を実現できる。なお、半導体素子１０の配線基板９に対する実装方法はフリップチップ実装でなく、例えばＴＡＢ（Tape Automated Bonding）実装方法等でもよい。
【００１６】
図４は、本発明の第２の実施例による積層型半導体装置の断面図である。
第２の実施例では、上部の配線基板２９の接地配線層３０が配線基板２９の内部に埋設されている点が前述の第１の実施例と相違している。その他の構造については第１の実施例と同じである。従って、第２の実施例による積層型半導体装置は第１の実施例による積層半導体装置と同様の効果を奏する。さらに第２の実施例による積層型半導体装置では接地配線層３０が配線基板２９の内部に埋設されているので、それだけ接地配線層３０が配線基板２９上に実装されている半導体素子２１〜２３に接近でき、半導体素子２１〜２３により構成される回路の高速伝送特性を向上させることができる。
【００１７】
図５は、本発明の第３の実施例による積層型半導体装置の断面図であり、図６は、図５における導体支持部材３１の配置を説明するための平面図である。第３の実施例では、導体支持部材３１として半田ボールを使用している点が第１の実施例と相違している。導体支持部材３１としての半田ボールは、配線基板９と配線基板１８間を電気的に接続している電極端子としての半田ボール１９の内側で、かつ半導体素子１０の周囲に配列する。第３の実施例では、導体支持部材３１として、通常の半田ボールを使用しているので、第１の実施例および第２の実施例において枠体の導体支持部材を使用するのに比べて安価に製造できる。
【００１８】
図７は、本発明の第４の実施例による積層型半導体装置の断面図である。
第４の実施例では、第３の実施例において配線基板９上に実装されている半導体素子１０の上面と配線基板１８の下面に形成された接地配線層２６の間に、例えば銀粒子を含む樹脂接着剤のような高熱伝導性接着剤３２を充填する。第４の実施例による積層型半導体装置では、半導体素子１０上面からの発熱を接地配線層２６および導体支持部材３１としての半田ボールを経由して熱を伝える経路が出来るので、半導体素子１０の放熱効果を高めることができる。
【００１９】
図８は、本発明の第５の実施例による積層型半導体装置の断面図である。
第５の実施例では、配線基板３３の上面に半導体素子３４およびコンデンサ等のチップ部品３５が実装されている。配線基板３３の内部には接地配線層１１が埋設され、接地配線層１１は、導体支持部材３１と接続するための接続パッド１３およびグランド端子１４と接続するための接続パッド１５に接続されている。
【００２０】
また配線基板３３の上面の周囲には配線基板３３と配線基板３６を半田ボール１９を介して電気的に接続するための多数の接続パッド２０が配列されている。
配線基板３６の上面には半導体素子１０が実装され、導体支持部材３７と接続するための接続パッド３８が形成され、その周囲には配線基板３６と配線基板１８を半田ボール３９を介して電気的に接続するための多数の接続パッド４０が配列されている。配線基板３６の下面には接地配線層４１、その周囲には配線基板３３と配線基板３６を半田ボール１９を介して電気的に接続するための多数の接続パッド２７が配列されている。なお導体支持部材３７と接続するための接続パッド３８と接地配線層４１は配線基板３６内部で導体部材で接続されている。
【００２１】
さらにその上に積層される配線基板１８および配線基板１８に実装される半導体素子の構成は、第４の実施例における配線基板１８の構成と同じである。
第５の実施例は、これら３個の配線基板３３、３６，１８を導体支持部材としての半田ボール３１、３７および、配線基板間を電気的に接続するための半田ボール１９，３９で接続し３段に積層した積層型半導体装置の例である。この第５の実施例では、半導体素子３４、チップ部品３５および半導体素子１０は接地電位の導体により上面、下面および側面を囲まれているので、これら半導体素子から発生する不要輻射を遮断して、他の素子への悪影響を低減できる。なお第５の実施例では配線基板を３段に積層した例であるが、さらに多段化することも可能である。第５の実施例によれば、複数の高周波回路素子を使用する場合も、多段化することにより容易に本発明を適用できる。
【００２２】
（付記１）上面に半導体素子が実装されている第１の配線基板と、該第１の配線基板と電気的に接続される複数の電極端子を介して該第１の配線基板の上に積層される第２の配線基板と、該半導体素子の周囲に配設され、かつ該第１の配線基板および第２の配線基板に設けられた接地配線層と接続された導体支持部材を有することを特徴とする積層型半導体装置。
【００２３】
（付記２）前記第１の配線基板および第２の配線基板の少なくとも一方の接地配線層は基板内部に埋設されていることを特徴とする付記１記載の積層型半導体装置。
（付記３）前記導体支持部材は、枠形状であることを特徴とする付記１または２記載の積層型半導体装置。
【００２４】
（付記４）前記導体支持部材は、複数のはんだボールで構成されていることを特徴とする付記１または２記載の積層型半導体装置。
（付記５）前記第１の配線基板に実装されている該半導体素子はフリップチップにより実装されていることを特徴とする付記１〜４の何れかに記載の積層型半導体装置。
【００２５】
（付記６）前記第１の配線基板に実装されている該半導体素子の上面と前記第２の配線基板に設けられた接地配線層との間に高熱伝導性部材を充填したことを特徴とする付記１〜５の何れかに記載の積層型半導体装置。
【００２６】
【発明の効果】
以上説明したように、本発明によれば、混載されている高周波回路素子からの電磁放射レベルを抑制した積層型半導体装置の構造を従来に比べ薄型化（小型化）かつ安価にでき、また配線基板間を接続している電極端子以外に、導体支持部材によっても配線基板間が接続されるので配線基板の反り等に起因する電極端子接続部の製造不良を低減でき、配線基板間の接続信頼性を向上した積層型半導体装置を提供できる。
【図面の簡単な説明】
【図１】 本発明の第１の実施例による積層型半導体装置の断面図。
【図２】 図１の積層型半導体装置における導体支持部材の形状を説明するための平面図。
【図３】 図１の積層型半導体装置における接地配線層のパターン形状を説明するための平面図。
【図４】 本発明の第２の実施例による積層型半導体装置の断面図。
【図５】 本発明の第３の実施例による積層型半導体装置の断面図。
【図６】 図５の積層型半導体装置における導体支持部材の形状を説明するための平面図。
【図７】 本発明の第４の実施例による積層型半導体装置の断面図。
【図８】 本発明の第５の実施例による積層型半導体装置の断面図。
【図９】 従来の積層型半導体装置の例を説明するための断面図。
【符号の説明】
９、１８、２９、３３，３６ 配線基板
１０、２１、２２、２３、３４ 半導体素子
１１、２６，３０、４１ 接地配線層
１２、３１、３７ 導体支持部材
１３、１５，１７、２０、２５、２７、３８，４０ 接続パッド
１４ グランド端子
１６ 外部電極端子
３２ 高熱伝導性接着剤
３５ チップ部品

Claims (5)

  1. 上面に半導体素子が実装されている第１の配線基板と、該第１の配線基板と電気的に接続される複数の電極端子を介して該第１の配線基板の上に積層される第２の配線基板と、該半導体素子の周囲に配設され、かつ該第１の配線基板および第２の配線基板に設けられた接地配線層と接続された導体支持部材を有し、
    該複数の電極端子は，該半導体素子に対して該導体支持部材よりも外側に配置されていることを特徴とする積層型半導体装置。
  2. 前記第１の配線基板および第２の配線基板の少なくとも一方の接地配線層は基板内部に埋設されていることを特徴とする請求項１記載の積層型半導体装置。
  3. 前記導体支持部材は、枠形状であることを特徴とする請求項１または２記載の積層型半導体装置。
  4. 前記導体支持部材は、複数の半田ボールで構成されていることを特徴とする請求項１または２記載の積層型半導体装置。
  5. 前記第１の配線基板に実装されている該半導体素子の上面と前記第２の配線基板に設けられた接地配線層との間に高熱伝導性部材を充填したことを特徴とする請求項１〜４の何れかに記載の積層型半導体装置。
JP2003180200A 2003-06-24 2003-06-24 積層型半導体装置 Expired - Fee Related JP3858854B2 (ja)

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JP2003180200A JP3858854B2 (ja) 2003-06-24 2003-06-24 積層型半導体装置
US10/867,722 US7217993B2 (en) 2003-06-24 2004-06-16 Stacked-type semiconductor device
TW093117314A TWI282153B (en) 2003-06-24 2004-06-16 Stacked-type semiconductor device
CNB2004100597875A CN1326234C (zh) 2003-06-24 2004-06-23 堆栈型半导体装置
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