TWI546932B - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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Publication number
TWI546932B
TWI546932B TW103124500A TW103124500A TWI546932B TW I546932 B TWI546932 B TW I546932B TW 103124500 A TW103124500 A TW 103124500A TW 103124500 A TW103124500 A TW 103124500A TW I546932 B TWI546932 B TW I546932B
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Taiwan
Prior art keywords
semiconductor device
conductive
semiconductor
layer
semiconductor package
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TW103124500A
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English (en)
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TW201605013A (zh
Inventor
江政嘉
林欣達
黃富堂
王愉博
王隆源
徐逐崎
施嘉凱
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矽品精密工業股份有限公司
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Priority to TW103124500A priority Critical patent/TWI546932B/zh
Priority to CN201410364624.1A priority patent/CN105280598B/zh
Priority to US14/616,013 priority patent/US9356008B2/en
Publication of TW201605013A publication Critical patent/TW201605013A/zh
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Publication of TWI546932B publication Critical patent/TWI546932B/zh

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Description

半導體封裝件及其製法
本發明係關於一種半導體封裝件及其製法，特別是指一種以導電柱與導通球作電性連接之堆疊式半導體封裝件及其製法。
在堆疊式半導體封裝件之技術中，常於上基板與下基板上分別形成供電性連接之複數銲球，並將該上基板貼合該下基板以透過該些銲球互相電性連接，且藉由該些銲球控制該半導體封裝件之高度以及該上基板與該下基板間之間隙。
但是，該些銲球於迴銲(reflow)作業時會形成軟塌狀態，因而不易控制該半導體封裝件之高度，且該些銲球間之融合處需具有較大的空間，故無法廣泛用於具有更精細間距的半導體封裝件上。
第1A圖與第1B圖係繪示習知技術之半導體封裝件1及其製法之剖視示意圖。
如1A圖所示，先提供具有複數第一銲墊101之第一基板10，並形成複數具有間距d1之第一銲球11於該些第 一銲墊101上，且藉由複數銲球121將半導體晶片12設置於該第一基板10上，再形成具有複數開口131之封裝膠體13於該第一基板10上，以包覆該半導體晶片12及該些銲球121與外露出該些第一銲球11之頂部及側部。同時，提供具有複數第二銲墊141之第二基板14，並形成複數對應該些第一銲球11之第二銲球15於該些第二銲墊141上。
如1B圖所示，對該些第一銲球11與該些第二銲球15進行迴銲作業，以共同形成熔融狀態而互相接合成複數導電體16。
上述習知技術之缺點在於：該些第一銲球11與該些第二銲球15於迴銲作業時會形成軟塌狀態，因而不易控制該半導體封裝件1之高度、或者該封裝膠體13與該第二基板14間之間隙17，且該些第一銲球11或該些第二銲球15之間容易互相橋接而短路，加上該些第一銲球11與該些第二銲球15之融合處需具有較大的空間，故無法廣泛地用於具有更精細間距的半導體封裝件1上。
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。
本發明係提供一種半導體封裝件，其包括：第一半導體裝置，係具有相對之第一頂面與第一底面；複數導通球，係形成於該第一半導體裝置之第一頂面；第二半導體裝置，係具有相對之第二頂面與第二底面，且該第二底面係面向該第一半導體裝置之第一頂面；以及複數導電柱，係 形成於該第二半導體裝置之第二底面，並分別接合該些導通球以電性連接該第一半導體裝置及該第二半導體裝置，其中，該導電柱之高度係小於300微米。
本發明亦提供一種半導體封裝件，其包括：第一半導體裝置，係具有第一頂面與第一底面；複數導通球，係形成於該第一半導體裝置之第一頂面；第二半導體裝置，係具有相對之第二頂面與第二底面，且該第二底面係面向該第一半導體裝置之第一頂面；以及複數導電柱，係形成於該第二半導體裝置之第二底面，並分別接合該些導通球以電性連接該第一半導體裝置及該第二半導體裝置，其中，該導電柱係為圓柱體且其高度係大於直徑的二分之一。
本發明又提供一種半導體封裝件，其包括：第一半導體裝置，係具有第一頂面與第一底面；複數導通球，係形成於該第一半導體裝置之第一頂面；第二半導體裝置，係具有相對之第二頂面與第二底面，且該第二底面係面向該第一半導體裝置之第一頂面；以及複數導電柱，係形成於該第二半導體裝置之第二底面，並分別接合該些導通球以電性連接該第一半導體裝置及該第二半導體裝置，其中，該導電柱係為橢圓柱體且其長軸長度係大於短軸長度的1.1倍。
本發明另提供一種半導體封裝件之製法，其包括：提供具有相對之第一頂面與第一底面之第一半導體裝置、以及具有相對之第二頂面與第二底面之第二半導體裝置，該第一半導體裝置之第一頂面係形成有複數導通球，且該第 二半導體裝置之第二底面係形成有複數導電柱，其中，該導電柱之高度係小於300微米；以及將該第一半導體裝置上之該些導通球分別對應該第二半導體裝置上之該些導電柱，以將該些導通球分別接合該些導電柱而電性連接該第一半導體裝置及該第二半導體裝置。
上述第一半導體裝置或該第二半導體裝置可為基板、中介板、半導體晶片、半導體晶圓或半導體封裝結構。
上述導通球可為單層球體、雙層球體或三層球體，該雙層球體係具有內層之球體與包覆該內層之球體之外層，該三層球體係具有內層之球體與依序包覆該內層之球體之中間層及外層。或者，該導通球可具有至少一圓柱體與包覆該圓柱體之外層，且該導通球可由不同比例的錫鉛材料、錫銀材料或錫銀銅材料所構成。
上述導電柱可為圓柱體且其高度係大於直徑的二分之一，或者該導電柱可為橢圓柱體且其長軸長度係大於短軸長度的1.1倍，該導電柱亦可為多邊形柱體或球形柱體。
上述半導體封裝件及其製法可包括：形成封裝膠體於該第一半導體裝置之第一頂面與該第二半導體裝置之第二底面之間，以包覆該些導通球及該些導電柱。
上述半導體封裝件及其製法中，該第一半導體裝置之第一頂面係設置有半導體元件，以令該半導體元件嵌埋於該封裝膠體內。
上述半導體封裝件及其製法可包括：形成保護層於該半導體元件與該第二半導體裝置間之間隙，該保護層係作 為保護、散熱或電性接地之用。
上述半導體封裝件及其製法可包括：形成複數支撐元件於該第一半導體裝置與該第二半導體裝置之間，該些支撐元件係作為支撐、散熱或電性接地之用。
上述半導體封裝件及其製法可包括：形成至少一電子元件於該第一半導體裝置或該第二半導體裝置之內部或表面上。
由上可知，本發明之半導體封裝件及其製法中，主要係於第一半導體裝置之頂面形成複數導通球，並於第二半導體裝置之底面形成複數導電柱，且將該些導通球分別接合該些導電柱以電性連接該第一及第二半導體裝置，其中該導電柱之高度可小於300微米或大於直徑的二分之一，或者該導電柱之長軸長度可大於短軸長度的1.1倍。
因此，本發明於迴銲作業時僅需將該些導通球形成熔融狀態，但該些導電柱則可維持狀態不變而不會形成軟塌狀態，藉以將該些導通球分別接合該些導電柱，從而避免該些導通球互相橋接而短路，並易於控制該半導體封裝件之高度、或者該封裝膠體與該第二半導體裝置間之間隙，亦可用於具有更精細間距之導通球之半導體封裝件上，還可提高該半導體封裝件之結構信賴性。
1、2a、2b、2c、2d‧‧‧半導體封裝件
10‧‧‧第一基板
101、201‧‧‧第一銲墊
11‧‧‧第一銲球
12‧‧‧半導體晶片
121、28‧‧‧銲球
13、24‧‧‧封裝膠體
131、241‧‧‧開口
14‧‧‧第二基板
141、202‧‧‧第二銲墊
15‧‧‧第二銲球
16‧‧‧導電體
17、271‧‧‧間隙
20‧‧‧第一半導體裝置
20a‧‧‧第一頂面
20b‧‧‧第一底面
21、21a、21b、21c、21d‧‧‧導通球
211‧‧‧頂部
212‧‧‧側部
213‧‧‧內層之球體
214‧‧‧中間層
215‧‧‧外層
216‧‧‧圓柱體
22‧‧‧半導體元件
221‧‧‧導電元件
23‧‧‧底膠
25‧‧‧第二半導體裝置
25a‧‧‧第二頂面
25b‧‧‧第二底面
251‧‧‧第三銲墊
26、26a、26b、26c‧‧‧導電柱
27‧‧‧保護層
29‧‧‧支撐元件
30‧‧‧電子元件
d1、d2‧‧‧間距
H‧‧‧高度
L‧‧‧長軸長度
R‧‧‧直徑
S‧‧‧短軸長度
第1A圖與第1B圖係繪示習知技術之半導體封裝件及其製法之剖視示意圖；第2A圖至第2E圖係繪示本發明之半導體封裝件及其 製法之第一實施例之剖視示意圖；第3A圖至第3E圖係繪示本發明之半導體封裝件及其製法之第二實施例之剖視示意圖；第4A圖係繪示本發明之半導體封裝件之第三實施例之剖視示意圖；第4B圖係繪示本發明之半導體封裝件之第四實施例之剖視示意圖；第5A圖至第5D圖係分別繪示本發明各種態樣之導通球之示意圖；以及第6A圖至第6C圖係分別繪示本發明各種態樣之導電柱之示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。
同時，本說明書中所引用之如「上」、「一」、「第一」、「第二」、「頂面」、「底面」等用語，亦僅為便於敘述之明 瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A圖至第2E圖係繪示本發明之半導體封裝件2a及其製法之第一實施例之剖視示意圖。
如第2A圖所示，先提供具有相對之第一頂面20a與第一底面20b、複數第一銲墊201及複數第二銲墊202之第一半導體裝置20，該些第一銲墊201與該些第二銲墊202係分別形成於該第一頂面20a及該第一底面20b。
接著，形成複數具有間距d2之導通球21於該第一半導體裝置20之第一頂面20a之該些第一銲墊201上，並設置例如為半導體晶片之半導體元件22於該第一半導體裝置20之第一頂面20a，且透過複數例如為銲球之導電元件221電性連接該半導體元件22與該第一半導體裝置20，再形成底膠23於該半導體元件22與該第一半導體裝置20之第一頂面20a之間以包覆該些導電元件221。
該些導通球21之間距d2可小於習知技術第1A圖之第一銲球11之間距d1，但不以此為限。而且，該導通球21可為均勻球體，並依據不同法規或熔點的需求由不同比例的錫鉛(Sn-Pb)、錫銀(Sn-Ag)或錫銀銅(Sn-Ag-Cu)等材料所構成，例如63Sn-37Pb、90Sn-10Pb、98Sn-2Ag、95.5Sn-4.0Ag-0.5Cu之類。
同時，該導通球21可為單層球體、雙層球體或三層球體，該雙層球體係具有內層之球體與包覆該內層之球體之 外層，該三層球體係具有內層之球體與依序包覆該內層之球體之中間層及外層，該導通球21亦可具有至少一圓柱體與包覆該圓柱體之外層，請見第5A圖至第5D圖。
如第2B圖所示，形成封裝膠體24於該第一半導體裝置20之第一頂面20a，以包覆該些導通球21、半導體元件22、導電元件221及底膠23並嵌埋該半導體元件22於該封裝膠體24內，亦可外露出該半導體元件22之上表面。繼之，藉由雷射或其他方式於該封裝膠體24上燒穿或形成複數開口241以分別外露出該些導通球21之頂部211，但可不外露出該些導通球21之側部212以形成較小的開口241。
如第2C圖所示，提供具有相對之第二頂面25a與第二底面25b及複數第三銲墊251之第二半導體裝置25，並形成複數具有高度H之導電柱26於該第二半導體裝置25之第二底面25b之該些第三銲墊251上，且該導電柱26之高度H可小於300微米(μm)。該第一半導體裝置20或第二半導體裝置25可為基板、中介板、半導體晶片、半導體晶圓或半導體封裝結構等，該中介板可為含矽材質之中介板、無機中介板或有機中介板等。
該導電柱26a可為圓柱體且其高度H係大於直徑R的二分之一(H>1/2R)，或者該導電柱26b可為橢圓柱體且其長軸長度L係大於短軸長度S的1.1倍(L>1.1S)，該導電柱26亦可為多邊形柱體或球形柱體等。該導電柱26之材質可為銅、金或其合金等金屬材料或導電材料，且該導電 柱26之表面上可形成有抗氧化層(圖中未繪示)，例如電鍍之鉻層或有機可銲保護膜(Organic Solderablity Preservative,OSP)。
如第2D圖所示，將第2B圖之第一半導體裝置20上之該些導通球21分別對應第2C圖之第二半導體裝置25上之該些導電柱26，並藉由迴銲作業將該些導通球21形成熔融狀態，且將該些導通球21分別接合該些導電柱26以電性連接該第一半導體裝置20及該第二半導體裝置25。
另外，可形成保護層27於該半導體元件22之上表面與該第二半導體裝置25之第二底面25b間之間隙271。該保護層27可為非導電膜(non-conductive film,NCF)、黏合膜(adhesive film)、預浸體(prepreg)、聚醯亞胺(polymide,PI)、散熱膠(thermal adhesive)或接地層(ground)等，且該保護層27可用於保護該半導體元件22免於受損與增加第2D圖之整體結構之信賴性，亦可對該半導體元件22產生散熱效果，也可用於電性接地以防止電磁干擾(electromagnetic interference,EMI)或靜電放電(electrostatic discharge,ESD)。
如第2E圖所示，形成複數銲球28於該第一半導體裝置20之該些第二銲墊202上，從而形成一半導體封裝件2a。
本發明復提供一種如第2E圖所示之半導體封裝件2a。該半導體封裝件2a係包括一第一半導體裝置20、複數導通球21、一第二半導體裝置25、複數導電柱26以及一封裝膠體24。
該第一半導體裝置20係具有相對之第一頂面20a與第一底面20b、複數第一銲墊201及複數第二銲墊202，該些第一銲墊201與該些第二銲墊202係分別形成於該第一頂面20a及該第一底面20b。
該些導通球21係具有間距d2並形成於該第一半導體裝置20之第一頂面20a之該些第一銲墊201上，且該間距d2可小於習知技術第1A圖之第一銲球11之間距d1，但不以此為限。該導通球21可為均勻球體，並依據不同法規或熔點的需求由不同比例的錫鉛(Sn-Pb)、錫銀(Sn-Ag)或錫銀銅(Sn-Ag-Cu)等材料所構成，例如63Sn-37Pb、90Sn-10Pb、98Sn-2Ag、95.5Sn-4.0Ag-0.5Cu之類。
同時，該導通球21可為單層球體、雙層球體或三層球體，該雙層球體係具有內層之球體與包覆該內層之球體之外層，該三層球體係具有內層之球體與依序包覆該內層之球體之中間層及外層，該導通球21亦可具有至少一圓柱體與包覆該圓柱體之外層，請見第5A圖至第5D圖。
該第二半導體裝置25係具有相對之第二頂面25a與第二底面25b及複數第三銲墊251。該第一半導體裝置20或該第二半導體裝置25可為基板、中介板、半導體晶片、半導體晶圓或半導體封裝結構等，該中介板可為含矽材質之中介板、無機中介板或有機中介板等。
該些導電柱26均可具有小於300微米之高度H，並分別形成於該第二半導體裝置25之第二底面25b之該些第三銲墊251上，且該些導電柱26可分別接合該些導通球21 以電性連接該第一半導體裝置20及該第二半導體裝置25。
該導電柱26a可為圓柱體且其高度H係大於直徑R的二分之一，或者該導電柱26b可為橢圓柱體且其長軸長度L係大於短軸長度S的1.1倍，該導電柱26亦可為多邊形柱體或球形柱體等。該導電柱26之材質可為銅、金或其合金等金屬材料或導電材料，且該導電柱26之表面上可形成有抗氧化層(圖中未繪示)，例如電鍍之鉻層或有機可銲保護膜(OSP)。
該封裝膠體24可形成於該第一半導體裝置20之第一頂面20a以包覆該些導通球21，且該封裝膠體24可具有複數開口241以分別外露出該些導通球21之頂部211。
該半導體封裝件2a可包括例如為半導體晶片之半導體元件22，係設置於該第一半導體裝置20之第一頂面20a並嵌埋於該封裝膠體24內，而該半導體元件22之上表面可外露於該封裝膠體24之上表面，且該半導體元件22可透過複數導電元件221電性連接該第一半導體裝置20。
該半導體封裝件2a可包括底膠23，係形成於該半導體元件221與該第一半導體裝置20之間以包覆該些導電元件221。
該半導體封裝件2a可包括保護層27，係形成於該半導體元件22之上表面與該第二半導體裝置25之第二底面25b間之間隙271。該保護層27可為非導電膜(NCF)、黏合膜、預浸體、聚醯亞胺(PI)、散熱膠或接地層等，且該保護層27可用於保護該半導體元件22免於受損與增加該半 導體封裝件2a之結構信賴性，亦可對該半導體元件22產生散熱效果，也可用於電性接地以防止電磁干擾(EMI)或靜電放電(ESD)。
第3A圖至第3E圖係繪示本發明之半導體封裝件2b及其製法之第二實施例之剖視示意圖，且第3A圖至第3E圖與上述第2A圖至第2E圖之相同部分將不再重覆敘述。
如第3A圖所示，先提供具有相對之第一頂面20a與第一底面20b、複數第一銲墊201及複數第二銲墊202之第一半導體裝置20，該些第一銲墊201與該些第二銲墊202係分別形成於該第一頂面20a及該第一底面20b。
接著，形成複數具有間距d2之導通球21於該第一半導體裝置20之第一頂面20a之該些第一銲墊201上，並設置例如為半導體晶片之半導體元件22於該第一半導體裝置20之第一頂面20a，且透過複數例如為銲球或銲線之導電元件221電性連接該半導體元件22與該第一半導體裝置20。
如第3B圖所示，提供具有相對之第二頂面25a與第二底面25b及複數第三銲墊251之第二半導體裝置25，並形成複數具有高度H之導電柱26於該第二半導體裝置25之第二底面25b之該些第三銲墊251上，且該導電柱26之高度H可小於300微米。
如第3C圖所示，將第3A圖之第一半導體裝置20上之該些導通球21分別對應第3B圖之第二半導體裝置25上之該些導電柱26，並藉由迴銲作業將該些導通球21形 成熔融狀態，且將該些導通球21分別接合該些導電柱26以電性連接該第一半導體裝置20及該第二半導體裝置25
如第3D圖所示，形成具有較細顆粒之封裝膠體24於該第一半導體裝置20之第一頂面20a與該第二半導體裝置25之第二底面25b之間，以包覆該些導通球21、導電柱26、半導體元件22及導電元件221，並藉由該封裝膠體24取代第2A圖所示之底膠23。
如第3E圖所示，形成複數銲球28於該第一半導體裝置20之該些第二銲墊202上，從而形成一半導體封裝件2b。
本發明復提供一種如第3E圖所示之半導體封裝件2b，第3E圖之半導體封裝件2b與上述第2E圖之半導體封裝件2a大致相同，其主要差異如下：在第3E圖中，該封裝膠體24係形成於該第一半導體裝置20之第一頂面20a與該第二半導體裝置25之第二底面25b之間，以包覆該些導通球21、導電柱26、半導體元件22及導電元件221。
因此，第3E圖之第二半導體裝置25之第二底面25b與封裝膠體24之間並未形成有第2E圖之間隙271，而第3E圖之第二半導體裝置25之第二底面25b與半導體元件22之間亦可不必形成有第2E圖之保護層27，且第3E圖可用較細顆粒之封裝膠體24直接包覆該些導電元件221以取代第2E圖之底膠23。
第4A圖係繪示本發明之半導體封裝件2c之第三實施 例之剖視示意圖，第4A圖之半導體封裝件2c與上述第3E圖之半導體封裝件2b大致相同，其主要差異如下：在第4A圖中，該半導體封裝件2c可包括複數支撐元件29，係形成於該第一半導體裝置20與該第二半導體裝置25之間。換言之，該半導體封裝件2c之製法可包括形成複數支撐元件29於該第一半導體裝置20與該第二半導體裝置25之間。
該些支撐元件29可用於支撐第二半導體裝置25以保護該半導體元件22免於受損與增加半導體封裝件2c之結構信賴性，亦可對該半導體元件22產生散熱效果，也可用於電性接地以防止電磁干擾(EMI)或靜電放電(ESD)。
此外，第4A圖之支撐元件29亦可形成於上述第2E圖之第一半導體裝置20與第二半導體裝置25之間。
第4B圖係繪示本發明之半導體封裝件2d之第四實施例之剖視示意圖，第4B圖之半導體封裝件2d與上述第4A圖之半導體封裝件2c大致相同，其主要差異如下：在第4B圖中，該半導體封裝件2d可包括至少一電子元件30，係形成於該第一半導體裝置20或該第二半導體裝置25之內部或表面上，該表面可為該第一頂面20a、第一底面20b、第二頂面25a或第二底面25b。換言之，該半導體封裝件2d之製法可包括形成至少一電子元件30於該第一半導體裝置20或該第二半導體裝置25之內部上。
此外，第4B圖之電子元件30亦可形成於上述第2E圖與第3E圖之第一半導體裝置20或第二半導體裝置25 之內部或表面上。
第5A圖至第5D圖係分別繪示本發明各種態樣之導通球21a至導通球21d之示意圖。
如第5A圖所示，該導通球21a可為雙層球體，並具有內層之球體213與包覆該內層之球體213之外層215。
如第5B圖所示，該導通球21b可為三層球體，並具有內層之球體213與依序包覆該內層之球體213之中間層214及外層215。該內層之球體213、中間層214及外層215之材質可分別為塑膠、金屬(除錫以外)及錫等，該內層之球體213為塑膠材質可以降低該導通球21b之成本。
如第5C圖所示，該導通球21c可具有一圓柱體216與包覆該圓柱體216之外層215。
如第5D圖所示，該導通球21d可具有二圓柱體216與包覆該二圓柱體216之外層215。
上述第5A圖至第5D圖之內層之球體213或圓柱體216可使該導通球21a至該導通球21d具有強化結構或避免該外層215發生崩塌情形，而該外層215則可形成熔融狀態以便接合該導電柱26。
第6A圖至第6C圖係分別繪示本發明各種態樣之導電柱26a至導電柱26c之示意圖。
如第6A圖之立體圖與下列表格所示，由於該導電柱26a需具有一定的高度H(或長度)才能達到精細間距(fine pitch)，在該導電柱26a之寬度(或直徑)、形狀及材質等條件不變下，當該導電柱26a之高度H分別為100微米(μm) 與500微米時，其相應之力矩M分別為100F及500F，其中力矩M之單位為牛頓‧米(Nm)，F為作用力且其單位為牛頓(N)，表示該導電柱26a於500微米時之力矩M等於100微米時之力矩M之5倍(500F÷100F=5)，此將導致該導電柱26a於500微米時容易發生斷裂之問題。
因此，經多次的實驗結果，該導電柱26a之較佳高度(或長度)為小於300微米，可使該導電柱26a具有較精細間距並避免發生斷裂情形。
在第6A圖中，該導電柱26a可為圓柱體且其高度H可大於直徑R的二分之一。但在其他實施例中，該導電柱26a亦可為橢圓柱體、多邊形柱體或球形柱體等。
如第6B圖之上視圖所示，該導電柱26b可為橢圓柱體且其長軸長度L可大於短軸長度S的1.1倍。
如第6C圖之剖視圖所示，該導電柱26c可為至少二球體(如二或三球體)所構成或堆疊而成之球形柱體。
由上可知，本發明之半導體封裝件及其製法中，主要係於第一半導體裝置之頂面形成複數導通球，並於第二半導體裝置之底面形成複數導電柱，且將該些導通球分別接合該些導電柱以電性連接該第一及第二半導體裝置，其中該導電柱之高度可小於300微米或大於直徑的二分之一，或者該導電柱之長軸長度可大於短軸長度的1.1倍。
因此，本發明於迴銲作業時僅需將該些導通球形成熔 融狀態，但該些導電柱則可維持狀態不變而不會形成軟塌狀態，藉以將該些導通球分別接合該些導電柱，從而避免該些導通球互相橋接而短路，並易於控制該半導體封裝件之高度、或者該封裝膠體與該第二半導體裝置間之間隙，亦可用於具有更精細間距之導通球之半導體封裝件上，還可提高該半導體封裝件之結構信賴性。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如所提出之申請專利範圍所列。
2a‧‧‧半導體封裝件
20‧‧‧第一半導體裝置
20a‧‧‧第一頂面
20b‧‧‧第一底面
201‧‧‧第一銲墊
202‧‧‧第二銲墊
21‧‧‧導通球
22‧‧‧半導體元件
221‧‧‧導電元件
23‧‧‧底膠
24‧‧‧封裝膠體
241‧‧‧開口
25‧‧‧第二半導體裝置
25a‧‧‧第二頂面
25b‧‧‧第二底面
251‧‧‧第三銲墊
26‧‧‧導電柱
27‧‧‧保護層
271‧‧‧間隙
28‧‧‧銲球
d2‧‧‧間距
H‧‧‧高度

Claims (29)

  1. 一種半導體封裝件，其包括：第一半導體裝置，係具有相對之第一頂面與第一底面；複數導通球，係形成於該第一半導體裝置之第一頂面；第二半導體裝置，係具有相對之第二頂面與第二底面，且該第二底面係面向該第一半導體裝置之第一頂面；以及複數導電柱，係形成於該第二半導體裝置之第二底面，並分別接合該些導通球以電性連接該第一半導體裝置及該第二半導體裝置，其中，該導電柱之高度係小於300微米。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中，該第一半導體裝置或該第二半導體裝置係為基板、中介板、半導體晶片、半導體晶圓或半導體封裝結構。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中，該導通球係為單層球體、雙層球體或三層球體，該雙層球體係具有內層之球體與包覆該內層之球體之外層，該三層球體係具有內層之球體與依序包覆該內層之球體之中間層及外層。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中，該導通球係具有至少一圓柱體與包覆該圓柱體之外層。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中，該導通球係由不同比例的錫鉛材料、錫銀材料或錫銀銅材料所構成。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中，該導電柱係為圓柱體、橢圓柱體、多邊形柱體或球形柱體。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中，該導電柱係為圓柱體且其高度係大於直徑的二分之一。
  8. 如申請專利範圍第1項所述之半導體封裝件，其中，該導電柱係為橢圓柱體且其長軸長度係大於短軸長度的1.1倍。
  9. 如申請專利範圍第1項所述之半導體封裝件，復包括封裝膠體，係形成於該第一半導體裝置之第一頂面與該第二半導體裝置之第二底面之間，以包覆該些導通球及該些導電柱。
  10. 如申請專利範圍第1項所述之半導體封裝件，復包括半導體元件，係設置於該第一半導體裝置之第一頂面並嵌埋於封裝膠體內。
  11. 如申請專利範圍第10項所述之半導體封裝件，復包括保護層，係形成於該半導體元件與該第二半導體裝置間之間隙，並作為保護、散熱或電性接地之用。
  12. 如申請專利範圍第1項所述之半導體封裝件，復包括複數支撐元件，係形成於該第一半導體裝置與該第二 半導體裝置之間，並作為支撐、散熱或電性接地之用。
  13. 如申請專利範圍第1項所述之半導體封裝件，復包括至少一電子元件，係形成於該第一半導體裝置或該第二半導體裝置之內部或表面上。
  14. 一種半導體封裝件，其包括：第一半導體裝置，係具有第一頂面與第一底面；複數導通球，係形成於該第一半導體裝置之第一頂面；第二半導體裝置，係具有相對之第二頂面與第二底面，且該第二底面係面向該第一半導體裝置之第一頂面；以及複數單層之導電柱，係形成於該第二半導體裝置之第二底面，且該些單層之導電柱分別接合該些導通球以電性連接該第一半導體裝置及該第二半導體裝置，其中，該單層之導電柱係為圓柱體且其高度係大於直徑的二分之一。
  15. 一種半導體封裝件，其包括：第一半導體裝置，係具有第一頂面與第一底面；複數導通球，係形成於該第一半導體裝置之第一頂面；第二半導體裝置，係具有相對之第二頂面與第二底面，且該第二底面係面向該第一半導體裝置之第一頂面；以及複數導電柱，係形成於該第二半導體裝置之第二 底面，並分別接合該些導通球以電性連接該第一半導體裝置及該第二半導體裝置，其中，該導電柱係為橢圓柱體且其長軸長度係大於短軸長度的1.1倍。
  16. 如申請專利範圍第14項或第15項所述之半導體封裝件，其中，該導通球係為單層球體、雙層球體或三層球體，該雙層球體係具有內層之球體與包覆該內層之球體之外層，該三層球體係具有內層之球體與依序包覆該內層之球體之中間層及外層。
  17. 如申請專利範圍第14項或第15項所述之半導體封裝件，其中，該導通球係具有至少一圓柱體與包覆該圓柱體之外層。
  18. 如申請專利範圍第14項或第15項所述之半導體封裝件，復包括半導體元件與保護層，該半導體元件係設置於該第一半導體裝置之第一頂面並嵌埋於封裝膠體內，該保護層係形成於該半導體元件與該第二半導體裝置間之間隙並作為保護、散熱或電性接地之用。
  19. 如申請專利範圍第14項或第15項所述之半導體封裝件，復包括複數支撐元件，係形成於該第一半導體裝置與該第二半導體裝置之間，並作為支撐、散熱或電性接地之用。
  20. 一種半導體封裝件之製法，其包括：提供具有相對之第一頂面與第一底面之第一半導體裝置、以及具有相對之第二頂面與第二底面之第二半導體裝置，該第一半導體裝置之第一頂面係形成有 複數導通球，且該第二半導體裝置之第二底面係形成有複數導電柱，其中，該導電柱之高度係小於300微米；以及將該第一半導體裝置上之該些導通球分別對應該第二半導體裝置上之該些導電柱，以將該些導通球分別接合該些導電柱而電性連接該第一半導體裝置及該第二半導體裝置。
  21. 如申請專利範圍第20項所述之半導體封裝件之製法，其中，該導通球係為單層球體、雙層球體或三層球體，該雙層球體係具有內層之球體與包覆該內層之球體之外層，該三層球體係具有內層之球體與依序包覆該內層之球體之中間層及外層。
  22. 如申請專利範圍第20項所述之半導體封裝件之製法，其中，該導通球係具有至少一圓柱體與包覆該圓柱體之外層。
  23. 如申請專利範圍第20項所述之半導體封裝件之製法，其中，該導電柱係為圓柱體，且該圓柱體之高度係大於直徑的二分之一。
  24. 如申請專利範圍第20項所述之半導體封裝件之製法，其中，該導電柱係為橢圓柱體，且該橢圓柱體之長軸長度係大於短軸長度的1.1倍。
  25. 如申請專利範圍第20項所述之半導體封裝件之製法，復包括形成封裝膠體於該第一半導體裝置之第一頂面與該第二半導體裝置之第二底面之間，以包覆該些導 通球及該些導電柱。
  26. 如申請專利範圍第20項所述之半導體封裝件之製法，其中，該第一半導體裝置之第一頂面設置有半導體元件，以令該半導體元件嵌埋於封裝膠體內。
  27. 如申請專利範圍第26項所述之半導體封裝件之製法，復包括形成保護層於該半導體元件與該第二半導體裝置間之間隙，該保護層係作為保護、散熱或電性接地之用。
  28. 如申請專利範圍第20項所述之半導體封裝件之製法，復包括形成複數支撐元件於該第一半導體裝置與該第二半導體裝置之間，該些支撐元件係作為支撐、散熱或電性接地之用。
  29. 如申請專利範圍第20項所述之半導體封裝件之製法，復包括形成至少一電子元件於該第一半導體裝置或該第二半導體裝置之內部或表面上。
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