JP2008226946A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP2008226946A
JP2008226946A JP2007059513A JP2007059513A JP2008226946A JP 2008226946 A JP2008226946 A JP 2008226946A JP 2007059513 A JP2007059513 A JP 2007059513A JP 2007059513 A JP2007059513 A JP 2007059513A JP 2008226946 A JP2008226946 A JP 2008226946A
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Prior art keywords
conductive adhesive
lsi
semiconductor device
substrate
electrode pad
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JP2007059513A
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English (en)
Inventor
Eiji Hori
英治 堀
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NEC Corp
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NEC Corp
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Priority to JP2007059513A priority Critical patent/JP2008226946A/ja
Priority to US12/032,136 priority patent/US20080224309A1/en
Publication of JP2008226946A publication Critical patent/JP2008226946A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
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Abstract

【課題】ボンディング工程時に搭載部品にかかる熱負荷を軽減する。接続部へのストレスの軽減。実装コストの削減。ＬＳＩチップのスタンドオフを一定に確保する。
【解決手段】ＬＳＩチップ１は、基板２上に搭載されている。基板２上には配線（図示なし）と該配線に連なるパッド３が形成されている外、配線とは接続されていないダミーパッド３ａが、ＬＳＩチップ１の四隅に対応する位置に形成されている。ＬＳＩチップ１の電極パッド（図示なし）と基板上のパッド３とは導電性接着剤４を介して接続されている。ダミーパッド３ａ上には、ボールスペーサ５と導電性接着剤４とが形成されており、ボールスペーサ５によりＬＳＩチップ１と基板２との距離が一定に保持されている。
【選択図】図１

Description

本発明は、半導体装置およびその製造方法に関し、より詳しくは、ＬＳＩの電極パッドと実装基板上の電極パッドとが導電性接着剤にて接続されている半導体装置とその製造方法に関するものである。
ＬＳＩの実装基板への実装には、フリップチップボンディング法が広く用いられている。これは、主にはんだボールやはんだバンプを接続手段として用いてボンディングを行なうものであるが、はんだ材料としては、従前にはＳｎ−Ｐｂ共晶などの鉛はんだが用いられてきたが、環境規制により鉛フリーはんだを用いた実装が行なわれるようになってきている（例えば、特許文献１参照）。現在主流となっているＳｎ−Ａｇ−Ｃｕ系など鉛フリーはんだは融点が高く、高温でのはんだ接続プロセスを必要とし、基板や搭載部品への熱負荷が大きい。また、鉛フリーはんだは弾性率が高く、接続部の周囲にストレスが加わりやすく、ＬＳＩがlow-k膜などのストレスに弱い構造部を有する場合には剥離などの事故が発生しやすく、接続信頼性に影響を与える場合がある。一方で、はんだを用いないボンディング技術の一つに導電性接着剤を用いるものがある（例えば、特許文献２参照）。導電性接着剤は、はんだに比べ低温での接続が可能であるため、搭載部品への熱負荷の軽減が可能となるのに加え、ストレスが軽減されてＬＳＩが損傷を受ける可能性が低くなる。
この種従来の導電性接着剤を用いた接続技術は、スタッドバンプ法と呼ばれるものである。図６は、この方法により実装されたＬＳＩチップの接続部の状態を示す断面図である。ボンディングに先立って、ＬＳＩチップ１のＡｌ電極１ａ上には、金細線などを用いてスタッド１ｂが形成される。基板２上に形成されたパッド３上に導電性接着剤４が塗布された後、ＬＳＩチップ１が基板２上に搭載される。そして、熱処理が行なわれ、導電性接着剤が硬化される。
特開２００６−３１３８２６号公報 特開２００５−３１１２０９号公報
従来の鉛フリーはんだを用いたフリップチップボンディングでは、搭載部品への熱負荷が懸念されると共に接続部へのストレスが高くなるという問題がある。一方、スタッドバンプ法では、ＬＳＩチップにＡｕスタッドを形成しなければならなくなるため、実装コストが高くなる。本願発明は、これらの問題点に鑑みてなされたものであって、本発明者等は、低温でかつ低コストのボンディングを目指して開発を進め、導電性接着剤のみによる接続に想到したが、実際に試作してみると、ＬＳＩチップに傾きやパッド間にショートが発生する可能性が高いことが分かった。高温導電性接着剤のみを用いてＬＳＩを基板に接続する場合、導電性接着剤ははんだのように球状化せずそしてはんだの場合のようにセルフアライメント効果を期待することができず、また、スタッドバンプのようなＬＳＩチップと基板との間隔（接続部の高さ：スタンドオフ）を規制するものの存在がないため、ＬＳＩの搭載時あるいは導電性接着剤の硬化の際に、ＬＳＩチップは自重により沈降しがちである。このため、ＬＳＩのスタンドオフが設定より小さくなり、接着剤が周囲にはみ出し、隣接パッド間でショートが発生する可能性が高くなるのである。
本発明の課題は、上述した問題点を解決することであって、その目的は、第１に、ＬＳＩに熱負荷やストレスを与えることのない実装方法と実装構造を提供できるようにすることであり、第２に、Ａｕスタッド形成工程などを必要としないローコストな実装技術を提供できるようにすることであり、第３に、ＬＳＩのスタンドオフが適切な値に維持できるようにして、パッド間でのショートを防止できるようにすることである。
上記の目的を達成するため、本発明によれば、ＬＳＩの電極パッドと実装基板上の電極パッドとが導電性接着剤にて接続されている半導体装置において、前記ＬＳＩと前記実装基板との間には複数のスペーサが介在していることを特徴とする半導体装置、が提供される。
また、上記の目的を達成するため、本発明によれば、ＬＳＩの電極パッドと実装基板上の電極パッドとが導電性接着剤にて接続されている半導体装置の製造方法において、実装基板の電極パッド上とスペーサ配置位置とに導電性接着剤を塗布する工程と、前記スペーサ配置位置にスペーサを配置する工程と、実装基板上にＬＳＩを搭載する工程と、前記導電性接着剤を硬化させる工程と、を有することを特徴とする半導体装置の製造方法、が提供される。
また、上記の目的を達成するため、本発明によれば、ＬＳＩの電極パッドと実装基板上の電極パッドとが導電性接着剤にて接続されている半導体装置の製造方法において、実装基板の電極パッド上に導電性接着剤を塗布する工程と、前記実装基板上にスペーサを配置する工程と、実装基板上にＬＳＩを搭載する工程と、前記導電性接着剤を硬化させる工程と、を有することを特徴とする半導体装置の製造方法、が提供される。
また、上記の目的を達成するため、本発明によれば、ＬＳＩの電極パッドと実装基板上の電極パッドとが導電性接着剤にて接続されている半導体装置の製造方法において、実装基板の電極パッド上に導電性接着剤を塗布する工程と、ＬＳＩのコーナ部にスペーサを配置する工程と、実装基板上にＬＳＩを搭載する工程と、前記導電性接着剤を硬化させる工程と、を有することを特徴とする半導体装置の製造方法、が提供される。
なお、上記の解決手段において、ＬＳＩは、ＬＳＩチップのみならずＣＳＰ型ＬＳＩのようにパッケージングされたデバイスを含むものである。
導電性接着剤は、概ね２００℃以下の硬化温度で硬化が可能であり、硬化後の導電性接着剤の弾性率は、鉛フリーはんだのそれよりはるかに小さいため、本発明によれば、実装工程時にＬＳＩに熱負荷を与えないようにすることができると共にストレスを与えないようにしてＬＳＩに剥離などの損傷が発生しないようにすることができる。また、ＬＳＩチップにＡｕスタッド形成工程などの高コストの工程の必要がなく、導電性接着剤のみの使用でボンディングが可能となるため、安価に半導体装置を製造することが可能になる。そして、ＬＳＩ−基板間にスペーサが挿入されることにより、ＬＳＩのスタンドオフを十分に確保することができ、隣接パッド間のショートを効果的に防止することが可能になる。
以下、本発明の好適な実施の形態を、添付した図面を参照しつつ詳細に説明する。
〔第１の実施の形態〕
図１は、本発明の半導体装置の第１の実施の形態を示す図であって、図１（ａ）は断面図、図１（ｂ）は、（ａ）図のＡ−Ａ線より基板側を見た断面図である。ＬＳＩチップ１は、基板２上に搭載されている。基板２上には配線（図示なし）と該配線に連なるパッド３が形成されている外、配線とは接続されていないダミーパッド３ａが、ＬＳＩチップ１の四隅に対応する位置に形成されている。ＬＳＩチップ１の電極パッド（図示なし）と基板上のパッド３とは導電性接着剤４を介して接続されている。ダミーパッド３ａ上には、ボールスペーサ５と導電性接着剤４とが形成されており、ボールスペーサ５によりＬＳＩチップ１と基板２との距離が一定に保持されている。ダミーパッド３ａ上で、導電性接着剤４はボールスペーサ５を取り囲むように形成されている。
基板２上には他のＬＳＩなどの半導体チップが搭載されていてもよく、また抵抗、コンデンサなどの受動部品が搭載されていてもよい。
基板２は、リジッドあるいはフレキシブルな樹脂基板であってもまたセラミック基板であってもよい。そして、配線は基板両面に形成されていてもよく、また基板に多層配線が形成されていてもよい。また、ＢＧＡやＣＳＰのキャリア基板であってもよい。
スペーサボール５は、ＬＳＩの高さ（スタンドオフ）を所望の値に維持できるようにするためのものであるあるので、一定の径の球体であれば樹脂ボールないし金属ボールのいずれもが使用可能である。
導電性接着剤は、樹脂材料に金属粉末などの導電性フィラーを混入したものであって、市販の適宜のものを用い得る。すなわち、その樹脂材料としては、エポキシ樹脂、ポリエステル樹脂、アクリル樹脂、メラミン樹脂、ポリイミド樹脂、フェノール樹脂、シリコーン樹脂等であってよいが、それらの２種以上を組み合わせたものであってもよい。樹脂材料に添加される導電性粒子は、銀、銅、銅合金、金、パラジウム、銀パラジウム合金、ニッケル等の金属粒子やカーボンなどである。ナノサイズの金属粉末の混入されたナノペーストの使用も可能である。その場合、低温でのキュアにより低抵抗の接続が可能になる。
次に、図２を参照して本発明の第１の実施の形態の半導体装置の製造方法について説明する。図２は、その製造方法を示す工程順の断面図である。まず、図２（ａ）に示すように、ＬＳＩチップの電極端子の形成位置に相当する位置にパッド３が、またＬＳＩチップの四隅に相当する位置にダミーパッド３ａが形成された基板１を用意する。次に、図２（ｂ）に示すように、パッド３およびダミーパッド３ａ上にスクリーン印刷法などにより導電性接着剤４を塗布する。導電性接着剤の塗布は、マイクロディスペンサやジェット・プリンタを用いて行なってもよい。次に、図２（ｃ）に示すように、ダミーパッド３ａ上の導電性接着剤４上にボールスペーサ５を配置する。続いて、図２（ｄ）に示すように、基板２のパッド３とＬＳＩチップ１の電極パッド（図示なし）とを位置合わせし、ＬＳＩチップ１を基板２上に搭載する。そして、熱処理を行なって導電性接着剤を硬化させる。導電性接着剤が熱可塑性樹脂を用いるものである場合には、熱処理を行なって固化する。
〔第２の実施の形態〕
図３は、本発明の第２の実施の形態の断面図である。図３において、図１に示す第１の実施の形態の部分と同等の部分には同一の参照符号を付し、重複する説明は省略する。本実施の形態においては、第１の実施の形態で用いられていたダミーパッドが削除されており、またＬＳＩチップの四隅に対応する個所に設置されるボールスペーサ５は、接着剤６によって接着されている。第１の実施の形態では、ボールスペーサ５の配置位置には予め導電性接着剤が塗布されていたが、この方法では当該個所に塗布される導電性接着剤の量が過剰になり易い。そのため、ダミーパッド上の導電性接着剤を介してパッド間にショートが発生する可能性が高くなる。本実施の形態においては、導電性接着剤４の塗布工程とは別に接着剤６の塗布工程を設け、ボールスペーサ５設置位置には適宜量の接着剤が塗布される。
〔第３の実施の形態〕
図４は、本発明の第３の実施の形態の半導体装置の製造方法を示す工程順の断面図である。まず、図４（ａ）に示されるように、第１の実施の形態の場合と同様に準備された基板２上のパッド３上にスクリーン印刷法などにより導電性接着剤４を塗布する。このとき、ダミーパッド３ａ上には導電性接着剤は塗布しない。次に、図４（ｂ）に示されるように、ダミーパッド３ａ上に、接着剤（図示なし）が表面に一様に塗布されたボールスペーサ５を配置する。続いて、図４（ｃ）に示すように、パッド３とＬＳＩチップ１の電極パッド（図示なし）とを位置合わせし、ＬＳＩチップ１を基板２上に搭載する。そして、熱処理を行なって導電性接着剤を硬化させる。
〔第４の実施の形態〕
図５は、本発明の第４の実施の形態の半導体装置の製造方法を示す工程順の断面図である。まず、図５（ａ）に示されるように、第２の実施の形態の場合と同様に準備された基板２上のパッド３上に導電性接着剤４をスクリーン印刷法などにより塗布する。そして、図５（ｂ）に示されるように、ＬＳＩチップ１の電極パッド形成面の四隅に、予め接着剤（図示なし）が表面に塗布された、立方体形状のブロックスペーサ７を配置する。続いて、図５（ｃ）に示すように、基板２のパッド３とＬＳＩチップ１の電極パッド（図示なし）とを位置合わせし、ＬＳＩチップ１を基板２上に搭載する。そして、熱処理を行なって導電性接着剤を硬化させる。
図５（ａ）の工程と図５（ｂ）の工程とはいずれが先であっても、あるいは同時併行であってもよい。また、図５（ｂ）に示す工程において、接着剤の硬化ないしポリベークを行なってもよい。
以上本発明の好ましい実施の形態について説明したが、本発明はこれら実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において適宜の変更が可能なものである。例えば、実施の形態では、搭載部品をＬＳＩチップとしたが、ＣＳＰなどのパッケージングされたものであってもよい。また、スペーサとしては、球状のものと立方体状のものについて説明したが、この他にも円柱状や正四面体など適宜の形状のものを用い得る。また、スペーサの設置位置は、ＬＳＩの四隅に限定されず、ＬＳＩの電極パッドの形成されていない適宜の領域を選択して設置するようにしてもよい。
本発明の第１の実施の形態の半導体装置を示す縦断面図と横断面図。 本発明の第１の実施の形態の半導体装置の製造方法を示す工程順の断面図。 本発明の第２の実施の形態の半導体装置を示す断面図。 本発明の第３の実施の形態の半導体装置の製造方法を示す工程順の断面図。 本発明の第４の実施の形態の半導体装置の製造方法を示す工程順の断面図。 従来例の断面図。
符号の説明
１ ＬＳＩチップ
１ａ Ａｌ電極
１ｂ スタッド
２ 基板
３ パッド
３ａ ダミーパッド
４ 導電性接着剤
５ ボールスペーサ
６ 接着剤
７ ブロックスペーサ

Claims (9)

  1. ＬＳＩの電極パッドと実装基板上の電極パッドとが導電性接着剤にて接続されている半導体装置であって、前記ＬＳＩと前記実装基板との間には複数のスペーサが介在していることを特徴とする半導体装置。
  2. 前記スペーサが前記ＬＳＩのコーナ部に配置されていることを特徴とする請求項１に記載の半導体装置。
  3. 前記ＬＳＩがベアチップまたはパッケージングされたものであることを特徴とする請求項１または２に記載の半導体装置。
  4. 前記スペーサが前記実装基板上のダミーパッド上に配置されていることを特徴とする請求項１から３のいずれかに記載の半導体装置。
  5. 前記スペーサが導電性接着剤に埋め込まれて配置されていることを特徴とする請求項１から４のいずれかに記載の半導体装置。
  6. ＬＳＩの電極パッドと実装基板上の電極パッドとが導電性接着剤にて接続されている半導体装置の製造方法において、実装基板の電極パッド上とスペーサ配置位置とに導電性接着剤を塗布する工程と、前記スペーサ配置位置にスペーサを配置する工程と、実装基板上にＬＳＩを搭載する工程と、前記導電性接着剤を硬化させる工程と、を有することを特徴とする半導体装置の製造方法。
  7. ＬＳＩの電極パッドと実装基板上の電極パッドとが導電性接着剤にて接続されている半導体装置の製造方法において、実装基板の電極パッド上に導電性接着剤を塗布する工程と、前記実装基板上にスペーサを配置する工程と、実装基板上にＬＳＩを搭載する工程と、前記導電性接着剤を硬化させる工程と、を有することを特徴とする半導体装置の製造方法。
  8. ＬＳＩの電極パッドと実装基板上の電極パッドとが導電性接着剤にて接続されている半導体装置の製造方法において、実装基板の電極パッド上に導電性接着剤を塗布する工程と、ＬＳＩのコーナ部にスペーサを配置する工程と、実装基板上にＬＳＩを搭載する工程と、前記導電性接着剤を硬化させる工程と、を有することを特徴とする半導体装置の製造方法。
  9. 配置されるスペーサには予め接着剤が塗布されていることを特徴とする請求項７または８に記載の半導体装置の製造方法。
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