JP2009010437A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2009010437A JP2009010437A JP2008269173A JP2008269173A JP2009010437A JP 2009010437 A JP2009010437 A JP 2009010437A JP 2008269173 A JP2008269173 A JP 2008269173A JP 2008269173 A JP2008269173 A JP 2008269173A JP 2009010437 A JP2009010437 A JP 2009010437A
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- semiconductor device
- insulating film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】個々のランド2bを覆う個々の絶縁膜3は、互いに分離されており、かつ、ランド2bを覆う絶縁膜3の側面3bから、ランド2bに接続される導電性配線2の他にダミー配線10を突出させる。これによって、絶縁膜3内部で剛性の大きな配線材料が占める割合を大きくすることができ、絶縁膜3自体の熱変形の拘束を、ダミー配線10により強化することができるようになる。また、絶縁膜側面3bの剥離を導電性配線2とダミー配線10とによって抑制することができ、側面3bの剥離発生による絶縁膜3の熱変形量の増加を抑制することができる。
【選択図】図1
Description
2 導電性配線
2a ボンディングパッド
2b ランド
3 絶縁膜
3a ボンディングパッド部の絶縁膜開口部
3b 絶縁膜の側面
4 絶縁性テープ
4a 絶縁性テープの半導体素子固着面
4b 絶縁性テープの実装面
5 接着部材
6 金属細線
7 封止樹脂
8 外部端子
9 絶縁性テープの開口部
10 ダミー配線
11 突起
12 絶縁膜の開口部
13 スリット
14 変形拘束部材
Claims (9)
- 基材、前記基材に形成されたボンディングパッド、前記ボンディングパッドと繋がる導電性配線、前記導電性配線と繋がるランド、及び前記ランドと繋がるダミー配線を有する基板と、
前記基板に接着部材を介して固着された半導体素子と、
前記半導体素子を封止する封止樹脂と、
前記基板の前記ランドに形成されたはんだ材と、
を含むことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記ダミー配線は、前記導電性配線と対向する方向に延在していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記ランドには、複数の前記ダミー配線が繋がっていることを特徴とする半導体装置。
- 請求項2又は3記載の半導体装置において、前記基材は、さらに前記絶縁膜を有し、前記ランドは前記絶縁膜の外形線の内側に位置しており、前記導電性配線及びダミー配線のそれぞれは、前記絶縁膜の前記外形線の内外に亘って延在していることを特徴とする半導体装置。
- 請求項4記載の半導体装置において、前記絶縁膜の前記外形線の内側に位置する前記導電性配線の幅は、前記絶縁膜の前記外形線の外側に位置する前記導電性配線の幅よりも太く形成されていることを特徴とする半導体装置。
- 請求項4記載の半導体装置において、前記絶縁膜の前記外形線の内側に位置する前記ダミー配線の幅は、前記絶縁膜の前記外形線の外側に位置する前記ダミー配線の幅よりも太く形成されていることを特徴とする半導体装置。
- 半導体装置の製造方法において、
(a)基材、前記基材に形成されたボンディングパッド、前記ボンディングパッドと繋がる導電性配線、前記導電性配線と繋がるランド、及び前記ランドと繋がるダミー配線を有する基板を準備する工程と、
(b)前記基板に接着部材を介して半導体素子を固着する工程と、
(c)前記半導体素子を樹脂で封止する工程と、
(d)前記基板の前記ランドにはんだ材を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、前記ダミー配線は、前記導電性配線と対向する方向に延在していることを特徴とする半導体装置の製造方法。
- 請求項8記載の半導体装置の製造方法において、前記(d)工程では、前記ランドに球状又はペースト状の前記はんだ材を配置した後、前記はんだ材を溶融させて前記ランドと接合させることを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008269173A JP5000621B2 (ja) | 2008-10-17 | 2008-10-17 | 半導体装置 |
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JP2008269173A JP5000621B2 (ja) | 2008-10-17 | 2008-10-17 | 半導体装置 |
Related Parent Applications (1)
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JP2003030314A Division JP2003224229A (ja) | 2003-02-07 | 2003-02-07 | ボールグリッドアレイ型半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2009010437A true JP2009010437A (ja) | 2009-01-15 |
JP5000621B2 JP5000621B2 (ja) | 2012-08-15 |
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JP2008269173A Expired - Fee Related JP5000621B2 (ja) | 2008-10-17 | 2008-10-17 | 半導体装置 |
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JP (1) | JP5000621B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9305895B2 (en) * | 2013-11-25 | 2016-04-05 | SK Hynix Inc. | Substrates having ball lands, semiconductor packages including the same, and methods of fabricating semiconductor packages including the same |
JP2020013996A (ja) * | 2018-07-13 | 2020-01-23 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 半導体パッケージ |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05275840A (ja) * | 1992-03-25 | 1993-10-22 | Matsushita Electric Ind Co Ltd | プリント配線板 |
JPH0669638A (ja) * | 1992-08-21 | 1994-03-11 | Unisia Jecs Corp | プリント配線板のランド部構造 |
JPH10200218A (ja) * | 1996-12-28 | 1998-07-31 | Casio Comput Co Ltd | 電子部品搭載用基板および電子部品搭載モジュール |
-
2008
- 2008-10-17 JP JP2008269173A patent/JP5000621B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05275840A (ja) * | 1992-03-25 | 1993-10-22 | Matsushita Electric Ind Co Ltd | プリント配線板 |
JPH0669638A (ja) * | 1992-08-21 | 1994-03-11 | Unisia Jecs Corp | プリント配線板のランド部構造 |
JPH10200218A (ja) * | 1996-12-28 | 1998-07-31 | Casio Comput Co Ltd | 電子部品搭載用基板および電子部品搭載モジュール |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9305895B2 (en) * | 2013-11-25 | 2016-04-05 | SK Hynix Inc. | Substrates having ball lands, semiconductor packages including the same, and methods of fabricating semiconductor packages including the same |
JP2020013996A (ja) * | 2018-07-13 | 2020-01-23 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 半導体パッケージ |
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JP5000621B2 (ja) | 2012-08-15 |
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