TWI495082B - 多層半導體封裝 - Google Patents

多層半導體封裝 Download PDF

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Publication number
TWI495082B
TWI495082B TW100105024A TW100105024A TWI495082B TW I495082 B TWI495082 B TW I495082B TW 100105024 A TW100105024 A TW 100105024A TW 100105024 A TW100105024 A TW 100105024A TW I495082 B TWI495082 B TW I495082B
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Taiwan
Prior art keywords
substrate
die
planar surface
major planar
encapsulating resin
Prior art date
Application number
TW100105024A
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English (en)
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TW201130110A (en
Inventor
Rajendra D Pendse
Original Assignee
Stats Chippac Inc
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Publication of TW201130110A publication Critical patent/TW201130110A/zh
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Publication of TWI495082B publication Critical patent/TWI495082B/zh

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Description

多層半導體封裝
本發明係關於半導體封裝。
電子裝置通常會運用多個半導體組件，例如數個微晶片。部份裝置可能會被設計成「多晶片模組」，其通常包括一印刷電路板(PCB)基板，於其上會直接附接一組分離的微晶片。此等多晶片模組能夠提高電路密度以及微型化結果，不過，它們的體積卻可能會非常龐大。
用以縮小多晶片模組之尺寸及從而提高它們的有效密度的其中一種方法係以垂直方式來堆疊晶粒或晶片。此方式的習知實施例有可以節省PCB上空間的封裝上封裝(package-on package，PoP)組態以及封裝中封裝(package-in package，PiP)組態。這些封裝可能為例如約為15mm平方的大小等級，高度約為2mm。
一些封裝設計會在晶粒上放置一中介層。舉例來說，授與Shim等人的美國專利案第6,861,288號揭示了：「一種用以製造堆疊式半導體封裝的方法，其包含提供一基板並且將一第一半導體裝置安置在該基板上。一中介層會被支撐在與基板反對的第一半導體裝置上方。該中介層會被電連接至該基板。接著，將第二半導體裝置安置在該中介層上。」參見發明摘要。不過，這種設計所造成的封裝面積卻可能會遠大於被封裝晶粒的面積。
鑒於上述，需要改良的半導體封裝與封裝方法。
一半導體封裝可能包括一基底基板，於該基底基板的頂側之上會安置半導體晶粒，而在該晶粒的頂部上會安置一中介層基板。該中介層基板的底側可能會經由垂直連接器被電耦合至基底基板的頂側。該中介層基板的頂側實質上會曝露出來，以便安置另外的電子組件。該等基底基板與中介層基板可能會配置輸入/輸出(I/O)終端，而使得安置在該等基板上的組件能夠經由垂直連接器而與彼此電耦合。該基底基板還可能會被電耦合至另外的電子組件，例如PCB。
於一實施例中，一半導體封裝包括：一第一基板，其具有由第一周圍所界定的第一主平面表面與第二主平面表面；一第一半導體晶粒，其被電耦合至該第一基板的第二主平面表面；一第二基板，其具有由第二周圍所界定的第一主平面表面與第二主平面表面；第一複數個垂直連接器，它們被配置成用以將該第二基板的第一主平面表面電耦合至該第一基板的第二主平面表面；以及一第一囊封樹脂，其係位在該半導體晶粒與該第一基板的第二表面之間，該囊封樹脂還涵蓋至少其中一些該等垂直連接器中的至少一部份，其中，該等垂直連接器實質上定位在該第一周圍與該第二周圍內，且其中，該第二基板的第二主平面表面實質上可用來容置一或多個電子組件。該第一半導體晶粒可能以倒裝晶片組態的方式被電耦合至該第一基板的第二主平面表面。於其它實施例中，該第一半導體晶粒則會利用至少一焊線被電耦合至該第一基板的第二主平面表面。
該封裝更可能包括一第二囊封樹脂，其係位在該第一基板的第二表面與該第二基板的第一表面之間。在一些實施例中，該第一囊封樹脂與該第二囊封樹脂包括一連續的囊封樹脂。於另外的實施例中，該等第一複數個垂直連接器中的至少其中之一包括一導線上焊接(bond-on-lead，BOL)連接線。於另外的實施例中，該等第一複數個垂直連接器中的至少其中之一包括一柱凸塊(stud bump)。在一些實施例中，該第一囊封樹脂包括以下至少其中之一：環氧樹脂材料、熱固性材料及熱塑性材料。
在一些實施例中，該第二基板的第二主平面表面係配置成用以容置一電子組件。該第二基板的第二主平面表面可能更會配置成用以容置一球柵陣列，該球柵陣列的至少一部份的球間距係介於約0.25mm與約1.0mm之間。於其它實施例中，該第二基板的第二主平面表面可能更會配置成用以容置以下至少其中之一：倒裝晶片組件、方形扁平封裝、無導線方形扁平封裝、模製封裝、或被動元件。在半導體封裝的其它實施例中，該第一周圍包括複數個周圍側，且其中，至少一些該等第一複數個垂直連接器係位於該等周圍側之中的兩側、三側、四側、或更多側處。在一些實施例中，至少一些該等第一複數個垂直連接器大體上係沿著該等第一周圍與第二周圍中至少其中之而正相反地相對。
在另外的實施例中，該第一基板具有一第一基板邊緣且該第一半導體晶粒具有一第一晶粒邊緣，且該第一晶粒邊緣與該第一基板邊緣之間的水平距離係介於約0.25mm與約1.5mm之間。在進一步實施例中，該距離係介於約0.25mm與約1.0mm之間。於其它實施例中，該水平距離約等於一垂直連接器的寬度。在進一步實施例中，介於該第一半導體晶粒面向該第一基板的表面以及該第二基板的第一主平面表面之間的垂直距離小於約0.2mm。
於其它實施例中，該半導體封裝更包括：一第三基板，其具有由第三周圍所界定的第一主平面表面與第二主平面表面；一第二半導體晶粒，其被電耦合至該第三基板的第二主平面表面；以及第二複數個垂直連接器，該等連接器會被配置成用以將該第一基板的第一主平面表面電耦合至該第三基板的第二主平面表面。
於另外的實施例中，一種製造半導體封裝的方法包括：提供一第一基板、一半導體晶粒、一第二基板、及一或多個垂直連接器，該等第一基板與第二基板兩者均具有第一主平面表面與第二主平面表面；經由該第一基板的第二主平面表面、該第二基板的第一主平面表面、以及至少其中一個該等一或多個垂直連接器將該晶粒電耦合至該第二基板的第二主平面表面，其中，電耦合該晶粒包括將至少一或多個垂直連接器耦合至該第一基板的第二主平面表面；以及在該晶粒與該第一基板之間提供一囊封樹脂，其中，係在將至少一或多個該等垂直連接器耦合至該第一基板的第二主平面表面之後才提供該囊封樹脂，且其中，該第二基板的第二主平面表面實質上可用來容置一或多個電子組件。該方法更可能包括在該第一基板與該第二基板之間提供一囊封樹脂。該囊封樹脂的一部份可能位於該晶粒與該第一基板之間，且一部份可能係位於該第一基板與該第二基板之間，該等部份實質上係同時提供的。在一些實施例中，係藉由以下製程來提供該囊封樹脂：印刷囊封製程；轉送模製製程；無流動底部封膠填充製程；或是其它模製製程、底部封膠製程、或囊封製程。
在該方法的一些實施例中，將晶粒電耦合至該第二基板的第二主平面表面可能包括：將該晶粒電耦合至該第一基板的第二主平面表面；以及經由該等一或多個垂直連接器來電耦合該第一基板的第二表面與該第二基板的第一表面。經由該第一基板的第二主平面表面來將晶粒電耦合至該第二基板的第二主平面表面可能包括利用複數個焊球來將該晶粒附接至該第一基板的第二主平面表面，且以約略同時方式來回填該等一或多個垂直連接器以及該等焊球。
在該方法的進一步實施例中，該第一基板具有一第一邊緣且該晶粒具有一第一邊緣，且其中，第一晶粒的該第一邊緣與第一基板的該第一邊緣之間的水平距離係介於約0.25mm與約1.5mm之間。在另外實施例中，該水平距離介於約0.25mm與約1.0mm之間。
在該方法的一些實施例中，附接該半導體晶粒及提供該第二基板等步驟係以實質同時的方式來實施。於其它實施例中，該方法更包括將一另外的半導體裝置電耦合至該第二基板的第二主平面表面。
本文所揭示之技術的其它實施例包含根據本文所揭示之方法的一或多個實施例所製成的半導體封裝。
在一些進一步實施例中，一半導體封裝包括：一第一基板，其具有由第一周圍所界定的第一主平面表面與第二主平面表面，該第二主平面表面具有耦合至該第二主平面表面的一半導體晶粒；以及一第二基板，其係由第二周圍所界定的第一主平面表面與第二主平面表面所組成，第二基板的第一主平面表面會藉由一或多個垂直連接器被有效地耦合至該第一基板的第二主平面表面，其中，該等垂直連接器實質上係定位在該第一周圍與該第二周圍內，其中，該第一基板具有一第一基板邊緣且該晶粒具有一第一晶粒邊緣，且其中，該第一晶粒邊緣與該第一基板邊緣之間的水平距離係介於約0.25mm與約1.5mm之間。
參考附圖，從以下的詳細說明中便會更明白本文所揭示之技術的前述與其它目的、特點及優點。
除非文中清楚表示，否則，本申請案及申請專利範圍中所使用的單數型式「一」及「該」等詞語亦包含複數型式。除此之外，「包含」一詞亦具有「包括」之意。進一步言之，「耦合」一詞所指的係以電氣方式、電磁方式、或機械方式被耦合或是被連結且並不排除在被耦合項目之間會有中間元件存在。
雖然為方便表達起見，本文係以特殊、循序順序的方式來說明本文所揭示方法之示範性實施例的操作，不過，應該瞭解的，本文所揭示之實施例仍可涵蓋本文所揭示之特殊、循序順序以外的操作順序。舉例來說，於一些情況中，可能會重新排列或是同時實施本文依序說明的操作。再者，為簡化起見，附圖可能並未顯示出本文所揭示之系統、方法及設備能夠配合其它系統、方法及設備來使用的各種方式(因為熟習本技術的人士依據本揭示內容便可輕易地察知)。除此之外，本說明有時候會使用「產生(produce)」以及「提供(provide)」之類的詞語來說明本文所揭示的方法。這些詞語均為能夠實施實際操作的上層抽象概念。舉例來說，「提供」一組件可能所指的係使得組件可與另外的組件來使用或配置。與該些詞語對應的實際操作則可能會隨著特殊的施行方式而改變，且熟習本技術的人士依據本揭示內容便可輕易地察知。
無論組件的定向為何，本文中所使用的「水平」一詞係被定義為在該適當組件之主要為平面的相對表面的平面之中。「垂直」一詞所指的是大體垂直本文所定義之水平方向的方向。「之上」、「上方」、「下方」、「底部」、「頂端」、「側邊」、「高於」、「低於」、以及「之下」之類的詞語則依照該水平平面來定義。
(半導體封裝的示範性實施例)
圖1係一半導體封裝100的一實施例的平面圖。該封裝100可能包括：一中介層基板110，其會相對於一半導體晶粒120而被有效地定位，例如被定位在該晶粒120的頂部(如圖中的虛線所示)；及一基底基板130。在一些實施例中，該等基板110與130具有約略相同的水平面積。於其它實施例中，它們可能具有實質不同的水平面積。圖1的實施例顯示出基板110略小於基板130。該中介層基板110可能包括一或多個I/O終端140，該等終端可依需要被排列成用以電耦合至晶粒120或基底基板130。
圖2係沿著圖1中的直線2-2所獲得之封裝100的側面剖面圖。如圖2所示，該中介層基板110包括由基板110邊緣所形成的周圍來界定的兩個主平面反向表面，也就是，頂表面112與底表面114。該基底基板130同樣包括由基板130邊緣所形成的周圍來界定的兩個主平面反向表面，也就是，頂表面132與底表面134。基底基板130可能包括一或多個I/O終端142，該等I/O終端142可能和中介層基板110的I/O終端140雷同(圖中的一些特徵，例如，終端140、142，係以簡化方式繪製以便更清楚地說明該等實施例的其它特徵)。該等終端140、142可能會配置成用以在一基板表面上的某一點及該表面上的另一點之間來攜載電信號，或是在兩個不同的基板表面之間攜載電信號。
在圖2的實施例中，晶粒120係被安置成倒裝晶片組態，其具有複數個焊球122或類似的電連接線來將該晶粒120電耦合至基底基板終端142的其中一個或多個。基底基板130可能會經由一或多個垂直連接器，例如代表性的垂直連接器150、154，而被電耦合至中介層基板110。依此方式，來自基底基板130的電連接線可將晶粒120「纏繞」於該中介層基板110周圍。在一些實施例中，垂直連接器150並不會水平延伸超越基板110、130邊緣，而允許產生緊密的封裝。
如圖1所示，封裝100可被建構成使得垂直連接器可以定位成接近封裝100的其中一個邊緣、兩個邊緣、三個邊緣、四個邊緣或更多邊緣，如垂直連接器150、152、154、156所示範解釋者。圖10係顯示被建構之封裝1000之示範性實施例的平面圖，使得垂直連接器係定位成接近封裝1000的五個邊緣(參見如垂直連接器1010、1020、1030、1040、1050)。下文將說明此等連接器的示範性實施例。如圖2所示，封裝100更可能包括一介於基板110、130之間以及介於該晶粒120與該等基板110、130的其中一或二者之間的材料160。在一些實施例中，材料160包括囊封樹脂並且係經由底部封膠製程(例如，針頭點膠製程、無流動底層填充製程)來塗敷。在本說明書以及申請專利範圍中使用的「囊封樹脂」一詞所指的是在封裝中的一種材料，該材料：大體上在二或多個組件之間界定一空間；用以至少部份填充一介於二或多個組件之間的間隙；及/或座落在其中一或多個基板的周圍處，用以至少部份界定一封裝的形狀及/或密封該封裝的一區域。該囊封樹脂可能會提供：例如，預定的導熱性；預定的導電性；及用以阻擋環境污染物的屏障。舉例來說，可以使用下面一些合宜的材料來作為該囊封樹脂：環氧樹脂材料、熱固性材料及熱塑性材料。在一些實施例中，這些材料會與填料顆粒一起使用；而於其它實施例中，它們並不需要與填料顆粒一起使用。於其它實施例中，係利用包覆成型囊封製程來塗敷材料160(為更清楚地看見基底基板130，圖1中並未顯示材料160)。可以提供焊球170或其它電連接線來將基底基板130電耦合至其它電路元件或組件，例如，印刷電路板。
封裝100可被建構成用以使得封裝100在一安置表面(例如，印刷電路板)上所佔據的面積僅會略大於晶粒120的水平面積。在一些實施例中，介於晶粒120邊緣124與基底基板130邊緣136(或是同樣地中介層基板110邊緣)之間的距離d2係介於約0.25mm與約1mm之間。在一些晶片級封裝(CSP)設計中的類似距離則可能介於約2mm與約3mm之間。不過，封裝100亦可被設計成使其面積遠大於晶粒120的面積。於進一步實施例中，封裝100可能包括多個半導體封裝(圖中並未顯示)，該等半導體封裝會被定位在該基底基板130之上且被電耦合至該基底基板130。
於其它實施例中，基板110的頂表面112係至少部份地被一被耦合至終端140、142的另外半導體晶粒(或其它電子組件)所佔據。圖11係顯示封裝1100之示範性實施例的側面剖面圖，該封裝1100包括部分1110並且類似於封裝100。該封裝1100進一步包括一另外基板1120(可能類似於基板110、130)定位在另外晶粒1130的頂部，而垂直連接器1140、1142(可能與垂直連接器150、152、154、156相似)係將該另外的基板1120電耦合至終端140、142。因此，封裝1100可能包括被夾設在多層基板之間的多個晶粒。
一些組態的封裝100的一項優點係I/O終端可被配置成顯露在該封裝的頂表面與底表面二者上。除此之外，中介層基板110的大部份或全部的頂表面112可供終端140使用。頂表面112可能呈現出平坦或約略平坦的安置表面，而其它封裝有時候則會具有隆起的特徵，例如中斷安置表面的晶粒鑄模罩。該封裝100的這些特徵可能有助於對多個半導體組件進行三維整合。
於另外的實施例中，圖3說明封裝100的側面剖面圖，於該封裝100的頂部上安置著一電子組件180。電子組件180可能會經由中介層基板110之頂表面112處的一或多個終端140被電耦合至封裝100。於一實施例中，終端140、142及垂直連接器150、152、154、156可被建構成用以電耦合該電子組件180與該晶粒120。於另一實施例中，終端140、142及垂直連接器150可被建構成用以在該電子組件180與複數個焊球170之間提供一或多條電連接線。於另外的實施例中，終端140、142及垂直連接器150可被建構成用以在該電子組件180、該晶粒120、以及該等焊球170之間產生電連接。
在一些實施例中，封裝100的晶粒120係一微處理器或其它微晶片；而該電子組件180則係一含有一能夠結合晶粒120來運作之記憶體元件的封裝。於其它實施例中，電子組件180包括例如一或多個另外的處理器、一或多個離散組件(例如，被動式或主動式)、一倒裝晶片組件、一方形扁平封裝(QFP)、一無導線方形扁平封裝(QFN)、一成型封裝、或是它們的組合。
圖3所示的電子組件180包括一用以連接至中介層基板110的球柵陣列(BGA)182。一些半導體封裝會沿著封裝的周圍區域提供安置表面用以收納BGA，於該安置表面的中央或附近會有一隆起的特徵(例如，用於封裝之中的晶粒的鑄模套)。當使用BGA的另外裝置安置在此封裝上時，該BGA的球間距經常會經過選擇，以便足夠大而可以將該另外裝置抬昇於該隆起特徵上方。舉例來說，於此等裝置中，該球間距可能約為0.65mm。在圖3的封裝100的一些實施例中，中介層基板110的大體水平頂表面112並不需要電子組件180的BGA 182將該電子組件180抬昇於一隆起區域上方。據此，該BGA 182的間距可能會小於至少部份先前技術設計。此較小的BGA間距可能會產生較小的總封裝高度(例如，在一些實施例中，從該基板130的底表面134至該基板110的頂表面112約0.28mm)以及較高密度的BGA 182。舉例來說，在一些實施例中，該球間距可能介於約0.25mm與約0.3mm之間；不過，於其它實施例中，該球間距可能會較小或較大。在一些另外的實施例中，該電子組件180可能會利用焊線技術或是本技術中已知的其它技術被連接至該基板110。於封裝100的替代實施例中，中介層基板110的頂表面112可能包括一或多個隆起的特徵。
圖4為半導體封裝400的側面剖面圖。於此實施例中，封裝400相似於封裝100。不過，對圖4的實施例來說，晶粒420並不會被配置成倒裝晶片，而會被配置成一焊線結合的晶粒，其中，焊線444、446會將晶粒420電耦合至一基抵基板430。在封裝400的頂部上可以安置一半導體封裝480(或其它電子組件)。圖12係半導體封裝1200之進一步示範性實施例的側面剖面圖。此實施例相似於封裝400係因為該半導體封裝1200包括以焊線組態被耦合至基板1230之表面1220的晶粒1210。在此封裝1200中，該晶粒1210係藉由囊封樹脂1240層而至少部分從基板表面1220分離。
垂直連接器150有數種實施例可以用在該等封裝100、400之中。圖5係圖2中區域190的放大圖，其係顯示用以電耦合一中介層基板510與一基底基板530的垂直連接器550的實施例。在此放大圖中還顯示出一囊封樹脂(例如，環氧樹脂材料、熱固性材料、或熱塑性材料)560及一晶粒520，該晶粒520係藉由一或多個焊球522或類似的連接器被電耦合至基底基板530。舉例來說，包括黏著劑的一附接層524可能會在基板510與晶粒520之間提供實體連接作用。在圖5所示之封裝的一些實施例中(及在下文圖6與圖7所示之封裝的一些實施例中)，取而代之的係，被例如附接層524的一層體所佔據的空間則可能會利用一成型化合物來填充。不過，為讓該成型化合物可以穿透此區域，應該要在晶粒520的頂部與中介層基板510的底部之間為該成型作業提供足夠的餘隙。必要的「成型餘隙」通常至少約0.2mm。因此，在一些實施例中，可因為不將成型化合物放置在晶粒520頂部與中介層基板510底部之間而縮減封裝高度。圖中所示之實施例中進一步顯示出，垂直連接器550包括一導體焊珠552，其會被電耦合至該中介層基板510上的一導體痕跡556。焊珠552也會被電耦合至一導電基底，例如導線554，用以構成導線上焊接(BOL)的連接。導線554可能進一步被電耦合至基底基板530上的導體痕跡558。焊珠552可能包括一或多個導體材料，例如金或焊錫，且可以使用觸點上焊接(SOP)技術被塗敷至痕跡556，或者亦可被耦合至痕跡556。
圖6為圖2區域190的放大圖，其顯示用以電耦合一中介層基板610與一基底基板630的垂直連接器650的進一步實施例。在此放大圖中亦顯示出一囊封樹脂(例如，環氧樹脂材料、熱固性材料、或是熱塑性材料)660以及一晶粒620，該晶粒620會藉由一或多個焊球622或類似的連接器被電耦合至基底基板630。舉例來說，一包括黏著劑的附接層624可能會在基板610與晶粒620之間提供實體連接作用。於此實施例中，該垂直連接器650包括一導體焊珠652，其會被電耦合至該中介層基板610之上的一導體痕跡656。焊珠652可能包括一或多個導體材料，例如金或焊錫，並且可以使用本項技術中所熟知的觸點上焊接(solder-on-pad，SOP)技術被塗敷至痕跡656。焊珠652亦可被電耦合至一導電基底，例如柱凸塊654，其可能包括本技術中已知 的數種不同柱凸塊材料。在一些實施例中，該柱凸塊654係由金所構成。該柱凸塊654可能進一步被電耦合至基底基板630之上的一導體痕跡658。
圖7係圖2中區域190的另外實施例。此實施例顯示出一焊球750，其做為一基底基板730與一中介層基板710之間的垂直連接器。該焊球750會被電耦合至該中介層基板710上的一導體痕跡756並且會被電耦合至該基底基板730上的一導體痕跡758。在此放大圖中也顯示出一晶粒720，其會利用一或多個焊球722和類似的連接器被電耦合至基底基板730；在此放大圖中亦顯示出一囊封樹脂(例如，環氧樹脂材料、熱固性材料、或熱塑性材料)760。舉例來說，一包括黏著劑的附接層724可能會在基板710與晶粒720之間提供實體連接作用。
一給定的封裝組態可被建構成用以使用上文所述之垂直連接器實施例中的其中之一或多者以及其它類型的垂直連接器。
相較於使用圖7中所示之垂直連接器的封裝，使用圖5與圖6中所示之垂直連接器的封裝可被建構成更加精簡。相較於圖7的垂直連接器所使用的對應痕跡(例如，痕跡756、758)，圖5與圖6的垂直連接器實施例可被建構成使用較小的痕跡(例如，圖5的痕跡556、558以及圖6的痕跡656、658)。據此，圖5與圖6的垂直連接器能夠在給定的基板空間中達成經改良的路徑選擇效率，並且允許在該晶粒的邊緣與最大基板(在圖5至圖7的實施例中最大基板分別為基底基板530、630、730)的邊緣之間有較短的距離d。圖5、圖6及圖7所示的距離d分別為d5 、d6 及d7 。在所示的實施例中，d7 >d5 且d7 >d6 。距離d可能約與一垂直連接器的寬度相同。因此，這便能夠讓一封裝的水平尺寸接近被封裝晶粒的水平尺寸。
(本文揭示方法的示範性實施例)
圖8所示的係製造半導體封裝的方法800之示範性實施例的流程圖。在步驟810之中會提供封裝組件。這些組件可能包含一基底基板、一中介層基板、一半導體晶粒及一或多個垂直連接器。基底基板與中介層基板二者均具有一頂表面與一底表面。在一些實施例中，可能會同時或約略同時的方式來提供一或多個組件。舉例來說，可能會同時提供垂直連接器及中介層基板。在步驟820之中，晶粒則會被電耦合至該中介層基板的頂表面。
圖9係用以實施圖8步驟820的方法之實施例的流程圖。該方法包括將晶粒電耦合至基底基板的頂表面(步驟910)。如上文所述，晶粒與基底基板可能會利用本技術中已知的數種組態，例如焊線結合組態或是倒裝晶片組態，而被電耦合。可能會形成一或多個垂直連接器(例如，在基底基板的頂表面上、在中介層基板的底表面上、或兩者)(步驟920)。基底基板與中介層基板兩者可能會經由垂直連接器被電耦合(步驟930)。於進一步實施例中，可能會與被耦合至基底基板的晶粒同時或約略同時藉由拾放製程(pick-and-place process)來提供該中介層基板。
回來參照圖8，在另外的實施例中，方法800必要時可能進一步包括一或多道回填步驟830。對具有運用倒裝晶片組態之晶粒的封裝及對具有運用圖5至圖7所述之垂直連接器組態的封裝來說，可能會使用再填充步驟。在一些實施例中，可能會在放置晶粒之後進行第一次回填步驟，且可能會在放置中介層基板之後進行第二次回填步驟。於其它實施例中，可能會對介於基底基板與中介層基板之間的晶粒與垂直連接器兩者使用單一回填步驟。
於其它實施例中，方法800必要時可能進一步包括一或多道底部封膠填充步驟840。在一些實施例中，倘若晶粒係以倒裝晶片組態的方式被電耦合至基底基板的話，那麼如本技術中所熟知的，便可以使用囊封樹脂(例如，環氧樹脂材料、熱固性材料或熱塑性材料)來對該晶粒進行底部封膠填充。亦可能在稍後的另外步驟中對介於該中介層基板與該基底基板之間的空間進行底部封膠填充。當對倒裝晶片進行底部封膠填充時，囊封樹脂可能會在沿著基底基板的頂表面延伸出去的晶片邊緣附近產生填角。倘若在形成填角之後增加垂直連接器的話，便可將該等垂直連接器放置在填角周圍外側。不過，這卻會增加基底基板的頂表面上使用的空間大小，且無法使用在填角下方的表面(有時候稱為「禁制區(keep-out region)」)。此組態可能需要較大的基板且因而會提高封裝的尺寸。多道底部封膠填充步驟可能會在不同底部封膠填充步驟的材料之間造成一或多個界面。在一些實施例中，會在垂直連接器處於適當位置(在一些實施例中，會使得囊封樹脂可以包圍一些垂直連接器中的至少一部份)之後對該倒裝晶片以及該中介層基板同時進行底部封膠填充。這能夠減少底層填充步驟840的數目，且可讓垂直連接器的放置位置更接近晶粒(可能可達成較小的封裝尺寸)。
對於晶粒以焊線結合組態被耦合至基底基板的實施例來說，底部封膠填充步驟840可能包括對介於晶粒面與基底基板之間的空間以及介於中介層基板與基底基板之間的空間進行底部封膠填充。於其它實施例中，底部封膠填充步驟840可能包括(在放置中介層基板之前)經由印刷囊封法利用囊封樹脂來覆蓋晶粒(例如，藉由在晶粒頂部印刷一層材料)。於此等實施例中，可能會在該中介層基板上形成至少一部份垂直連接器，並且中介層基板可被放置成(步驟830)讓垂直連接器會被推過已印刷的囊封樹脂，從而讓中介層基板變成被電耦合至基底基板。接著便可以提供回填步驟830。
於進一步實施例中，另外的半導體組件可以與中介層基板的頂表面電耦合(步驟850)。此步驟可以獨立於任何底部封膠填充步驟或回填步驟來完成。
本文所揭示的材料與結構以及用於製造與使用此等材料與結構之方法的實施例均不應被視為具有任何限制意義。反而是，本揭示內容係針對本文所揭示之各種實施例所有新穎且非顯而易見的特點、觀點、以及同等物之單獨的或與彼此的各種組合以及子組合。本文所揭示之技術並不受限於任何特定觀點、特點、或是其組合，而所揭示的材料、結構及方法亦不需要具有任何一或多項特定優點存在或解決任何問題。本發明主張下面申請專利範圍所涵蓋的全部範圍。
100、400、480．．．半導體封裝
110、510、610、710．．．中介層基板
112．．．中介層基板頂表面
114．．．中介層基板底表面
120．．．半導體晶粒
122、170、622、722、750．．．焊球
124．．．晶粒邊緣
130、430、530、630、730．．．基底基板
132．．．基底基板頂表面
134．．．基底基板底表面
136．．．基底基板邊緣
140、142．．．輸入/輸出終端
150、152、154、156、550、650、1010、1020、1030、1040、1050、1140、1142．．．垂直連接器
160．．．材料
180．．．電子組件
182．．．球柵陣列
190．．．半導體封裝中的一些區域
420、520、620、720、1130．．．晶粒
444、446、522．．．焊線
524、624、724．．．附接層
552、652．．．導體焊珠
554．．．導線
556、558、656、658、756、758．．．導體痕跡
560、660、760、1240．．．囊封樹脂
654．．．柱凸塊
1000、1100．．．封裝
1110．．．部分
1120、1230．．．基板
1200．．．半導體封裝
1210．．．晶粒
1220．．．表面
圖1係半導體封裝之實施例的平面圖；
圖2係說明圖1之封裝的側面剖面圖；
圖3係說明具有另外半導體封裝的圖1之封裝的側面剖面圖；
圖4所示的係本發明所揭示之半導體封裝的替代實施例的側面剖面圖；
圖5係垂直連接器一實施例的放大剖面圖；
圖6係垂直連接器一實施例的放大剖面圖；
圖7係垂直連接器一實施例的放大剖面圖；
圖8係製造半導體封裝的方法之一實施例的流程圖；
圖9係將晶粒電耦合至中介層基板的頂部表面的方法之一實施例的流程圖；
圖10係半導體封裝之實施例的平面圖；
圖11係半導體封裝之實施例的側面剖面圖；及
圖12係半導體封裝之實施例的側面剖面圖。
100．．．半導體封裝
110．．．中介層基板
120．．．半導體晶粒
130．．．基底基板
140．．．輸入/輸出終端
150．．．垂直連接器
152．．．垂直連接器
154．．．垂直連接器
156．．．垂直連接器

Claims (15)

  1. 一種製造半導體封裝的方法，該方法包括：提供一第一基板、一半導體晶粒、一第二基板、以及一或多個垂直連接器，該等第一基板與第二基板兩者均具有第一主平面表面與第二主平面表面；經由該第一基板的第二主平面表面、該第二基板的第一主平面表面、以及至少其中一個該等一或多個垂直連接器將該晶粒電耦合至該第二基板的第二主平面表面，其中，電耦合該晶粒包括將至少一或多個垂直連接器耦合至該第一基板的第二主平面表面；以及在該晶粒與該第一基板之間提供一囊封樹脂，其中，係在將至少一或多個該等垂直連接器耦合至該第一基板的第二主平面表面之後才提供該囊封樹脂，其中，該垂直連接器包括電耦合至導電基底之導體焊珠，且其中，該第二基板的第二主平面表面實質上可用來接收一或多個電子組件。
  2. 如申請專利範圍第1項所述之方法，其中，其進一步包括在該第一基板與該第二基板之間提供一囊封樹脂。
  3. 如申請專利範圍第2項所述之方法，其中，該囊封樹脂的至少其中一些係藉由印刷囊封製程來提供。
  4. 如申請專利範圍第2項所述之方法，其中，該囊封樹脂的至少其中一些係藉由轉移成型製程來提供。
  5. 如申請專利範圍第2項所述之方法，其中，該囊封樹脂的至少其中一些係藉由無流動底部封膠填充點膠製程 來提供。
  6. 如申請專利範圍第2項所述之方法，其中，該囊封樹脂的其中至少一些係藉由底部封膠填充製程來提供。
  7. 如申請專利範圍第2項所述之方法，其中，會同時提供該囊封樹脂之位於該晶粒與該第一基板之間的一部份以及該囊封樹脂之位於該第一基板與該第二基板之間的一部份。
  8. 如申請專利範圍第2項所述之方法，其中，會在一道步驟中提供該囊封樹脂之位於該晶粒與該第一基板之間的一部份以及該囊封樹脂之位於該第一基板與該第二基板之間的一部份。
  9. 如申請專利範圍第1項所述之方法，其中，將該晶粒電耦合至該第二基板的第二主平面表面包括：將該晶粒電耦合至該第一基板的第二主平面表面；及經由該等一或多個垂直連接器來電耦合該第一基板的第二表面與該第二基板的第一表面。
  10. 如申請專利範圍第1項所述之方法，其中，經由該第一基板的第二主平面表面來將該晶粒電耦合至該第二基板的第二主平面表面包括：利用複數個焊球來將該晶粒附接至該第一基板的第二主平面表面；以及以約略同時的方式來回填該等一或多個垂直連接器以及該等焊球。
  11. 如申請專利範圍第1項所述之方法，其中，該第一基板具有一第一邊緣且該晶粒具有一第一邊緣，且其中，該晶粒的該第一邊緣與該第一基板的該第一邊緣之間的水平距離係介於約0.25mm與約1.5mm之間。
  12. 如申請專利範圍第11項所述之方法，其中，該晶粒的該第一邊緣與該第一基板的該第一邊緣之間的水平距離係介於約0.25mm與約1.0mm之間。
  13. 如申請專利範圍第1項所述之方法，其中，附接該半導體晶粒以及提供該第二基板等步驟係以實質同時的方式來實施。
  14. 如申請專利範圍第1項所述之方法，其進一步包括將一另外的半導體裝置電耦合至該第二基板的第二主平面表面。
  15. 如申請專利範圍第1項所述之方法，其中，該導電基底包括導線或柱凸塊。
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US7608921B2 (en) 2009-10-27
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JP2012235170A (ja) 2012-11-29
US20080136003A1 (en) 2008-06-12
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